RubyPort.cc revision 11266
16876Ssteve.reinhardt@amd.com/* 210089Sandreas.hansson@arm.com * Copyright (c) 2012-2013 ARM Limited 38922Swilliam.wang@arm.com * All rights reserved. 48922Swilliam.wang@arm.com * 58922Swilliam.wang@arm.com * The license below extends only to copyright in the software and shall 68922Swilliam.wang@arm.com * not be construed as granting a license to any other intellectual 78922Swilliam.wang@arm.com * property including but not limited to intellectual property relating 88922Swilliam.wang@arm.com * to a hardware implementation of the functionality of the software 98922Swilliam.wang@arm.com * licensed hereunder. You may use the software subject to the license 108922Swilliam.wang@arm.com * terms below provided that you ensure that this notice is replicated 118922Swilliam.wang@arm.com * unmodified and in its entirety in all distributions of the software, 128922Swilliam.wang@arm.com * modified or unmodified, in source code or in binary form. 138922Swilliam.wang@arm.com * 1411266SBrad.Beckmann@amd.com * Copyright (c) 2009-2013 Advanced Micro Devices, Inc. 158717Snilay@cs.wisc.edu * Copyright (c) 2011 Mark D. Hill and David A. Wood 166876Ssteve.reinhardt@amd.com * All rights reserved. 176876Ssteve.reinhardt@amd.com * 186876Ssteve.reinhardt@amd.com * Redistribution and use in source and binary forms, with or without 196876Ssteve.reinhardt@amd.com * modification, are permitted provided that the following conditions are 206876Ssteve.reinhardt@amd.com * met: redistributions of source code must retain the above copyright 216876Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer; 226876Ssteve.reinhardt@amd.com * redistributions in binary form must reproduce the above copyright 236876Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer in the 246876Ssteve.reinhardt@amd.com * documentation and/or other materials provided with the distribution; 256876Ssteve.reinhardt@amd.com * neither the name of the copyright holders nor the names of its 266876Ssteve.reinhardt@amd.com * contributors may be used to endorse or promote products derived from 276876Ssteve.reinhardt@amd.com * this software without specific prior written permission. 286876Ssteve.reinhardt@amd.com * 296876Ssteve.reinhardt@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306876Ssteve.reinhardt@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316876Ssteve.reinhardt@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326876Ssteve.reinhardt@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336876Ssteve.reinhardt@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346876Ssteve.reinhardt@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356876Ssteve.reinhardt@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366876Ssteve.reinhardt@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376876Ssteve.reinhardt@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386876Ssteve.reinhardt@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396876Ssteve.reinhardt@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406876Ssteve.reinhardt@amd.com */ 416876Ssteve.reinhardt@amd.com 427632SBrad.Beckmann@amd.com#include "cpu/testers/rubytest/RubyTester.hh" 438688Snilay@cs.wisc.edu#include "debug/Config.hh" 449152Satgutier@umich.edu#include "debug/Drain.hh" 458232Snate@binkert.org#include "debug/Ruby.hh" 468436SBrad.Beckmann@amd.com#include "mem/protocol/AccessPermission.hh" 477039Snate@binkert.org#include "mem/ruby/slicc_interface/AbstractController.hh" 486285Snate@binkert.org#include "mem/ruby/system/RubyPort.hh" 4910525Snilay@cs.wisc.edu#include "mem/simple_mem.hh" 5010117Snilay@cs.wisc.edu#include "sim/full_system.hh" 518923Sandreas.hansson@arm.com#include "sim/system.hh" 526285Snate@binkert.org 536876Ssteve.reinhardt@amd.comRubyPort::RubyPort(const Params *p) 5410919Sbrandon.potter@amd.com : MemObject(p), m_ruby_system(p->ruby_system), m_version(p->version), 5510919Sbrandon.potter@amd.com m_controller(NULL), m_mandatory_q_ptr(NULL), 5610919Sbrandon.potter@amd.com m_usingRubyTester(p->using_ruby_tester), system(p->system), 5710090Snilay@cs.wisc.edu pioMasterPort(csprintf("%s.pio-master-port", name()), this), 5810090Snilay@cs.wisc.edu pioSlavePort(csprintf("%s.pio-slave-port", name()), this), 5910090Snilay@cs.wisc.edu memMasterPort(csprintf("%s.mem-master-port", name()), this), 6010090Snilay@cs.wisc.edu memSlavePort(csprintf("%s-mem-slave-port", name()), this, 6111266SBrad.Beckmann@amd.com p->ruby_system->getAccessBackingStore(), -1, 6211266SBrad.Beckmann@amd.com p->no_retry_on_stall), 6310913Sandreas.sandberg@arm.com gotAddrRanges(p->port_master_connection_count) 646876Ssteve.reinhardt@amd.com{ 656876Ssteve.reinhardt@amd.com assert(m_version != -1); 666876Ssteve.reinhardt@amd.com 678922Swilliam.wang@arm.com // create the slave ports based on the number of connected ports 688922Swilliam.wang@arm.com for (size_t i = 0; i < p->port_slave_connection_count; ++i) { 6910090Snilay@cs.wisc.edu slave_ports.push_back(new MemSlavePort(csprintf("%s.slave%d", name(), 7011266SBrad.Beckmann@amd.com i), this, p->ruby_system->getAccessBackingStore(), 7111266SBrad.Beckmann@amd.com i, p->no_retry_on_stall)); 728922Swilliam.wang@arm.com } 737039Snate@binkert.org 748922Swilliam.wang@arm.com // create the master ports based on the number of connected ports 758922Swilliam.wang@arm.com for (size_t i = 0; i < p->port_master_connection_count; ++i) { 7610090Snilay@cs.wisc.edu master_ports.push_back(new PioMasterPort(csprintf("%s.master%d", 7710090Snilay@cs.wisc.edu name(), i), this)); 788922Swilliam.wang@arm.com } 796876Ssteve.reinhardt@amd.com} 806876Ssteve.reinhardt@amd.com 817039Snate@binkert.orgvoid 827039Snate@binkert.orgRubyPort::init() 836882SBrad.Beckmann@amd.com{ 846882SBrad.Beckmann@amd.com assert(m_controller != NULL); 856882SBrad.Beckmann@amd.com m_mandatory_q_ptr = m_controller->getMandatoryQueue(); 866882SBrad.Beckmann@amd.com} 876882SBrad.Beckmann@amd.com 889294Sandreas.hansson@arm.comBaseMasterPort & 899294Sandreas.hansson@arm.comRubyPort::getMasterPort(const std::string &if_name, PortID idx) 906876Ssteve.reinhardt@amd.com{ 9110090Snilay@cs.wisc.edu if (if_name == "mem_master_port") { 9210090Snilay@cs.wisc.edu return memMasterPort; 9310090Snilay@cs.wisc.edu } 9410090Snilay@cs.wisc.edu 9510090Snilay@cs.wisc.edu if (if_name == "pio_master_port") { 9610090Snilay@cs.wisc.edu return pioMasterPort; 978922Swilliam.wang@arm.com } 988922Swilliam.wang@arm.com 998839Sandreas.hansson@arm.com // used by the x86 CPUs to connect the interrupt PIO and interrupt slave 1008839Sandreas.hansson@arm.com // port 1018922Swilliam.wang@arm.com if (if_name != "master") { 1028922Swilliam.wang@arm.com // pass it along to our super class 1038922Swilliam.wang@arm.com return MemObject::getMasterPort(if_name, idx); 1048922Swilliam.wang@arm.com } else { 1059294Sandreas.hansson@arm.com if (idx >= static_cast<PortID>(master_ports.size())) { 1068922Swilliam.wang@arm.com panic("RubyPort::getMasterPort: unknown index %d\n", idx); 1078922Swilliam.wang@arm.com } 1088839Sandreas.hansson@arm.com 1098922Swilliam.wang@arm.com return *master_ports[idx]; 1108839Sandreas.hansson@arm.com } 1118922Swilliam.wang@arm.com} 1128839Sandreas.hansson@arm.com 1139294Sandreas.hansson@arm.comBaseSlavePort & 1149294Sandreas.hansson@arm.comRubyPort::getSlavePort(const std::string &if_name, PortID idx) 1158922Swilliam.wang@arm.com{ 11610090Snilay@cs.wisc.edu if (if_name == "mem_slave_port") { 11710090Snilay@cs.wisc.edu return memSlavePort; 11810090Snilay@cs.wisc.edu } 11910090Snilay@cs.wisc.edu 12010090Snilay@cs.wisc.edu if (if_name == "pio_slave_port") 12110090Snilay@cs.wisc.edu return pioSlavePort; 12210090Snilay@cs.wisc.edu 1238922Swilliam.wang@arm.com // used by the CPUs to connect the caches to the interconnect, and 1248922Swilliam.wang@arm.com // for the x86 case also the interrupt master 1258922Swilliam.wang@arm.com if (if_name != "slave") { 1268922Swilliam.wang@arm.com // pass it along to our super class 1278922Swilliam.wang@arm.com return MemObject::getSlavePort(if_name, idx); 1288922Swilliam.wang@arm.com } else { 1299294Sandreas.hansson@arm.com if (idx >= static_cast<PortID>(slave_ports.size())) { 1308922Swilliam.wang@arm.com panic("RubyPort::getSlavePort: unknown index %d\n", idx); 1318922Swilliam.wang@arm.com } 1328922Swilliam.wang@arm.com 1338922Swilliam.wang@arm.com return *slave_ports[idx]; 1347039Snate@binkert.org } 1356876Ssteve.reinhardt@amd.com} 1366882SBrad.Beckmann@amd.com 13710090Snilay@cs.wisc.eduRubyPort::PioMasterPort::PioMasterPort(const std::string &_name, 1386882SBrad.Beckmann@amd.com RubyPort *_port) 13910713Sandreas.hansson@arm.com : QueuedMasterPort(_name, _port, reqQueue, snoopRespQueue), 14010713Sandreas.hansson@arm.com reqQueue(*_port, *this), snoopRespQueue(*_port, *this) 1416882SBrad.Beckmann@amd.com{ 14210090Snilay@cs.wisc.edu DPRINTF(RubyPort, "Created master pioport on sequencer %s\n", _name); 1436882SBrad.Beckmann@amd.com} 1446882SBrad.Beckmann@amd.com 14510090Snilay@cs.wisc.eduRubyPort::PioSlavePort::PioSlavePort(const std::string &_name, 14610090Snilay@cs.wisc.edu RubyPort *_port) 14710090Snilay@cs.wisc.edu : QueuedSlavePort(_name, _port, queue), queue(*_port, *this) 14810090Snilay@cs.wisc.edu{ 14910090Snilay@cs.wisc.edu DPRINTF(RubyPort, "Created slave pioport on sequencer %s\n", _name); 15010090Snilay@cs.wisc.edu} 15110090Snilay@cs.wisc.edu 15210090Snilay@cs.wisc.eduRubyPort::MemMasterPort::MemMasterPort(const std::string &_name, 15310090Snilay@cs.wisc.edu RubyPort *_port) 15410713Sandreas.hansson@arm.com : QueuedMasterPort(_name, _port, reqQueue, snoopRespQueue), 15510713Sandreas.hansson@arm.com reqQueue(*_port, *this), snoopRespQueue(*_port, *this) 15610090Snilay@cs.wisc.edu{ 15710090Snilay@cs.wisc.edu DPRINTF(RubyPort, "Created master memport on ruby sequencer %s\n", _name); 15810090Snilay@cs.wisc.edu} 15910090Snilay@cs.wisc.edu 16010090Snilay@cs.wisc.eduRubyPort::MemSlavePort::MemSlavePort(const std::string &_name, RubyPort *_port, 16111266SBrad.Beckmann@amd.com bool _access_backing_store, PortID id, 16211266SBrad.Beckmann@amd.com bool _no_retry_on_stall) 16310089Sandreas.hansson@arm.com : QueuedSlavePort(_name, _port, queue, id), queue(*_port, *this), 16411266SBrad.Beckmann@amd.com access_backing_store(_access_backing_store), 16511266SBrad.Beckmann@amd.com no_retry_on_stall(_no_retry_on_stall) 1666882SBrad.Beckmann@amd.com{ 16710090Snilay@cs.wisc.edu DPRINTF(RubyPort, "Created slave memport on ruby sequencer %s\n", _name); 1686882SBrad.Beckmann@amd.com} 1696882SBrad.Beckmann@amd.com 17010089Sandreas.hansson@arm.combool 17110090Snilay@cs.wisc.eduRubyPort::PioMasterPort::recvTimingResp(PacketPtr pkt) 17210090Snilay@cs.wisc.edu{ 17310919Sbrandon.potter@amd.com RubyPort *rp = static_cast<RubyPort *>(&owner); 17410090Snilay@cs.wisc.edu DPRINTF(RubyPort, "Response for address: 0x%#x\n", pkt->getAddr()); 17510090Snilay@cs.wisc.edu 17610090Snilay@cs.wisc.edu // send next cycle 17710919Sbrandon.potter@amd.com rp->pioSlavePort.schedTimingResp( 17810919Sbrandon.potter@amd.com pkt, curTick() + rp->m_ruby_system->clockPeriod()); 17910090Snilay@cs.wisc.edu return true; 18010090Snilay@cs.wisc.edu} 18110090Snilay@cs.wisc.edu 18210090Snilay@cs.wisc.edubool RubyPort::MemMasterPort::recvTimingResp(PacketPtr pkt) 18310089Sandreas.hansson@arm.com{ 18410089Sandreas.hansson@arm.com // got a response from a device 18510089Sandreas.hansson@arm.com assert(pkt->isResponse()); 1866882SBrad.Beckmann@amd.com 18710090Snilay@cs.wisc.edu // First we must retrieve the request port from the sender State 18810090Snilay@cs.wisc.edu RubyPort::SenderState *senderState = 18910090Snilay@cs.wisc.edu safe_cast<RubyPort::SenderState *>(pkt->popSenderState()); 19010090Snilay@cs.wisc.edu MemSlavePort *port = senderState->port; 19110090Snilay@cs.wisc.edu assert(port != NULL); 19210090Snilay@cs.wisc.edu delete senderState; 1937039Snate@binkert.org 19410657Sandreas.hansson@arm.com // In FS mode, ruby memory will receive pio responses from devices 19510657Sandreas.hansson@arm.com // and it must forward these responses back to the particular CPU. 19610657Sandreas.hansson@arm.com DPRINTF(RubyPort, "Pio response for address %#x, going to %s\n", 19710657Sandreas.hansson@arm.com pkt->getAddr(), port->name()); 19810657Sandreas.hansson@arm.com 19910089Sandreas.hansson@arm.com // attempt to send the response in the next cycle 20010919Sbrandon.potter@amd.com RubyPort *rp = static_cast<RubyPort *>(&owner); 20110919Sbrandon.potter@amd.com port->schedTimingResp(pkt, curTick() + rp->m_ruby_system->clockPeriod()); 2027039Snate@binkert.org 2036882SBrad.Beckmann@amd.com return true; 2046882SBrad.Beckmann@amd.com} 2056882SBrad.Beckmann@amd.com 2066882SBrad.Beckmann@amd.combool 20710090Snilay@cs.wisc.eduRubyPort::PioSlavePort::recvTimingReq(PacketPtr pkt) 2086882SBrad.Beckmann@amd.com{ 20910090Snilay@cs.wisc.edu RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 21010090Snilay@cs.wisc.edu 21110090Snilay@cs.wisc.edu for (size_t i = 0; i < ruby_port->master_ports.size(); ++i) { 21210090Snilay@cs.wisc.edu AddrRangeList l = ruby_port->master_ports[i]->getAddrRanges(); 21310090Snilay@cs.wisc.edu for (auto it = l.begin(); it != l.end(); ++it) { 21410090Snilay@cs.wisc.edu if (it->contains(pkt->getAddr())) { 21510412Sandreas.hansson@arm.com // generally it is not safe to assume success here as 21610412Sandreas.hansson@arm.com // the port could be blocked 21710412Sandreas.hansson@arm.com bool M5_VAR_USED success = 21810412Sandreas.hansson@arm.com ruby_port->master_ports[i]->sendTimingReq(pkt); 21910412Sandreas.hansson@arm.com assert(success); 22010090Snilay@cs.wisc.edu return true; 22110090Snilay@cs.wisc.edu } 22210090Snilay@cs.wisc.edu } 22310090Snilay@cs.wisc.edu } 22410090Snilay@cs.wisc.edu panic("Should never reach here!\n"); 22510090Snilay@cs.wisc.edu} 22610090Snilay@cs.wisc.edu 22710090Snilay@cs.wisc.edubool 22810090Snilay@cs.wisc.eduRubyPort::MemSlavePort::recvTimingReq(PacketPtr pkt) 22910090Snilay@cs.wisc.edu{ 23010090Snilay@cs.wisc.edu DPRINTF(RubyPort, "Timing request for address %#x on port %d\n", 23110090Snilay@cs.wisc.edu pkt->getAddr(), id); 23210090Snilay@cs.wisc.edu RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 2336882SBrad.Beckmann@amd.com 2349662Sandreas.hansson@arm.com if (pkt->memInhibitAsserted()) 2359662Sandreas.hansson@arm.com panic("RubyPort should never see an inhibited request\n"); 2366882SBrad.Beckmann@amd.com 2376882SBrad.Beckmann@amd.com // Check for pio requests and directly send them to the dedicated 2386882SBrad.Beckmann@amd.com // pio port. 2396882SBrad.Beckmann@amd.com if (!isPhysMemAddress(pkt->getAddr())) { 24010090Snilay@cs.wisc.edu assert(ruby_port->memMasterPort.isConnected()); 24110090Snilay@cs.wisc.edu DPRINTF(RubyPort, "Request address %#x assumed to be a pio address\n", 2426922SBrad.Beckmann@amd.com pkt->getAddr()); 2436882SBrad.Beckmann@amd.com 24410090Snilay@cs.wisc.edu // Save the port in the sender state object to be used later to 24510090Snilay@cs.wisc.edu // route the response 24610090Snilay@cs.wisc.edu pkt->pushSenderState(new SenderState(this)); 24710090Snilay@cs.wisc.edu 2489163Sandreas.hansson@arm.com // send next cycle 24910919Sbrandon.potter@amd.com RubySystem *rs = ruby_port->m_ruby_system; 25010090Snilay@cs.wisc.edu ruby_port->memMasterPort.schedTimingReq(pkt, 25110919Sbrandon.potter@amd.com curTick() + rs->clockPeriod()); 2529163Sandreas.hansson@arm.com return true; 2536882SBrad.Beckmann@amd.com } 2546882SBrad.Beckmann@amd.com 25511025Snilay@cs.wisc.edu assert(getOffset(pkt->getAddr()) + pkt->getSize() <= 2568615Snilay@cs.wisc.edu RubySystem::getBlockSizeBytes()); 2577906SBrad.Beckmann@amd.com 2586882SBrad.Beckmann@amd.com // Submit the ruby request 2598615Snilay@cs.wisc.edu RequestStatus requestStatus = ruby_port->makeRequest(pkt); 2607023SBrad.Beckmann@amd.com 2617550SBrad.Beckmann@amd.com // If the request successfully issued then we should return true. 26210089Sandreas.hansson@arm.com // Otherwise, we need to tell the port to retry at a later point 26310089Sandreas.hansson@arm.com // and return false. 2647550SBrad.Beckmann@amd.com if (requestStatus == RequestStatus_Issued) { 26510657Sandreas.hansson@arm.com // Save the port in the sender state object to be used later to 26610657Sandreas.hansson@arm.com // route the response 26710657Sandreas.hansson@arm.com pkt->pushSenderState(new SenderState(this)); 26810657Sandreas.hansson@arm.com 26910089Sandreas.hansson@arm.com DPRINTF(RubyPort, "Request %s 0x%x issued\n", pkt->cmdString(), 27010089Sandreas.hansson@arm.com pkt->getAddr()); 2716922SBrad.Beckmann@amd.com return true; 2726882SBrad.Beckmann@amd.com } 2737023SBrad.Beckmann@amd.com 2747910SBrad.Beckmann@amd.com 27510090Snilay@cs.wisc.edu DPRINTF(RubyPort, "Request for address %#x did not issued because %s\n", 2767039Snate@binkert.org pkt->getAddr(), RequestStatus_to_string(requestStatus)); 2777039Snate@binkert.org 27811266SBrad.Beckmann@amd.com addToRetryList(); 27911266SBrad.Beckmann@amd.com 2806922SBrad.Beckmann@amd.com return false; 2816882SBrad.Beckmann@amd.com} 2826882SBrad.Beckmann@amd.com 2838436SBrad.Beckmann@amd.comvoid 28411266SBrad.Beckmann@amd.comRubyPort::MemSlavePort::addToRetryList() 28511266SBrad.Beckmann@amd.com{ 28611266SBrad.Beckmann@amd.com RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 28711266SBrad.Beckmann@amd.com 28811266SBrad.Beckmann@amd.com // 28911266SBrad.Beckmann@amd.com // Unless the requestor do not want retries (e.g., the Ruby tester), 29011266SBrad.Beckmann@amd.com // record the stalled M5 port for later retry when the sequencer 29111266SBrad.Beckmann@amd.com // becomes free. 29211266SBrad.Beckmann@amd.com // 29311266SBrad.Beckmann@amd.com if (!no_retry_on_stall && !ruby_port->onRetryList(this)) { 29411266SBrad.Beckmann@amd.com ruby_port->addToRetryList(this); 29511266SBrad.Beckmann@amd.com } 29611266SBrad.Beckmann@amd.com} 29711266SBrad.Beckmann@amd.com 29811266SBrad.Beckmann@amd.comvoid 29910090Snilay@cs.wisc.eduRubyPort::MemSlavePort::recvFunctional(PacketPtr pkt) 3008436SBrad.Beckmann@amd.com{ 30110090Snilay@cs.wisc.edu DPRINTF(RubyPort, "Functional access for address: %#x\n", pkt->getAddr()); 3028436SBrad.Beckmann@amd.com 30310919Sbrandon.potter@amd.com RubyPort *rp M5_VAR_USED = static_cast<RubyPort *>(&owner); 30410919Sbrandon.potter@amd.com RubySystem *rs = rp->m_ruby_system; 30510919Sbrandon.potter@amd.com 3068436SBrad.Beckmann@amd.com // Check for pio requests and directly send them to the dedicated 3078436SBrad.Beckmann@amd.com // pio port. 3088436SBrad.Beckmann@amd.com if (!isPhysMemAddress(pkt->getAddr())) { 30910919Sbrandon.potter@amd.com assert(rp->memMasterPort.isConnected()); 31010090Snilay@cs.wisc.edu DPRINTF(RubyPort, "Pio Request for address: 0x%#x\n", pkt->getAddr()); 31110090Snilay@cs.wisc.edu panic("RubyPort::PioMasterPort::recvFunctional() not implemented!\n"); 3128436SBrad.Beckmann@amd.com } 3138436SBrad.Beckmann@amd.com 3148436SBrad.Beckmann@amd.com assert(pkt->getAddr() + pkt->getSize() <= 31511025Snilay@cs.wisc.edu makeLineAddress(pkt->getAddr()) + RubySystem::getBlockSizeBytes()); 3168436SBrad.Beckmann@amd.com 31710525Snilay@cs.wisc.edu if (access_backing_store) { 3188436SBrad.Beckmann@amd.com // The attached physmem contains the official version of data. 3198436SBrad.Beckmann@amd.com // The following command performs the real functional access. 3208436SBrad.Beckmann@amd.com // This line should be removed once Ruby supplies the official version 3218436SBrad.Beckmann@amd.com // of data. 32210919Sbrandon.potter@amd.com rs->getPhysMem()->functionalAccess(pkt); 32310706Spower.jg@gmail.com } else { 32410706Spower.jg@gmail.com bool accessSucceeded = false; 32510706Spower.jg@gmail.com bool needsResponse = pkt->needsResponse(); 32610706Spower.jg@gmail.com 32710706Spower.jg@gmail.com // Do the functional access on ruby memory 32810706Spower.jg@gmail.com if (pkt->isRead()) { 32910919Sbrandon.potter@amd.com accessSucceeded = rs->functionalRead(pkt); 33010706Spower.jg@gmail.com } else if (pkt->isWrite()) { 33110919Sbrandon.potter@amd.com accessSucceeded = rs->functionalWrite(pkt); 33210706Spower.jg@gmail.com } else { 33310706Spower.jg@gmail.com panic("Unsupported functional command %s\n", pkt->cmdString()); 33410706Spower.jg@gmail.com } 33510706Spower.jg@gmail.com 33610706Spower.jg@gmail.com // Unless the requester explicitly said otherwise, generate an error if 33710706Spower.jg@gmail.com // the functional request failed 33810706Spower.jg@gmail.com if (!accessSucceeded && !pkt->suppressFuncError()) { 33910706Spower.jg@gmail.com fatal("Ruby functional %s failed for address %#x\n", 34010706Spower.jg@gmail.com pkt->isWrite() ? "write" : "read", pkt->getAddr()); 34110706Spower.jg@gmail.com } 34210706Spower.jg@gmail.com 34310706Spower.jg@gmail.com // turn packet around to go back to requester if response expected 34410706Spower.jg@gmail.com if (needsResponse) { 34510706Spower.jg@gmail.com pkt->setFunctionalResponseStatus(accessSucceeded); 34610706Spower.jg@gmail.com } 34710706Spower.jg@gmail.com 34810706Spower.jg@gmail.com DPRINTF(RubyPort, "Functional access %s!\n", 34910706Spower.jg@gmail.com accessSucceeded ? "successful":"failed"); 3508436SBrad.Beckmann@amd.com } 3518436SBrad.Beckmann@amd.com} 3528436SBrad.Beckmann@amd.com 3536882SBrad.Beckmann@amd.comvoid 3546922SBrad.Beckmann@amd.comRubyPort::ruby_hit_callback(PacketPtr pkt) 3556882SBrad.Beckmann@amd.com{ 35610089Sandreas.hansson@arm.com DPRINTF(RubyPort, "Hit callback for %s 0x%x\n", pkt->cmdString(), 35710089Sandreas.hansson@arm.com pkt->getAddr()); 3587039Snate@binkert.org 35910089Sandreas.hansson@arm.com // The packet was destined for memory and has not yet been turned 36010089Sandreas.hansson@arm.com // into a response 36110089Sandreas.hansson@arm.com assert(system->isMemAddr(pkt->getAddr())); 36210089Sandreas.hansson@arm.com assert(pkt->isRequest()); 3636882SBrad.Beckmann@amd.com 36410657Sandreas.hansson@arm.com // First we must retrieve the request port from the sender State 36510657Sandreas.hansson@arm.com RubyPort::SenderState *senderState = 36610657Sandreas.hansson@arm.com safe_cast<RubyPort::SenderState *>(pkt->popSenderState()); 36710657Sandreas.hansson@arm.com MemSlavePort *port = senderState->port; 36810657Sandreas.hansson@arm.com assert(port != NULL); 36910657Sandreas.hansson@arm.com delete senderState; 37010089Sandreas.hansson@arm.com 37110657Sandreas.hansson@arm.com port->hitCallback(pkt); 3727910SBrad.Beckmann@amd.com 37311266SBrad.Beckmann@amd.com trySendRetries(); 37411266SBrad.Beckmann@amd.com} 37511266SBrad.Beckmann@amd.com 37611266SBrad.Beckmann@amd.comvoid 37711266SBrad.Beckmann@amd.comRubyPort::trySendRetries() 37811266SBrad.Beckmann@amd.com{ 3797910SBrad.Beckmann@amd.com // 38010090Snilay@cs.wisc.edu // If we had to stall the MemSlavePorts, wake them up because the sequencer 3817910SBrad.Beckmann@amd.com // likely has free resources now. 3827910SBrad.Beckmann@amd.com // 38310089Sandreas.hansson@arm.com if (!retryList.empty()) { 38411266SBrad.Beckmann@amd.com // Record the current list of ports to retry on a temporary list 38511266SBrad.Beckmann@amd.com // before calling sendRetryReq on those ports. sendRetryReq will cause 38611266SBrad.Beckmann@amd.com // an immediate retry, which may result in the ports being put back on 38711266SBrad.Beckmann@amd.com // the list. Therefore we want to clear the retryList before calling 38811266SBrad.Beckmann@amd.com // sendRetryReq. 38910090Snilay@cs.wisc.edu std::vector<MemSlavePort *> curRetryList(retryList); 3908162SBrad.Beckmann@amd.com 3918162SBrad.Beckmann@amd.com retryList.clear(); 39210089Sandreas.hansson@arm.com 39310089Sandreas.hansson@arm.com for (auto i = curRetryList.begin(); i != curRetryList.end(); ++i) { 3948162SBrad.Beckmann@amd.com DPRINTF(RubyPort, 39511266SBrad.Beckmann@amd.com "Sequencer may now be free. SendRetry to port %s\n", 3967910SBrad.Beckmann@amd.com (*i)->name()); 39710713Sandreas.hansson@arm.com (*i)->sendRetryReq(); 3987910SBrad.Beckmann@amd.com } 3997910SBrad.Beckmann@amd.com } 4008688Snilay@cs.wisc.edu} 4018688Snilay@cs.wisc.edu 4028688Snilay@cs.wisc.eduvoid 4038688Snilay@cs.wisc.eduRubyPort::testDrainComplete() 4048688Snilay@cs.wisc.edu{ 4058688Snilay@cs.wisc.edu //If we weren't able to drain before, we might be able to now. 40610913Sandreas.sandberg@arm.com if (drainState() == DrainState::Draining) { 4079245Shestness@cs.wisc.edu unsigned int drainCount = outstandingCount(); 4089152Satgutier@umich.edu DPRINTF(Drain, "Drain count: %u\n", drainCount); 4098688Snilay@cs.wisc.edu if (drainCount == 0) { 4109342SAndreas.Sandberg@arm.com DPRINTF(Drain, "RubyPort done draining, signaling drain done\n"); 41110913Sandreas.sandberg@arm.com signalDrainDone(); 4128688Snilay@cs.wisc.edu } 4138688Snilay@cs.wisc.edu } 4148688Snilay@cs.wisc.edu} 4158688Snilay@cs.wisc.edu 41610913Sandreas.sandberg@arm.comDrainState 41710913Sandreas.sandberg@arm.comRubyPort::drain() 4188688Snilay@cs.wisc.edu{ 4198688Snilay@cs.wisc.edu if (isDeadlockEventScheduled()) { 4208688Snilay@cs.wisc.edu descheduleDeadlockEvent(); 4218688Snilay@cs.wisc.edu } 4228688Snilay@cs.wisc.edu 4239245Shestness@cs.wisc.edu // 4249245Shestness@cs.wisc.edu // If the RubyPort is not empty, then it needs to clear all outstanding 42510913Sandreas.sandberg@arm.com // requests before it should call signalDrainDone() 4269245Shestness@cs.wisc.edu // 4279245Shestness@cs.wisc.edu DPRINTF(Config, "outstanding count %d\n", outstandingCount()); 42810913Sandreas.sandberg@arm.com if (outstandingCount() > 0) { 4299152Satgutier@umich.edu DPRINTF(Drain, "RubyPort not drained\n"); 43010913Sandreas.sandberg@arm.com return DrainState::Draining; 43110913Sandreas.sandberg@arm.com } else { 43210913Sandreas.sandberg@arm.com return DrainState::Drained; 4338688Snilay@cs.wisc.edu } 4346882SBrad.Beckmann@amd.com} 4356882SBrad.Beckmann@amd.com 4366882SBrad.Beckmann@amd.comvoid 43710090Snilay@cs.wisc.eduRubyPort::MemSlavePort::hitCallback(PacketPtr pkt) 4386882SBrad.Beckmann@amd.com{ 4396882SBrad.Beckmann@amd.com bool needsResponse = pkt->needsResponse(); 4406882SBrad.Beckmann@amd.com 44110917Sbrandon.potter@amd.com // Unless specified at configuraiton, all responses except failed SC 4428184Ssomayeh@cs.wisc.edu // and Flush operations access M5 physical memory. 44310525Snilay@cs.wisc.edu bool accessPhysMem = access_backing_store; 4447550SBrad.Beckmann@amd.com 4457550SBrad.Beckmann@amd.com if (pkt->isLLSC()) { 4467550SBrad.Beckmann@amd.com if (pkt->isWrite()) { 4477550SBrad.Beckmann@amd.com if (pkt->req->getExtraData() != 0) { 4487550SBrad.Beckmann@amd.com // 4497550SBrad.Beckmann@amd.com // Successful SC packets convert to normal writes 4507550SBrad.Beckmann@amd.com // 4517550SBrad.Beckmann@amd.com pkt->convertScToWrite(); 4527550SBrad.Beckmann@amd.com } else { 4537550SBrad.Beckmann@amd.com // 4547550SBrad.Beckmann@amd.com // Failed SC packets don't access physical memory and thus 4557550SBrad.Beckmann@amd.com // the RubyPort itself must convert it to a response. 4567550SBrad.Beckmann@amd.com // 4577550SBrad.Beckmann@amd.com accessPhysMem = false; 4587550SBrad.Beckmann@amd.com } 4597550SBrad.Beckmann@amd.com } else { 4607550SBrad.Beckmann@amd.com // 4617550SBrad.Beckmann@amd.com // All LL packets convert to normal loads so that M5 PhysMem does 4627550SBrad.Beckmann@amd.com // not lock the blocks. 4637550SBrad.Beckmann@amd.com // 4647550SBrad.Beckmann@amd.com pkt->convertLlToRead(); 4657550SBrad.Beckmann@amd.com } 4667550SBrad.Beckmann@amd.com } 4678184Ssomayeh@cs.wisc.edu 4688184Ssomayeh@cs.wisc.edu // Flush requests don't access physical memory 4698184Ssomayeh@cs.wisc.edu if (pkt->isFlush()) { 4708184Ssomayeh@cs.wisc.edu accessPhysMem = false; 4718184Ssomayeh@cs.wisc.edu } 4728184Ssomayeh@cs.wisc.edu 4738161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse); 4746882SBrad.Beckmann@amd.com 47510919Sbrandon.potter@amd.com RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 47610919Sbrandon.potter@amd.com RubySystem *rs = ruby_port->m_ruby_system; 4777550SBrad.Beckmann@amd.com if (accessPhysMem) { 47810919Sbrandon.potter@amd.com rs->getPhysMem()->access(pkt); 4798184Ssomayeh@cs.wisc.edu } else if (needsResponse) { 4807915SBrad.Beckmann@amd.com pkt->makeResponse(); 4817550SBrad.Beckmann@amd.com } 4826882SBrad.Beckmann@amd.com 4836882SBrad.Beckmann@amd.com // turn packet around to go back to requester if response expected 4846882SBrad.Beckmann@amd.com if (needsResponse) { 4858161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Sending packet back over port\n"); 48610961Sdavid.hashe@amd.com // Send a response in the same cycle. There is no need to delay the 48710961Sdavid.hashe@amd.com // response because the response latency is already incurred in the 48810961Sdavid.hashe@amd.com // Ruby protocol. 48910961Sdavid.hashe@amd.com schedTimingResp(pkt, curTick()); 4906882SBrad.Beckmann@amd.com } else { 4916882SBrad.Beckmann@amd.com delete pkt; 4926882SBrad.Beckmann@amd.com } 49310525Snilay@cs.wisc.edu 4948161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Hit callback done!\n"); 4956882SBrad.Beckmann@amd.com} 4966882SBrad.Beckmann@amd.com 4978922Swilliam.wang@arm.comAddrRangeList 49810090Snilay@cs.wisc.eduRubyPort::PioSlavePort::getAddrRanges() const 4998922Swilliam.wang@arm.com{ 5008922Swilliam.wang@arm.com // at the moment the assumption is that the master does not care 5018922Swilliam.wang@arm.com AddrRangeList ranges; 50210090Snilay@cs.wisc.edu RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 50310090Snilay@cs.wisc.edu 50410090Snilay@cs.wisc.edu for (size_t i = 0; i < ruby_port->master_ports.size(); ++i) { 50510090Snilay@cs.wisc.edu ranges.splice(ranges.begin(), 50610090Snilay@cs.wisc.edu ruby_port->master_ports[i]->getAddrRanges()); 50710090Snilay@cs.wisc.edu } 50810481Sandreas.hansson@arm.com for (const auto M5_VAR_USED &r : ranges) 50910481Sandreas.hansson@arm.com DPRINTF(RubyPort, "%s\n", r.to_string()); 5108922Swilliam.wang@arm.com return ranges; 5118922Swilliam.wang@arm.com} 5128922Swilliam.wang@arm.com 5136882SBrad.Beckmann@amd.combool 51410090Snilay@cs.wisc.eduRubyPort::MemSlavePort::isPhysMemAddress(Addr addr) const 5156882SBrad.Beckmann@amd.com{ 51610090Snilay@cs.wisc.edu RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 5178931Sandreas.hansson@arm.com return ruby_port->system->isMemAddr(addr); 5186882SBrad.Beckmann@amd.com} 5197909Shestness@cs.utexas.edu 5208717Snilay@cs.wisc.eduvoid 52111025Snilay@cs.wisc.eduRubyPort::ruby_eviction_callback(Addr address) 5228717Snilay@cs.wisc.edu{ 5238717Snilay@cs.wisc.edu DPRINTF(RubyPort, "Sending invalidations.\n"); 52411143Sjthestness@gmail.com // Allocate the invalidate request and packet on the stack, as it is 52511143Sjthestness@gmail.com // assumed they will not be modified or deleted by receivers. 5269633Sjthestness@gmail.com // TODO: should this really be using funcMasterId? 52711143Sjthestness@gmail.com Request request(address, RubySystem::getBlockSizeBytes(), 0, 52811143Sjthestness@gmail.com Request::funcMasterId); 5299633Sjthestness@gmail.com // Use a single packet to signal all snooping ports of the invalidation. 5309633Sjthestness@gmail.com // This assumes that snooping ports do NOT modify the packet/request 53111143Sjthestness@gmail.com Packet pkt(&request, MemCmd::InvalidateReq); 5328922Swilliam.wang@arm.com for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) { 5339088Sandreas.hansson@arm.com // check if the connected master port is snooping 5349088Sandreas.hansson@arm.com if ((*p)->isSnooping()) { 5358948Sandreas.hansson@arm.com // send as a snoop request 5369633Sjthestness@gmail.com (*p)->sendTimingSnoopReq(&pkt); 5378922Swilliam.wang@arm.com } 5388717Snilay@cs.wisc.edu } 5398717Snilay@cs.wisc.edu} 54010090Snilay@cs.wisc.edu 54110090Snilay@cs.wisc.eduvoid 54210090Snilay@cs.wisc.eduRubyPort::PioMasterPort::recvRangeChange() 54310090Snilay@cs.wisc.edu{ 54410090Snilay@cs.wisc.edu RubyPort &r = static_cast<RubyPort &>(owner); 54510090Snilay@cs.wisc.edu r.gotAddrRanges--; 54610117Snilay@cs.wisc.edu if (r.gotAddrRanges == 0 && FullSystem) { 54710090Snilay@cs.wisc.edu r.pioSlavePort.sendRangeChange(); 54810090Snilay@cs.wisc.edu } 54910090Snilay@cs.wisc.edu} 550