RubyPort.cc revision 11266
1/* 2 * Copyright (c) 2012-2013 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2009-2013 Advanced Micro Devices, Inc. 15 * Copyright (c) 2011 Mark D. Hill and David A. Wood 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 */ 41 42#include "cpu/testers/rubytest/RubyTester.hh" 43#include "debug/Config.hh" 44#include "debug/Drain.hh" 45#include "debug/Ruby.hh" 46#include "mem/protocol/AccessPermission.hh" 47#include "mem/ruby/slicc_interface/AbstractController.hh" 48#include "mem/ruby/system/RubyPort.hh" 49#include "mem/simple_mem.hh" 50#include "sim/full_system.hh" 51#include "sim/system.hh" 52 53RubyPort::RubyPort(const Params *p) 54 : MemObject(p), m_ruby_system(p->ruby_system), m_version(p->version), 55 m_controller(NULL), m_mandatory_q_ptr(NULL), 56 m_usingRubyTester(p->using_ruby_tester), system(p->system), 57 pioMasterPort(csprintf("%s.pio-master-port", name()), this), 58 pioSlavePort(csprintf("%s.pio-slave-port", name()), this), 59 memMasterPort(csprintf("%s.mem-master-port", name()), this), 60 memSlavePort(csprintf("%s-mem-slave-port", name()), this, 61 p->ruby_system->getAccessBackingStore(), -1, 62 p->no_retry_on_stall), 63 gotAddrRanges(p->port_master_connection_count) 64{ 65 assert(m_version != -1); 66 67 // create the slave ports based on the number of connected ports 68 for (size_t i = 0; i < p->port_slave_connection_count; ++i) { 69 slave_ports.push_back(new MemSlavePort(csprintf("%s.slave%d", name(), 70 i), this, p->ruby_system->getAccessBackingStore(), 71 i, p->no_retry_on_stall)); 72 } 73 74 // create the master ports based on the number of connected ports 75 for (size_t i = 0; i < p->port_master_connection_count; ++i) { 76 master_ports.push_back(new PioMasterPort(csprintf("%s.master%d", 77 name(), i), this)); 78 } 79} 80 81void 82RubyPort::init() 83{ 84 assert(m_controller != NULL); 85 m_mandatory_q_ptr = m_controller->getMandatoryQueue(); 86} 87 88BaseMasterPort & 89RubyPort::getMasterPort(const std::string &if_name, PortID idx) 90{ 91 if (if_name == "mem_master_port") { 92 return memMasterPort; 93 } 94 95 if (if_name == "pio_master_port") { 96 return pioMasterPort; 97 } 98 99 // used by the x86 CPUs to connect the interrupt PIO and interrupt slave 100 // port 101 if (if_name != "master") { 102 // pass it along to our super class 103 return MemObject::getMasterPort(if_name, idx); 104 } else { 105 if (idx >= static_cast<PortID>(master_ports.size())) { 106 panic("RubyPort::getMasterPort: unknown index %d\n", idx); 107 } 108 109 return *master_ports[idx]; 110 } 111} 112 113BaseSlavePort & 114RubyPort::getSlavePort(const std::string &if_name, PortID idx) 115{ 116 if (if_name == "mem_slave_port") { 117 return memSlavePort; 118 } 119 120 if (if_name == "pio_slave_port") 121 return pioSlavePort; 122 123 // used by the CPUs to connect the caches to the interconnect, and 124 // for the x86 case also the interrupt master 125 if (if_name != "slave") { 126 // pass it along to our super class 127 return MemObject::getSlavePort(if_name, idx); 128 } else { 129 if (idx >= static_cast<PortID>(slave_ports.size())) { 130 panic("RubyPort::getSlavePort: unknown index %d\n", idx); 131 } 132 133 return *slave_ports[idx]; 134 } 135} 136 137RubyPort::PioMasterPort::PioMasterPort(const std::string &_name, 138 RubyPort *_port) 139 : QueuedMasterPort(_name, _port, reqQueue, snoopRespQueue), 140 reqQueue(*_port, *this), snoopRespQueue(*_port, *this) 141{ 142 DPRINTF(RubyPort, "Created master pioport on sequencer %s\n", _name); 143} 144 145RubyPort::PioSlavePort::PioSlavePort(const std::string &_name, 146 RubyPort *_port) 147 : QueuedSlavePort(_name, _port, queue), queue(*_port, *this) 148{ 149 DPRINTF(RubyPort, "Created slave pioport on sequencer %s\n", _name); 150} 151 152RubyPort::MemMasterPort::MemMasterPort(const std::string &_name, 153 RubyPort *_port) 154 : QueuedMasterPort(_name, _port, reqQueue, snoopRespQueue), 155 reqQueue(*_port, *this), snoopRespQueue(*_port, *this) 156{ 157 DPRINTF(RubyPort, "Created master memport on ruby sequencer %s\n", _name); 158} 159 160RubyPort::MemSlavePort::MemSlavePort(const std::string &_name, RubyPort *_port, 161 bool _access_backing_store, PortID id, 162 bool _no_retry_on_stall) 163 : QueuedSlavePort(_name, _port, queue, id), queue(*_port, *this), 164 access_backing_store(_access_backing_store), 165 no_retry_on_stall(_no_retry_on_stall) 166{ 167 DPRINTF(RubyPort, "Created slave memport on ruby sequencer %s\n", _name); 168} 169 170bool 171RubyPort::PioMasterPort::recvTimingResp(PacketPtr pkt) 172{ 173 RubyPort *rp = static_cast<RubyPort *>(&owner); 174 DPRINTF(RubyPort, "Response for address: 0x%#x\n", pkt->getAddr()); 175 176 // send next cycle 177 rp->pioSlavePort.schedTimingResp( 178 pkt, curTick() + rp->m_ruby_system->clockPeriod()); 179 return true; 180} 181 182bool RubyPort::MemMasterPort::recvTimingResp(PacketPtr pkt) 183{ 184 // got a response from a device 185 assert(pkt->isResponse()); 186 187 // First we must retrieve the request port from the sender State 188 RubyPort::SenderState *senderState = 189 safe_cast<RubyPort::SenderState *>(pkt->popSenderState()); 190 MemSlavePort *port = senderState->port; 191 assert(port != NULL); 192 delete senderState; 193 194 // In FS mode, ruby memory will receive pio responses from devices 195 // and it must forward these responses back to the particular CPU. 196 DPRINTF(RubyPort, "Pio response for address %#x, going to %s\n", 197 pkt->getAddr(), port->name()); 198 199 // attempt to send the response in the next cycle 200 RubyPort *rp = static_cast<RubyPort *>(&owner); 201 port->schedTimingResp(pkt, curTick() + rp->m_ruby_system->clockPeriod()); 202 203 return true; 204} 205 206bool 207RubyPort::PioSlavePort::recvTimingReq(PacketPtr pkt) 208{ 209 RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 210 211 for (size_t i = 0; i < ruby_port->master_ports.size(); ++i) { 212 AddrRangeList l = ruby_port->master_ports[i]->getAddrRanges(); 213 for (auto it = l.begin(); it != l.end(); ++it) { 214 if (it->contains(pkt->getAddr())) { 215 // generally it is not safe to assume success here as 216 // the port could be blocked 217 bool M5_VAR_USED success = 218 ruby_port->master_ports[i]->sendTimingReq(pkt); 219 assert(success); 220 return true; 221 } 222 } 223 } 224 panic("Should never reach here!\n"); 225} 226 227bool 228RubyPort::MemSlavePort::recvTimingReq(PacketPtr pkt) 229{ 230 DPRINTF(RubyPort, "Timing request for address %#x on port %d\n", 231 pkt->getAddr(), id); 232 RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 233 234 if (pkt->memInhibitAsserted()) 235 panic("RubyPort should never see an inhibited request\n"); 236 237 // Check for pio requests and directly send them to the dedicated 238 // pio port. 239 if (!isPhysMemAddress(pkt->getAddr())) { 240 assert(ruby_port->memMasterPort.isConnected()); 241 DPRINTF(RubyPort, "Request address %#x assumed to be a pio address\n", 242 pkt->getAddr()); 243 244 // Save the port in the sender state object to be used later to 245 // route the response 246 pkt->pushSenderState(new SenderState(this)); 247 248 // send next cycle 249 RubySystem *rs = ruby_port->m_ruby_system; 250 ruby_port->memMasterPort.schedTimingReq(pkt, 251 curTick() + rs->clockPeriod()); 252 return true; 253 } 254 255 assert(getOffset(pkt->getAddr()) + pkt->getSize() <= 256 RubySystem::getBlockSizeBytes()); 257 258 // Submit the ruby request 259 RequestStatus requestStatus = ruby_port->makeRequest(pkt); 260 261 // If the request successfully issued then we should return true. 262 // Otherwise, we need to tell the port to retry at a later point 263 // and return false. 264 if (requestStatus == RequestStatus_Issued) { 265 // Save the port in the sender state object to be used later to 266 // route the response 267 pkt->pushSenderState(new SenderState(this)); 268 269 DPRINTF(RubyPort, "Request %s 0x%x issued\n", pkt->cmdString(), 270 pkt->getAddr()); 271 return true; 272 } 273 274 275 DPRINTF(RubyPort, "Request for address %#x did not issued because %s\n", 276 pkt->getAddr(), RequestStatus_to_string(requestStatus)); 277 278 addToRetryList(); 279 280 return false; 281} 282 283void 284RubyPort::MemSlavePort::addToRetryList() 285{ 286 RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 287 288 // 289 // Unless the requestor do not want retries (e.g., the Ruby tester), 290 // record the stalled M5 port for later retry when the sequencer 291 // becomes free. 292 // 293 if (!no_retry_on_stall && !ruby_port->onRetryList(this)) { 294 ruby_port->addToRetryList(this); 295 } 296} 297 298void 299RubyPort::MemSlavePort::recvFunctional(PacketPtr pkt) 300{ 301 DPRINTF(RubyPort, "Functional access for address: %#x\n", pkt->getAddr()); 302 303 RubyPort *rp M5_VAR_USED = static_cast<RubyPort *>(&owner); 304 RubySystem *rs = rp->m_ruby_system; 305 306 // Check for pio requests and directly send them to the dedicated 307 // pio port. 308 if (!isPhysMemAddress(pkt->getAddr())) { 309 assert(rp->memMasterPort.isConnected()); 310 DPRINTF(RubyPort, "Pio Request for address: 0x%#x\n", pkt->getAddr()); 311 panic("RubyPort::PioMasterPort::recvFunctional() not implemented!\n"); 312 } 313 314 assert(pkt->getAddr() + pkt->getSize() <= 315 makeLineAddress(pkt->getAddr()) + RubySystem::getBlockSizeBytes()); 316 317 if (access_backing_store) { 318 // The attached physmem contains the official version of data. 319 // The following command performs the real functional access. 320 // This line should be removed once Ruby supplies the official version 321 // of data. 322 rs->getPhysMem()->functionalAccess(pkt); 323 } else { 324 bool accessSucceeded = false; 325 bool needsResponse = pkt->needsResponse(); 326 327 // Do the functional access on ruby memory 328 if (pkt->isRead()) { 329 accessSucceeded = rs->functionalRead(pkt); 330 } else if (pkt->isWrite()) { 331 accessSucceeded = rs->functionalWrite(pkt); 332 } else { 333 panic("Unsupported functional command %s\n", pkt->cmdString()); 334 } 335 336 // Unless the requester explicitly said otherwise, generate an error if 337 // the functional request failed 338 if (!accessSucceeded && !pkt->suppressFuncError()) { 339 fatal("Ruby functional %s failed for address %#x\n", 340 pkt->isWrite() ? "write" : "read", pkt->getAddr()); 341 } 342 343 // turn packet around to go back to requester if response expected 344 if (needsResponse) { 345 pkt->setFunctionalResponseStatus(accessSucceeded); 346 } 347 348 DPRINTF(RubyPort, "Functional access %s!\n", 349 accessSucceeded ? "successful":"failed"); 350 } 351} 352 353void 354RubyPort::ruby_hit_callback(PacketPtr pkt) 355{ 356 DPRINTF(RubyPort, "Hit callback for %s 0x%x\n", pkt->cmdString(), 357 pkt->getAddr()); 358 359 // The packet was destined for memory and has not yet been turned 360 // into a response 361 assert(system->isMemAddr(pkt->getAddr())); 362 assert(pkt->isRequest()); 363 364 // First we must retrieve the request port from the sender State 365 RubyPort::SenderState *senderState = 366 safe_cast<RubyPort::SenderState *>(pkt->popSenderState()); 367 MemSlavePort *port = senderState->port; 368 assert(port != NULL); 369 delete senderState; 370 371 port->hitCallback(pkt); 372 373 trySendRetries(); 374} 375 376void 377RubyPort::trySendRetries() 378{ 379 // 380 // If we had to stall the MemSlavePorts, wake them up because the sequencer 381 // likely has free resources now. 382 // 383 if (!retryList.empty()) { 384 // Record the current list of ports to retry on a temporary list 385 // before calling sendRetryReq on those ports. sendRetryReq will cause 386 // an immediate retry, which may result in the ports being put back on 387 // the list. Therefore we want to clear the retryList before calling 388 // sendRetryReq. 389 std::vector<MemSlavePort *> curRetryList(retryList); 390 391 retryList.clear(); 392 393 for (auto i = curRetryList.begin(); i != curRetryList.end(); ++i) { 394 DPRINTF(RubyPort, 395 "Sequencer may now be free. SendRetry to port %s\n", 396 (*i)->name()); 397 (*i)->sendRetryReq(); 398 } 399 } 400} 401 402void 403RubyPort::testDrainComplete() 404{ 405 //If we weren't able to drain before, we might be able to now. 406 if (drainState() == DrainState::Draining) { 407 unsigned int drainCount = outstandingCount(); 408 DPRINTF(Drain, "Drain count: %u\n", drainCount); 409 if (drainCount == 0) { 410 DPRINTF(Drain, "RubyPort done draining, signaling drain done\n"); 411 signalDrainDone(); 412 } 413 } 414} 415 416DrainState 417RubyPort::drain() 418{ 419 if (isDeadlockEventScheduled()) { 420 descheduleDeadlockEvent(); 421 } 422 423 // 424 // If the RubyPort is not empty, then it needs to clear all outstanding 425 // requests before it should call signalDrainDone() 426 // 427 DPRINTF(Config, "outstanding count %d\n", outstandingCount()); 428 if (outstandingCount() > 0) { 429 DPRINTF(Drain, "RubyPort not drained\n"); 430 return DrainState::Draining; 431 } else { 432 return DrainState::Drained; 433 } 434} 435 436void 437RubyPort::MemSlavePort::hitCallback(PacketPtr pkt) 438{ 439 bool needsResponse = pkt->needsResponse(); 440 441 // Unless specified at configuraiton, all responses except failed SC 442 // and Flush operations access M5 physical memory. 443 bool accessPhysMem = access_backing_store; 444 445 if (pkt->isLLSC()) { 446 if (pkt->isWrite()) { 447 if (pkt->req->getExtraData() != 0) { 448 // 449 // Successful SC packets convert to normal writes 450 // 451 pkt->convertScToWrite(); 452 } else { 453 // 454 // Failed SC packets don't access physical memory and thus 455 // the RubyPort itself must convert it to a response. 456 // 457 accessPhysMem = false; 458 } 459 } else { 460 // 461 // All LL packets convert to normal loads so that M5 PhysMem does 462 // not lock the blocks. 463 // 464 pkt->convertLlToRead(); 465 } 466 } 467 468 // Flush requests don't access physical memory 469 if (pkt->isFlush()) { 470 accessPhysMem = false; 471 } 472 473 DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse); 474 475 RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 476 RubySystem *rs = ruby_port->m_ruby_system; 477 if (accessPhysMem) { 478 rs->getPhysMem()->access(pkt); 479 } else if (needsResponse) { 480 pkt->makeResponse(); 481 } 482 483 // turn packet around to go back to requester if response expected 484 if (needsResponse) { 485 DPRINTF(RubyPort, "Sending packet back over port\n"); 486 // Send a response in the same cycle. There is no need to delay the 487 // response because the response latency is already incurred in the 488 // Ruby protocol. 489 schedTimingResp(pkt, curTick()); 490 } else { 491 delete pkt; 492 } 493 494 DPRINTF(RubyPort, "Hit callback done!\n"); 495} 496 497AddrRangeList 498RubyPort::PioSlavePort::getAddrRanges() const 499{ 500 // at the moment the assumption is that the master does not care 501 AddrRangeList ranges; 502 RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 503 504 for (size_t i = 0; i < ruby_port->master_ports.size(); ++i) { 505 ranges.splice(ranges.begin(), 506 ruby_port->master_ports[i]->getAddrRanges()); 507 } 508 for (const auto M5_VAR_USED &r : ranges) 509 DPRINTF(RubyPort, "%s\n", r.to_string()); 510 return ranges; 511} 512 513bool 514RubyPort::MemSlavePort::isPhysMemAddress(Addr addr) const 515{ 516 RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 517 return ruby_port->system->isMemAddr(addr); 518} 519 520void 521RubyPort::ruby_eviction_callback(Addr address) 522{ 523 DPRINTF(RubyPort, "Sending invalidations.\n"); 524 // Allocate the invalidate request and packet on the stack, as it is 525 // assumed they will not be modified or deleted by receivers. 526 // TODO: should this really be using funcMasterId? 527 Request request(address, RubySystem::getBlockSizeBytes(), 0, 528 Request::funcMasterId); 529 // Use a single packet to signal all snooping ports of the invalidation. 530 // This assumes that snooping ports do NOT modify the packet/request 531 Packet pkt(&request, MemCmd::InvalidateReq); 532 for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) { 533 // check if the connected master port is snooping 534 if ((*p)->isSnooping()) { 535 // send as a snoop request 536 (*p)->sendTimingSnoopReq(&pkt); 537 } 538 } 539} 540 541void 542RubyPort::PioMasterPort::recvRangeChange() 543{ 544 RubyPort &r = static_cast<RubyPort &>(owner); 545 r.gotAddrRanges--; 546 if (r.gotAddrRanges == 0 && FullSystem) { 547 r.pioSlavePort.sendRangeChange(); 548 } 549} 550