dram_ctrl.cc revision 12706
19243SN/A/* 212706Swendy.elsasser@arm.com * Copyright (c) 2010-2018 ARM Limited 39243SN/A * All rights reserved 49243SN/A * 59243SN/A * The license below extends only to copyright in the software and shall 69243SN/A * not be construed as granting a license to any other intellectual 79243SN/A * property including but not limited to intellectual property relating 89243SN/A * to a hardware implementation of the functionality of the software 99243SN/A * licensed hereunder. You may use the software subject to the license 109243SN/A * terms below provided that you ensure that this notice is replicated 119243SN/A * unmodified and in its entirety in all distributions of the software, 129243SN/A * modified or unmodified, in source code or in binary form. 139243SN/A * 149831SN/A * Copyright (c) 2013 Amin Farmahini-Farahani 159831SN/A * All rights reserved. 169831SN/A * 179243SN/A * Redistribution and use in source and binary forms, with or without 189243SN/A * modification, are permitted provided that the following conditions are 199243SN/A * met: redistributions of source code must retain the above copyright 209243SN/A * notice, this list of conditions and the following disclaimer; 219243SN/A * redistributions in binary form must reproduce the above copyright 229243SN/A * notice, this list of conditions and the following disclaimer in the 239243SN/A * documentation and/or other materials provided with the distribution; 249243SN/A * neither the name of the copyright holders nor the names of its 259243SN/A * contributors may be used to endorse or promote products derived from 269243SN/A * this software without specific prior written permission. 279243SN/A * 289243SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 299243SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 309243SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 319243SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 329243SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 339243SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 349243SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 359243SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 369243SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379243SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389243SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 399243SN/A * 409243SN/A * Authors: Andreas Hansson 419243SN/A * Ani Udipi 429967SN/A * Neha Agarwal 4310618SOmar.Naji@arm.com * Omar Naji 4411678Swendy.elsasser@arm.com * Wendy Elsasser 4512266Sradhika.jagtap@arm.com * Radhika Jagtap 469243SN/A */ 479243SN/A 4811793Sbrandon.potter@amd.com#include "mem/dram_ctrl.hh" 4911793Sbrandon.potter@amd.com 5010146Sandreas.hansson@arm.com#include "base/bitfield.hh" 519356SN/A#include "base/trace.hh" 5210146Sandreas.hansson@arm.com#include "debug/DRAM.hh" 5310247Sandreas.hansson@arm.com#include "debug/DRAMPower.hh" 5410208Sandreas.hansson@arm.com#include "debug/DRAMState.hh" 559352SN/A#include "debug/Drain.hh" 569814SN/A#include "sim/system.hh" 579243SN/A 589243SN/Ausing namespace std; 5910432SOmar.Naji@arm.comusing namespace Data; 609243SN/A 6110146Sandreas.hansson@arm.comDRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) : 629243SN/A AbstractMemory(p), 6310619Sandreas.hansson@arm.com port(name() + ".port", *this), isTimingMode(false), 649243SN/A retryRdReq(false), retryWrReq(false), 6510211Sandreas.hansson@arm.com busState(READ), 6611678Swendy.elsasser@arm.com busStateNext(READ), 6712084Sspwilson2@wisc.edu nextReqEvent([this]{ processNextReqEvent(); }, name()), 6812084Sspwilson2@wisc.edu respondEvent([this]{ processRespondEvent(); }, name()), 6910489SOmar.Naji@arm.com deviceSize(p->device_size), 709831SN/A deviceBusWidth(p->device_bus_width), burstLength(p->burst_length), 719831SN/A deviceRowBufferSize(p->device_rowbuffer_size), 729831SN/A devicesPerRank(p->devices_per_rank), 739831SN/A burstSize((devicesPerRank * burstLength * deviceBusWidth) / 8), 749831SN/A rowBufferSize(devicesPerRank * deviceRowBufferSize), 7510140SN/A columnsPerRowBuffer(rowBufferSize / burstSize), 7610646Sandreas.hansson@arm.com columnsPerStripe(range.interleaved() ? range.granularity() / burstSize : 1), 779243SN/A ranksPerChannel(p->ranks_per_channel), 7810394Swendy.elsasser@arm.com bankGroupsPerRank(p->bank_groups_per_rank), 7910394Swendy.elsasser@arm.com bankGroupArch(p->bank_groups_per_rank > 0), 809566SN/A banksPerRank(p->banks_per_rank), channels(p->channels), rowsPerBank(0), 819243SN/A readBufferSize(p->read_buffer_size), 829243SN/A writeBufferSize(p->write_buffer_size), 8310140SN/A writeHighThreshold(writeBufferSize * p->write_high_thresh_perc / 100.0), 8410140SN/A writeLowThreshold(writeBufferSize * p->write_low_thresh_perc / 100.0), 8510147Sandreas.hansson@arm.com minWritesPerSwitch(p->min_writes_per_switch), 8610147Sandreas.hansson@arm.com writesThisTime(0), readsThisTime(0), 8712706Swendy.elsasser@arm.com tCK(p->tCK), tRTW(p->tRTW), tCS(p->tCS), tBURST(p->tBURST), 8812706Swendy.elsasser@arm.com tCCD_L_WR(p->tCCD_L_WR), 8910394Swendy.elsasser@arm.com tCCD_L(p->tCCD_L), tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS), 9010394Swendy.elsasser@arm.com tWR(p->tWR), tRTP(p->tRTP), tRFC(p->tRFC), tREFI(p->tREFI), tRRD(p->tRRD), 9111673SOmar.Naji@arm.com tRRD_L(p->tRRD_L), tXAW(p->tXAW), tXP(p->tXP), tXS(p->tXS), 9212706Swendy.elsasser@arm.com activationLimit(p->activation_limit), rankToRankDly(tCS + tBURST), 9312706Swendy.elsasser@arm.com wrToRdDly(tCL + tBURST + p->tWTR), rdToWrDly(tRTW + tBURST), 949243SN/A memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping), 959243SN/A pageMgmt(p->page_policy), 9610141SN/A maxAccessesPerRow(p->max_accesses_per_row), 979726SN/A frontendLatency(p->static_frontend_latency), 989726SN/A backendLatency(p->static_backend_latency), 9912706Swendy.elsasser@arm.com nextBurstAt(0), prevArrival(0), 10012266Sradhika.jagtap@arm.com nextReqTime(0), activeRank(0), timeStampOffset(0), 10112266Sradhika.jagtap@arm.com lastStatsResetTick(0) 1029243SN/A{ 10310620Sandreas.hansson@arm.com // sanity check the ranks since we rely on bit slicing for the 10410620Sandreas.hansson@arm.com // address decoding 10510620Sandreas.hansson@arm.com fatal_if(!isPowerOf2(ranksPerChannel), "DRAM rank count of %d is not " 10610620Sandreas.hansson@arm.com "allowed, must be a power of two\n", ranksPerChannel); 10710620Sandreas.hansson@arm.com 10810889Sandreas.hansson@arm.com fatal_if(!isPowerOf2(burstSize), "DRAM burst size %d is not allowed, " 10910889Sandreas.hansson@arm.com "must be a power of two\n", burstSize); 11010889Sandreas.hansson@arm.com 11110618SOmar.Naji@arm.com for (int i = 0; i < ranksPerChannel; i++) { 11212081Sspwilson2@wisc.edu Rank* rank = new Rank(*this, p, i); 11310618SOmar.Naji@arm.com ranks.push_back(rank); 11410246Sandreas.hansson@arm.com } 11510246Sandreas.hansson@arm.com 11610140SN/A // perform a basic check of the write thresholds 11710140SN/A if (p->write_low_thresh_perc >= p->write_high_thresh_perc) 11810140SN/A fatal("Write buffer low threshold %d must be smaller than the " 11910140SN/A "high threshold %d\n", p->write_low_thresh_perc, 12010140SN/A p->write_high_thresh_perc); 1219243SN/A 1229243SN/A // determine the rows per bank by looking at the total capacity 1239567SN/A uint64_t capacity = ULL(1) << ceilLog2(AbstractMemory::size()); 1249243SN/A 12510489SOmar.Naji@arm.com // determine the dram actual capacity from the DRAM config in Mbytes 12610489SOmar.Naji@arm.com uint64_t deviceCapacity = deviceSize / (1024 * 1024) * devicesPerRank * 12710489SOmar.Naji@arm.com ranksPerChannel; 12810489SOmar.Naji@arm.com 12910489SOmar.Naji@arm.com // if actual DRAM size does not match memory capacity in system warn! 13010489SOmar.Naji@arm.com if (deviceCapacity != capacity / (1024 * 1024)) 13110489SOmar.Naji@arm.com warn("DRAM device capacity (%d Mbytes) does not match the " 13210489SOmar.Naji@arm.com "address range assigned (%d Mbytes)\n", deviceCapacity, 13310489SOmar.Naji@arm.com capacity / (1024 * 1024)); 13410489SOmar.Naji@arm.com 1359243SN/A DPRINTF(DRAM, "Memory capacity %lld (%lld) bytes\n", capacity, 1369243SN/A AbstractMemory::size()); 1379831SN/A 1389831SN/A DPRINTF(DRAM, "Row buffer size %d bytes with %d columns per row buffer\n", 1399831SN/A rowBufferSize, columnsPerRowBuffer); 1409831SN/A 1419831SN/A rowsPerBank = capacity / (rowBufferSize * banksPerRank * ranksPerChannel); 1429243SN/A 14310207Sandreas.hansson@arm.com // some basic sanity checks 14410207Sandreas.hansson@arm.com if (tREFI <= tRP || tREFI <= tRFC) { 14510207Sandreas.hansson@arm.com fatal("tREFI (%d) must be larger than tRP (%d) and tRFC (%d)\n", 14610207Sandreas.hansson@arm.com tREFI, tRP, tRFC); 14710207Sandreas.hansson@arm.com } 14810394Swendy.elsasser@arm.com 14910394Swendy.elsasser@arm.com // basic bank group architecture checks -> 15010394Swendy.elsasser@arm.com if (bankGroupArch) { 15110394Swendy.elsasser@arm.com // must have at least one bank per bank group 15210394Swendy.elsasser@arm.com if (bankGroupsPerRank > banksPerRank) { 15310394Swendy.elsasser@arm.com fatal("banks per rank (%d) must be equal to or larger than " 15410394Swendy.elsasser@arm.com "banks groups per rank (%d)\n", 15510394Swendy.elsasser@arm.com banksPerRank, bankGroupsPerRank); 15610394Swendy.elsasser@arm.com } 15710394Swendy.elsasser@arm.com // must have same number of banks in each bank group 15810394Swendy.elsasser@arm.com if ((banksPerRank % bankGroupsPerRank) != 0) { 15910394Swendy.elsasser@arm.com fatal("Banks per rank (%d) must be evenly divisible by bank groups " 16010394Swendy.elsasser@arm.com "per rank (%d) for equal banks per bank group\n", 16110394Swendy.elsasser@arm.com banksPerRank, bankGroupsPerRank); 16210394Swendy.elsasser@arm.com } 16310394Swendy.elsasser@arm.com // tCCD_L should be greater than minimal, back-to-back burst delay 16410394Swendy.elsasser@arm.com if (tCCD_L <= tBURST) { 16510394Swendy.elsasser@arm.com fatal("tCCD_L (%d) should be larger than tBURST (%d) when " 16610394Swendy.elsasser@arm.com "bank groups per rank (%d) is greater than 1\n", 16710394Swendy.elsasser@arm.com tCCD_L, tBURST, bankGroupsPerRank); 16810394Swendy.elsasser@arm.com } 16912706Swendy.elsasser@arm.com // tCCD_L_WR should be greater than minimal, back-to-back burst delay 17012706Swendy.elsasser@arm.com if (tCCD_L_WR <= tBURST) { 17112706Swendy.elsasser@arm.com fatal("tCCD_L_WR (%d) should be larger than tBURST (%d) when " 17212706Swendy.elsasser@arm.com "bank groups per rank (%d) is greater than 1\n", 17312706Swendy.elsasser@arm.com tCCD_L_WR, tBURST, bankGroupsPerRank); 17412706Swendy.elsasser@arm.com } 17510394Swendy.elsasser@arm.com // tRRD_L is greater than minimal, same bank group ACT-to-ACT delay 17610561SOmar.Naji@arm.com // some datasheets might specify it equal to tRRD 17710561SOmar.Naji@arm.com if (tRRD_L < tRRD) { 17810394Swendy.elsasser@arm.com fatal("tRRD_L (%d) should be larger than tRRD (%d) when " 17910394Swendy.elsasser@arm.com "bank groups per rank (%d) is greater than 1\n", 18010394Swendy.elsasser@arm.com tRRD_L, tRRD, bankGroupsPerRank); 18110394Swendy.elsasser@arm.com } 18210394Swendy.elsasser@arm.com } 18310394Swendy.elsasser@arm.com 1849243SN/A} 1859243SN/A 1869243SN/Avoid 18710146Sandreas.hansson@arm.comDRAMCtrl::init() 18810140SN/A{ 18910466Sandreas.hansson@arm.com AbstractMemory::init(); 19010466Sandreas.hansson@arm.com 19110466Sandreas.hansson@arm.com if (!port.isConnected()) { 19210146Sandreas.hansson@arm.com fatal("DRAMCtrl %s is unconnected!\n", name()); 19310140SN/A } else { 19410140SN/A port.sendRangeChange(); 19510140SN/A } 19610646Sandreas.hansson@arm.com 19710646Sandreas.hansson@arm.com // a bit of sanity checks on the interleaving, save it for here to 19810646Sandreas.hansson@arm.com // ensure that the system pointer is initialised 19910646Sandreas.hansson@arm.com if (range.interleaved()) { 20010646Sandreas.hansson@arm.com if (channels != range.stripes()) 20110646Sandreas.hansson@arm.com fatal("%s has %d interleaved address stripes but %d channel(s)\n", 20210646Sandreas.hansson@arm.com name(), range.stripes(), channels); 20310646Sandreas.hansson@arm.com 20410646Sandreas.hansson@arm.com if (addrMapping == Enums::RoRaBaChCo) { 20510646Sandreas.hansson@arm.com if (rowBufferSize != range.granularity()) { 20610646Sandreas.hansson@arm.com fatal("Channel interleaving of %s doesn't match RoRaBaChCo " 20710646Sandreas.hansson@arm.com "address map\n", name()); 20810646Sandreas.hansson@arm.com } 20910646Sandreas.hansson@arm.com } else if (addrMapping == Enums::RoRaBaCoCh || 21010646Sandreas.hansson@arm.com addrMapping == Enums::RoCoRaBaCh) { 21110646Sandreas.hansson@arm.com // for the interleavings with channel bits in the bottom, 21210646Sandreas.hansson@arm.com // if the system uses a channel striping granularity that 21310646Sandreas.hansson@arm.com // is larger than the DRAM burst size, then map the 21410646Sandreas.hansson@arm.com // sequential accesses within a stripe to a number of 21510646Sandreas.hansson@arm.com // columns in the DRAM, effectively placing some of the 21610646Sandreas.hansson@arm.com // lower-order column bits as the least-significant bits 21710646Sandreas.hansson@arm.com // of the address (above the ones denoting the burst size) 21810646Sandreas.hansson@arm.com assert(columnsPerStripe >= 1); 21910646Sandreas.hansson@arm.com 22010646Sandreas.hansson@arm.com // channel striping has to be done at a granularity that 22110646Sandreas.hansson@arm.com // is equal or larger to a cache line 22210646Sandreas.hansson@arm.com if (system()->cacheLineSize() > range.granularity()) { 22310646Sandreas.hansson@arm.com fatal("Channel interleaving of %s must be at least as large " 22410646Sandreas.hansson@arm.com "as the cache line size\n", name()); 22510646Sandreas.hansson@arm.com } 22610646Sandreas.hansson@arm.com 22710646Sandreas.hansson@arm.com // ...and equal or smaller than the row-buffer size 22810646Sandreas.hansson@arm.com if (rowBufferSize < range.granularity()) { 22910646Sandreas.hansson@arm.com fatal("Channel interleaving of %s must be at most as large " 23010646Sandreas.hansson@arm.com "as the row-buffer size\n", name()); 23110646Sandreas.hansson@arm.com } 23210646Sandreas.hansson@arm.com // this is essentially the check above, so just to be sure 23310646Sandreas.hansson@arm.com assert(columnsPerStripe <= columnsPerRowBuffer); 23410646Sandreas.hansson@arm.com } 23510646Sandreas.hansson@arm.com } 23610140SN/A} 23710140SN/A 23810140SN/Avoid 23910146Sandreas.hansson@arm.comDRAMCtrl::startup() 2409243SN/A{ 24110619Sandreas.hansson@arm.com // remember the memory system mode of operation 24210619Sandreas.hansson@arm.com isTimingMode = system()->isTimingMode(); 24310618SOmar.Naji@arm.com 24410619Sandreas.hansson@arm.com if (isTimingMode) { 24510619Sandreas.hansson@arm.com // timestamp offset should be in clock cycles for DRAMPower 24610619Sandreas.hansson@arm.com timeStampOffset = divCeil(curTick(), tCK); 24710619Sandreas.hansson@arm.com 24810619Sandreas.hansson@arm.com // update the start tick for the precharge accounting to the 24910619Sandreas.hansson@arm.com // current tick 25010619Sandreas.hansson@arm.com for (auto r : ranks) { 25110619Sandreas.hansson@arm.com r->startup(curTick() + tREFI - tRP); 25210619Sandreas.hansson@arm.com } 25310619Sandreas.hansson@arm.com 25410619Sandreas.hansson@arm.com // shift the bus busy time sufficiently far ahead that we never 25510619Sandreas.hansson@arm.com // have to worry about negative values when computing the time for 25610619Sandreas.hansson@arm.com // the next request, this will add an insignificant bubble at the 25710619Sandreas.hansson@arm.com // start of simulation 25812706Swendy.elsasser@arm.com nextBurstAt = curTick() + tRP + tRCD; 25910618SOmar.Naji@arm.com } 2609243SN/A} 2619243SN/A 2629243SN/ATick 26310146Sandreas.hansson@arm.comDRAMCtrl::recvAtomic(PacketPtr pkt) 2649243SN/A{ 2659243SN/A DPRINTF(DRAM, "recvAtomic: %s 0x%x\n", pkt->cmdString(), pkt->getAddr()); 2669243SN/A 26711334Sandreas.hansson@arm.com panic_if(pkt->cacheResponding(), "Should not see packets where cache " 26811334Sandreas.hansson@arm.com "is responding"); 26911334Sandreas.hansson@arm.com 2709243SN/A // do the actual memory access and turn the packet into a response 2719243SN/A access(pkt); 2729243SN/A 2739243SN/A Tick latency = 0; 27411334Sandreas.hansson@arm.com if (pkt->hasData()) { 2759243SN/A // this value is not supposed to be accurate, just enough to 2769243SN/A // keep things going, mimic a closed page 2779243SN/A latency = tRP + tRCD + tCL; 2789243SN/A } 2799243SN/A return latency; 2809243SN/A} 2819243SN/A 2829243SN/Abool 28310146Sandreas.hansson@arm.comDRAMCtrl::readQueueFull(unsigned int neededEntries) const 2849243SN/A{ 2859831SN/A DPRINTF(DRAM, "Read queue limit %d, current size %d, entries needed %d\n", 2869831SN/A readBufferSize, readQueue.size() + respQueue.size(), 2879831SN/A neededEntries); 2889243SN/A 2899831SN/A return 2909831SN/A (readQueue.size() + respQueue.size() + neededEntries) > readBufferSize; 2919243SN/A} 2929243SN/A 2939243SN/Abool 29410146Sandreas.hansson@arm.comDRAMCtrl::writeQueueFull(unsigned int neededEntries) const 2959243SN/A{ 2969831SN/A DPRINTF(DRAM, "Write queue limit %d, current size %d, entries needed %d\n", 2979831SN/A writeBufferSize, writeQueue.size(), neededEntries); 2989831SN/A return (writeQueue.size() + neededEntries) > writeBufferSize; 2999243SN/A} 3009243SN/A 30110146Sandreas.hansson@arm.comDRAMCtrl::DRAMPacket* 30210146Sandreas.hansson@arm.comDRAMCtrl::decodeAddr(PacketPtr pkt, Addr dramPktAddr, unsigned size, 30310143SN/A bool isRead) 3049243SN/A{ 3059669SN/A // decode the address based on the address mapping scheme, with 30610136SN/A // Ro, Ra, Co, Ba and Ch denoting row, rank, column, bank and 30710136SN/A // channel, respectively 3089243SN/A uint8_t rank; 3099967SN/A uint8_t bank; 31010245Sandreas.hansson@arm.com // use a 64-bit unsigned during the computations as the row is 31110245Sandreas.hansson@arm.com // always the top bits, and check before creating the DRAMPacket 31210245Sandreas.hansson@arm.com uint64_t row; 3139243SN/A 31410286Sandreas.hansson@arm.com // truncate the address to a DRAM burst, which makes it unique to 31510286Sandreas.hansson@arm.com // a specific column, row, bank, rank and channel 3169831SN/A Addr addr = dramPktAddr / burstSize; 3179243SN/A 3189491SN/A // we have removed the lowest order address bits that denote the 3199831SN/A // position within the column 32010136SN/A if (addrMapping == Enums::RoRaBaChCo) { 3219491SN/A // the lowest order bits denote the column to ensure that 3229491SN/A // sequential cache lines occupy the same row 3239831SN/A addr = addr / columnsPerRowBuffer; 3249243SN/A 3259669SN/A // take out the channel part of the address 3269566SN/A addr = addr / channels; 3279566SN/A 3289669SN/A // after the channel bits, get the bank bits to interleave 3299669SN/A // over the banks 3309669SN/A bank = addr % banksPerRank; 3319669SN/A addr = addr / banksPerRank; 3329669SN/A 3339669SN/A // after the bank, we get the rank bits which thus interleaves 3349669SN/A // over the ranks 3359669SN/A rank = addr % ranksPerChannel; 3369669SN/A addr = addr / ranksPerChannel; 3379669SN/A 33811189Sandreas.hansson@arm.com // lastly, get the row bits, no need to remove them from addr 3399669SN/A row = addr % rowsPerBank; 34010136SN/A } else if (addrMapping == Enums::RoRaBaCoCh) { 34110286Sandreas.hansson@arm.com // take out the lower-order column bits 34210286Sandreas.hansson@arm.com addr = addr / columnsPerStripe; 34310286Sandreas.hansson@arm.com 3449669SN/A // take out the channel part of the address 3459669SN/A addr = addr / channels; 3469669SN/A 34710286Sandreas.hansson@arm.com // next, the higher-order column bites 34810286Sandreas.hansson@arm.com addr = addr / (columnsPerRowBuffer / columnsPerStripe); 3499669SN/A 3509669SN/A // after the column bits, we get the bank bits to interleave 3519491SN/A // over the banks 3529243SN/A bank = addr % banksPerRank; 3539243SN/A addr = addr / banksPerRank; 3549243SN/A 3559491SN/A // after the bank, we get the rank bits which thus interleaves 3569491SN/A // over the ranks 3579243SN/A rank = addr % ranksPerChannel; 3589243SN/A addr = addr / ranksPerChannel; 3599243SN/A 36011189Sandreas.hansson@arm.com // lastly, get the row bits, no need to remove them from addr 3619243SN/A row = addr % rowsPerBank; 36210136SN/A } else if (addrMapping == Enums::RoCoRaBaCh) { 3639491SN/A // optimise for closed page mode and utilise maximum 3649491SN/A // parallelism of the DRAM (at the cost of power) 3659491SN/A 36610286Sandreas.hansson@arm.com // take out the lower-order column bits 36710286Sandreas.hansson@arm.com addr = addr / columnsPerStripe; 36810286Sandreas.hansson@arm.com 3699566SN/A // take out the channel part of the address, not that this has 3709566SN/A // to match with how accesses are interleaved between the 3719566SN/A // controllers in the address mapping 3729566SN/A addr = addr / channels; 3739566SN/A 3749491SN/A // start with the bank bits, as this provides the maximum 3759491SN/A // opportunity for parallelism between requests 3769243SN/A bank = addr % banksPerRank; 3779243SN/A addr = addr / banksPerRank; 3789243SN/A 3799491SN/A // next get the rank bits 3809243SN/A rank = addr % ranksPerChannel; 3819243SN/A addr = addr / ranksPerChannel; 3829243SN/A 38310286Sandreas.hansson@arm.com // next, the higher-order column bites 38410286Sandreas.hansson@arm.com addr = addr / (columnsPerRowBuffer / columnsPerStripe); 3859243SN/A 38611189Sandreas.hansson@arm.com // lastly, get the row bits, no need to remove them from addr 3879243SN/A row = addr % rowsPerBank; 3889243SN/A } else 3899243SN/A panic("Unknown address mapping policy chosen!"); 3909243SN/A 3919243SN/A assert(rank < ranksPerChannel); 3929243SN/A assert(bank < banksPerRank); 3939243SN/A assert(row < rowsPerBank); 39410245Sandreas.hansson@arm.com assert(row < Bank::NO_ROW); 3959243SN/A 3969243SN/A DPRINTF(DRAM, "Address: %lld Rank %d Bank %d Row %d\n", 3979831SN/A dramPktAddr, rank, bank, row); 3989243SN/A 3999243SN/A // create the corresponding DRAM packet with the entry time and 4009567SN/A // ready time set to the current tick, the latter will be updated 4019567SN/A // later 4029967SN/A uint16_t bank_id = banksPerRank * rank + bank; 4039967SN/A return new DRAMPacket(pkt, isRead, rank, bank, row, bank_id, dramPktAddr, 40410618SOmar.Naji@arm.com size, ranks[rank]->banks[bank], *ranks[rank]); 4059243SN/A} 4069243SN/A 4079243SN/Avoid 40810146Sandreas.hansson@arm.comDRAMCtrl::addToReadQueue(PacketPtr pkt, unsigned int pktCount) 4099243SN/A{ 4109243SN/A // only add to the read queue here. whenever the request is 4119243SN/A // eventually done, set the readyTime, and call schedule() 4129243SN/A assert(!pkt->isWrite()); 4139243SN/A 4149831SN/A assert(pktCount != 0); 4159831SN/A 4169831SN/A // if the request size is larger than burst size, the pkt is split into 4179831SN/A // multiple DRAM packets 4189831SN/A // Note if the pkt starting address is not aligened to burst size, the 4199831SN/A // address of first DRAM packet is kept unaliged. Subsequent DRAM packets 4209831SN/A // are aligned to burst size boundaries. This is to ensure we accurately 4219831SN/A // check read packets against packets in write queue. 4229243SN/A Addr addr = pkt->getAddr(); 4239831SN/A unsigned pktsServicedByWrQ = 0; 4249831SN/A BurstHelper* burst_helper = NULL; 4259831SN/A for (int cnt = 0; cnt < pktCount; ++cnt) { 4269831SN/A unsigned size = std::min((addr | (burstSize - 1)) + 1, 4279831SN/A pkt->getAddr() + pkt->getSize()) - addr; 4289831SN/A readPktSize[ceilLog2(size)]++; 4299831SN/A readBursts++; 4309243SN/A 4319831SN/A // First check write buffer to see if the data is already at 4329831SN/A // the controller 4339831SN/A bool foundInWrQ = false; 43410889Sandreas.hansson@arm.com Addr burst_addr = burstAlign(addr); 43510889Sandreas.hansson@arm.com // if the burst address is not present then there is no need 43610889Sandreas.hansson@arm.com // looking any further 43710889Sandreas.hansson@arm.com if (isInWriteQueue.find(burst_addr) != isInWriteQueue.end()) { 43810889Sandreas.hansson@arm.com for (const auto& p : writeQueue) { 43910889Sandreas.hansson@arm.com // check if the read is subsumed in the write queue 44010889Sandreas.hansson@arm.com // packet we are looking at 44110889Sandreas.hansson@arm.com if (p->addr <= addr && (addr + size) <= (p->addr + p->size)) { 44210889Sandreas.hansson@arm.com foundInWrQ = true; 44310889Sandreas.hansson@arm.com servicedByWrQ++; 44410889Sandreas.hansson@arm.com pktsServicedByWrQ++; 44510889Sandreas.hansson@arm.com DPRINTF(DRAM, "Read to addr %lld with size %d serviced by " 44610889Sandreas.hansson@arm.com "write queue\n", addr, size); 44710889Sandreas.hansson@arm.com bytesReadWrQ += burstSize; 44810889Sandreas.hansson@arm.com break; 44910889Sandreas.hansson@arm.com } 4509831SN/A } 4519243SN/A } 4529831SN/A 4539831SN/A // If not found in the write q, make a DRAM packet and 4549831SN/A // push it onto the read queue 4559831SN/A if (!foundInWrQ) { 4569831SN/A 4579831SN/A // Make the burst helper for split packets 4589831SN/A if (pktCount > 1 && burst_helper == NULL) { 4599831SN/A DPRINTF(DRAM, "Read to addr %lld translates to %d " 4609831SN/A "dram requests\n", pkt->getAddr(), pktCount); 4619831SN/A burst_helper = new BurstHelper(pktCount); 4629831SN/A } 4639831SN/A 4649966SN/A DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, true); 4659831SN/A dram_pkt->burstHelper = burst_helper; 4669831SN/A 4679831SN/A assert(!readQueueFull(1)); 4689831SN/A rdQLenPdf[readQueue.size() + respQueue.size()]++; 4699831SN/A 4709831SN/A DPRINTF(DRAM, "Adding to read queue\n"); 4719831SN/A 4729831SN/A readQueue.push_back(dram_pkt); 4739831SN/A 47411678Swendy.elsasser@arm.com // increment read entries of the rank 47511678Swendy.elsasser@arm.com ++dram_pkt->rankRef.readEntries; 47611678Swendy.elsasser@arm.com 4779831SN/A // Update stats 4789831SN/A avgRdQLen = readQueue.size() + respQueue.size(); 4799831SN/A } 4809831SN/A 4819831SN/A // Starting address of next dram pkt (aligend to burstSize boundary) 4829831SN/A addr = (addr | (burstSize - 1)) + 1; 4839243SN/A } 4849243SN/A 4859831SN/A // If all packets are serviced by write queue, we send the repsonse back 4869831SN/A if (pktsServicedByWrQ == pktCount) { 4879831SN/A accessAndRespond(pkt, frontendLatency); 4889831SN/A return; 4899831SN/A } 4909243SN/A 4919831SN/A // Update how many split packets are serviced by write queue 4929831SN/A if (burst_helper != NULL) 4939831SN/A burst_helper->burstsServiced = pktsServicedByWrQ; 4949243SN/A 49510206Sandreas.hansson@arm.com // If we are not already scheduled to get a request out of the 49610206Sandreas.hansson@arm.com // queue, do so now 49710206Sandreas.hansson@arm.com if (!nextReqEvent.scheduled()) { 4989567SN/A DPRINTF(DRAM, "Request scheduled immediately\n"); 4999567SN/A schedule(nextReqEvent, curTick()); 5009243SN/A } 5019243SN/A} 5029243SN/A 5039243SN/Avoid 50410146Sandreas.hansson@arm.comDRAMCtrl::addToWriteQueue(PacketPtr pkt, unsigned int pktCount) 5059243SN/A{ 5069243SN/A // only add to the write queue here. whenever the request is 5079243SN/A // eventually done, set the readyTime, and call schedule() 5089243SN/A assert(pkt->isWrite()); 5099243SN/A 5109831SN/A // if the request size is larger than burst size, the pkt is split into 5119831SN/A // multiple DRAM packets 5129831SN/A Addr addr = pkt->getAddr(); 5139831SN/A for (int cnt = 0; cnt < pktCount; ++cnt) { 5149831SN/A unsigned size = std::min((addr | (burstSize - 1)) + 1, 5159831SN/A pkt->getAddr() + pkt->getSize()) - addr; 5169831SN/A writePktSize[ceilLog2(size)]++; 5179831SN/A writeBursts++; 5189243SN/A 5199832SN/A // see if we can merge with an existing item in the write 52010889Sandreas.hansson@arm.com // queue and keep track of whether we have merged or not 52110889Sandreas.hansson@arm.com bool merged = isInWriteQueue.find(burstAlign(addr)) != 52210889Sandreas.hansson@arm.com isInWriteQueue.end(); 5239243SN/A 5249832SN/A // if the item was not merged we need to create a new write 5259832SN/A // and enqueue it 5269832SN/A if (!merged) { 5279966SN/A DRAMPacket* dram_pkt = decodeAddr(pkt, addr, size, false); 5289243SN/A 5299832SN/A assert(writeQueue.size() < writeBufferSize); 5309832SN/A wrQLenPdf[writeQueue.size()]++; 5319243SN/A 5329832SN/A DPRINTF(DRAM, "Adding to write queue\n"); 5339831SN/A 5349832SN/A writeQueue.push_back(dram_pkt); 53510889Sandreas.hansson@arm.com isInWriteQueue.insert(burstAlign(addr)); 53610889Sandreas.hansson@arm.com assert(writeQueue.size() == isInWriteQueue.size()); 5379831SN/A 5389832SN/A // Update stats 5399832SN/A avgWrQLen = writeQueue.size(); 54011678Swendy.elsasser@arm.com 54111678Swendy.elsasser@arm.com // increment write entries of the rank 54211678Swendy.elsasser@arm.com ++dram_pkt->rankRef.writeEntries; 5439977SN/A } else { 54410889Sandreas.hansson@arm.com DPRINTF(DRAM, "Merging write burst with existing queue entry\n"); 54510889Sandreas.hansson@arm.com 5469977SN/A // keep track of the fact that this burst effectively 5479977SN/A // disappeared as it was merged with an existing one 5489977SN/A mergedWrBursts++; 5499832SN/A } 5509832SN/A 5519831SN/A // Starting address of next dram pkt (aligend to burstSize boundary) 5529831SN/A addr = (addr | (burstSize - 1)) + 1; 5539831SN/A } 5549243SN/A 5559243SN/A // we do not wait for the writes to be send to the actual memory, 5569243SN/A // but instead take responsibility for the consistency here and 5579243SN/A // snoop the write queue for any upcoming reads 5589831SN/A // @todo, if a pkt size is larger than burst size, we might need a 5599831SN/A // different front end latency 5609726SN/A accessAndRespond(pkt, frontendLatency); 5619243SN/A 56210206Sandreas.hansson@arm.com // If we are not already scheduled to get a request out of the 56310206Sandreas.hansson@arm.com // queue, do so now 56410206Sandreas.hansson@arm.com if (!nextReqEvent.scheduled()) { 56510206Sandreas.hansson@arm.com DPRINTF(DRAM, "Request scheduled immediately\n"); 56610206Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 5679243SN/A } 5689243SN/A} 5699243SN/A 5709243SN/Avoid 57110146Sandreas.hansson@arm.comDRAMCtrl::printQs() const { 5729243SN/A DPRINTF(DRAM, "===READ QUEUE===\n\n"); 5739833SN/A for (auto i = readQueue.begin() ; i != readQueue.end() ; ++i) { 5749243SN/A DPRINTF(DRAM, "Read %lu\n", (*i)->addr); 5759243SN/A } 5769243SN/A DPRINTF(DRAM, "\n===RESP QUEUE===\n\n"); 5779833SN/A for (auto i = respQueue.begin() ; i != respQueue.end() ; ++i) { 5789243SN/A DPRINTF(DRAM, "Response %lu\n", (*i)->addr); 5799243SN/A } 5809243SN/A DPRINTF(DRAM, "\n===WRITE QUEUE===\n\n"); 5819833SN/A for (auto i = writeQueue.begin() ; i != writeQueue.end() ; ++i) { 5829243SN/A DPRINTF(DRAM, "Write %lu\n", (*i)->addr); 5839243SN/A } 5849243SN/A} 5859243SN/A 5869243SN/Abool 58710146Sandreas.hansson@arm.comDRAMCtrl::recvTimingReq(PacketPtr pkt) 5889243SN/A{ 5899243SN/A // This is where we enter from the outside world 5909567SN/A DPRINTF(DRAM, "recvTimingReq: request %s addr %lld size %d\n", 5919831SN/A pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 5929243SN/A 59311334Sandreas.hansson@arm.com panic_if(pkt->cacheResponding(), "Should not see packets where cache " 59411334Sandreas.hansson@arm.com "is responding"); 59511334Sandreas.hansson@arm.com 59611334Sandreas.hansson@arm.com panic_if(!(pkt->isRead() || pkt->isWrite()), 59711334Sandreas.hansson@arm.com "Should only see read and writes at memory controller\n"); 5989243SN/A 5999243SN/A // Calc avg gap between requests 6009243SN/A if (prevArrival != 0) { 6019243SN/A totGap += curTick() - prevArrival; 6029243SN/A } 6039243SN/A prevArrival = curTick(); 6049243SN/A 6059831SN/A 6069831SN/A // Find out how many dram packets a pkt translates to 6079831SN/A // If the burst size is equal or larger than the pkt size, then a pkt 6089831SN/A // translates to only one dram packet. Otherwise, a pkt translates to 6099831SN/A // multiple dram packets 6109243SN/A unsigned size = pkt->getSize(); 6119831SN/A unsigned offset = pkt->getAddr() & (burstSize - 1); 6129831SN/A unsigned int dram_pkt_count = divCeil(offset + size, burstSize); 6139243SN/A 6149243SN/A // check local buffers and do not accept if full 6159243SN/A if (pkt->isRead()) { 6169567SN/A assert(size != 0); 6179831SN/A if (readQueueFull(dram_pkt_count)) { 6189567SN/A DPRINTF(DRAM, "Read queue full, not accepting\n"); 6199243SN/A // remember that we have to retry this port 6209243SN/A retryRdReq = true; 6219243SN/A numRdRetry++; 6229243SN/A return false; 6239243SN/A } else { 6249831SN/A addToReadQueue(pkt, dram_pkt_count); 6259243SN/A readReqs++; 6269977SN/A bytesReadSys += size; 6279243SN/A } 62811334Sandreas.hansson@arm.com } else { 62911334Sandreas.hansson@arm.com assert(pkt->isWrite()); 6309567SN/A assert(size != 0); 6319831SN/A if (writeQueueFull(dram_pkt_count)) { 6329567SN/A DPRINTF(DRAM, "Write queue full, not accepting\n"); 6339243SN/A // remember that we have to retry this port 6349243SN/A retryWrReq = true; 6359243SN/A numWrRetry++; 6369243SN/A return false; 6379243SN/A } else { 6389831SN/A addToWriteQueue(pkt, dram_pkt_count); 6399243SN/A writeReqs++; 6409977SN/A bytesWrittenSys += size; 6419243SN/A } 6429243SN/A } 6439243SN/A 6449243SN/A return true; 6459243SN/A} 6469243SN/A 6479243SN/Avoid 64810146Sandreas.hansson@arm.comDRAMCtrl::processRespondEvent() 6499243SN/A{ 6509243SN/A DPRINTF(DRAM, 6519243SN/A "processRespondEvent(): Some req has reached its readyTime\n"); 6529243SN/A 6539831SN/A DRAMPacket* dram_pkt = respQueue.front(); 6549243SN/A 65511678Swendy.elsasser@arm.com // if a read has reached its ready-time, decrement the number of reads 65611678Swendy.elsasser@arm.com // At this point the packet has been handled and there is a possibility 65711678Swendy.elsasser@arm.com // to switch to low-power mode if no other packet is available 65811678Swendy.elsasser@arm.com --dram_pkt->rankRef.readEntries; 65911678Swendy.elsasser@arm.com DPRINTF(DRAM, "number of read entries for rank %d is %d\n", 66011678Swendy.elsasser@arm.com dram_pkt->rank, dram_pkt->rankRef.readEntries); 66111678Swendy.elsasser@arm.com 66211678Swendy.elsasser@arm.com // counter should at least indicate one outstanding request 66311678Swendy.elsasser@arm.com // for this read 66411678Swendy.elsasser@arm.com assert(dram_pkt->rankRef.outstandingEvents > 0); 66511678Swendy.elsasser@arm.com // read response received, decrement count 66611678Swendy.elsasser@arm.com --dram_pkt->rankRef.outstandingEvents; 66711678Swendy.elsasser@arm.com 66811846Swendy.elsasser@arm.com // at this moment should not have transitioned to a low-power state 66911846Swendy.elsasser@arm.com assert((dram_pkt->rankRef.pwrState != PWR_SREF) && 67011846Swendy.elsasser@arm.com (dram_pkt->rankRef.pwrState != PWR_PRE_PDN) && 67111846Swendy.elsasser@arm.com (dram_pkt->rankRef.pwrState != PWR_ACT_PDN)); 67211678Swendy.elsasser@arm.com 67311678Swendy.elsasser@arm.com // track if this is the last packet before idling 67411678Swendy.elsasser@arm.com // and that there are no outstanding commands to this rank 67512705Swendy.elsasser@arm.com if (dram_pkt->rankRef.isQueueEmpty() && 67612705Swendy.elsasser@arm.com dram_pkt->rankRef.outstandingEvents == 0) { 67711678Swendy.elsasser@arm.com // verify that there are no events scheduled 67811678Swendy.elsasser@arm.com assert(!dram_pkt->rankRef.activateEvent.scheduled()); 67911678Swendy.elsasser@arm.com assert(!dram_pkt->rankRef.prechargeEvent.scheduled()); 68011678Swendy.elsasser@arm.com 68111678Swendy.elsasser@arm.com // if coming from active state, schedule power event to 68211678Swendy.elsasser@arm.com // active power-down else go to precharge power-down 68311678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Rank %d sleep at tick %d; current power state is " 68411678Swendy.elsasser@arm.com "%d\n", dram_pkt->rank, curTick(), dram_pkt->rankRef.pwrState); 68511678Swendy.elsasser@arm.com 68611678Swendy.elsasser@arm.com // default to ACT power-down unless already in IDLE state 68711678Swendy.elsasser@arm.com // could be in IDLE if PRE issued before data returned 68811678Swendy.elsasser@arm.com PowerState next_pwr_state = PWR_ACT_PDN; 68911678Swendy.elsasser@arm.com if (dram_pkt->rankRef.pwrState == PWR_IDLE) { 69011678Swendy.elsasser@arm.com next_pwr_state = PWR_PRE_PDN; 69111678Swendy.elsasser@arm.com } 69211678Swendy.elsasser@arm.com 69311678Swendy.elsasser@arm.com dram_pkt->rankRef.powerDownSleep(next_pwr_state, curTick()); 69411678Swendy.elsasser@arm.com } 69511678Swendy.elsasser@arm.com 6969831SN/A if (dram_pkt->burstHelper) { 6979831SN/A // it is a split packet 6989831SN/A dram_pkt->burstHelper->burstsServiced++; 6999831SN/A if (dram_pkt->burstHelper->burstsServiced == 70010143SN/A dram_pkt->burstHelper->burstCount) { 7019831SN/A // we have now serviced all children packets of a system packet 7029831SN/A // so we can now respond to the requester 7039831SN/A // @todo we probably want to have a different front end and back 7049831SN/A // end latency for split packets 7059831SN/A accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 7069831SN/A delete dram_pkt->burstHelper; 7079831SN/A dram_pkt->burstHelper = NULL; 7089831SN/A } 7099831SN/A } else { 7109831SN/A // it is not a split packet 7119831SN/A accessAndRespond(dram_pkt->pkt, frontendLatency + backendLatency); 7129831SN/A } 7139243SN/A 7149831SN/A delete respQueue.front(); 7159831SN/A respQueue.pop_front(); 7169243SN/A 7179831SN/A if (!respQueue.empty()) { 7189831SN/A assert(respQueue.front()->readyTime >= curTick()); 7199831SN/A assert(!respondEvent.scheduled()); 7209831SN/A schedule(respondEvent, respQueue.front()->readyTime); 7219831SN/A } else { 7229831SN/A // if there is nothing left in any queue, signal a drain 72310913Sandreas.sandberg@arm.com if (drainState() == DrainState::Draining && 72411676Swendy.elsasser@arm.com writeQueue.empty() && readQueue.empty() && allRanksDrained()) { 72510913Sandreas.sandberg@arm.com 72610509SAli.Saidi@ARM.com DPRINTF(Drain, "DRAM controller done draining\n"); 72710913Sandreas.sandberg@arm.com signalDrainDone(); 7289831SN/A } 7299831SN/A } 7309567SN/A 7319831SN/A // We have made a location in the queue available at this point, 7329831SN/A // so if there is a read that was forced to wait, retry now 7339831SN/A if (retryRdReq) { 7349831SN/A retryRdReq = false; 73510713Sandreas.hansson@arm.com port.sendRetryReq(); 7369831SN/A } 7379243SN/A} 7389243SN/A 73910618SOmar.Naji@arm.combool 74010890Swendy.elsasser@arm.comDRAMCtrl::chooseNext(std::deque<DRAMPacket*>& queue, Tick extra_col_delay) 7419243SN/A{ 74210206Sandreas.hansson@arm.com // This method does the arbitration between requests. The chosen 74310206Sandreas.hansson@arm.com // packet is simply moved to the head of the queue. The other 74410206Sandreas.hansson@arm.com // methods know that this is the place to look. For example, with 74510206Sandreas.hansson@arm.com // FCFS, this method does nothing 74610206Sandreas.hansson@arm.com assert(!queue.empty()); 7479243SN/A 74810618SOmar.Naji@arm.com // bool to indicate if a packet to an available rank is found 74910618SOmar.Naji@arm.com bool found_packet = false; 75010206Sandreas.hansson@arm.com if (queue.size() == 1) { 75110618SOmar.Naji@arm.com DRAMPacket* dram_pkt = queue.front(); 75210618SOmar.Naji@arm.com // available rank corresponds to state refresh idle 75312266Sradhika.jagtap@arm.com if (ranks[dram_pkt->rank]->inRefIdleState()) { 75410618SOmar.Naji@arm.com found_packet = true; 75510618SOmar.Naji@arm.com DPRINTF(DRAM, "Single request, going to a free rank\n"); 75610618SOmar.Naji@arm.com } else { 75710618SOmar.Naji@arm.com DPRINTF(DRAM, "Single request, going to a busy rank\n"); 75810618SOmar.Naji@arm.com } 75910618SOmar.Naji@arm.com return found_packet; 7609243SN/A } 7619243SN/A 7629243SN/A if (memSchedPolicy == Enums::fcfs) { 76310618SOmar.Naji@arm.com // check if there is a packet going to a free rank 76411321Ssteve.reinhardt@amd.com for (auto i = queue.begin(); i != queue.end() ; ++i) { 76510618SOmar.Naji@arm.com DRAMPacket* dram_pkt = *i; 76612266Sradhika.jagtap@arm.com if (ranks[dram_pkt->rank]->inRefIdleState()) { 76710618SOmar.Naji@arm.com queue.erase(i); 76810618SOmar.Naji@arm.com queue.push_front(dram_pkt); 76910618SOmar.Naji@arm.com found_packet = true; 77010618SOmar.Naji@arm.com break; 77110618SOmar.Naji@arm.com } 77210618SOmar.Naji@arm.com } 7739243SN/A } else if (memSchedPolicy == Enums::frfcfs) { 77410890Swendy.elsasser@arm.com found_packet = reorderQueue(queue, extra_col_delay); 7759243SN/A } else 7769243SN/A panic("No scheduling policy chosen\n"); 77710618SOmar.Naji@arm.com return found_packet; 7789243SN/A} 7799243SN/A 78010618SOmar.Naji@arm.combool 78110890Swendy.elsasser@arm.comDRAMCtrl::reorderQueue(std::deque<DRAMPacket*>& queue, Tick extra_col_delay) 7829974SN/A{ 78310890Swendy.elsasser@arm.com // Only determine this if needed 78412706Swendy.elsasser@arm.com vector<uint32_t> earliest_banks(ranksPerChannel, 0); 78512706Swendy.elsasser@arm.com 78612706Swendy.elsasser@arm.com // Has minBankPrep been called to populate earliest_banks? 78712706Swendy.elsasser@arm.com bool filled_earliest_banks = false; 78812706Swendy.elsasser@arm.com // can the PRE/ACT sequence be done without impacting utlization? 78910890Swendy.elsasser@arm.com bool hidden_bank_prep = false; 7909974SN/A 79110890Swendy.elsasser@arm.com // search for seamless row hits first, if no seamless row hit is 79210890Swendy.elsasser@arm.com // found then determine if there are other packets that can be issued 79310890Swendy.elsasser@arm.com // without incurring additional bus delay due to bank timing 79410890Swendy.elsasser@arm.com // Will select closed rows first to enable more open row possibilies 79510890Swendy.elsasser@arm.com // in future selections 79610890Swendy.elsasser@arm.com bool found_hidden_bank = false; 79710890Swendy.elsasser@arm.com 79810890Swendy.elsasser@arm.com // remember if we found a row hit, not seamless, but bank prepped 79910890Swendy.elsasser@arm.com // and ready 80010890Swendy.elsasser@arm.com bool found_prepped_pkt = false; 80110890Swendy.elsasser@arm.com 80210890Swendy.elsasser@arm.com // if we have no row hit, prepped or not, and no seamless packet, 80310890Swendy.elsasser@arm.com // just go for the earliest possible 8049974SN/A bool found_earliest_pkt = false; 80510890Swendy.elsasser@arm.com 80610618SOmar.Naji@arm.com auto selected_pkt_it = queue.end(); 8079974SN/A 80810890Swendy.elsasser@arm.com // time we need to issue a column command to be seamless 80912706Swendy.elsasser@arm.com const Tick min_col_at = std::max(nextBurstAt + extra_col_delay, curTick()); 81010890Swendy.elsasser@arm.com 8119974SN/A for (auto i = queue.begin(); i != queue.end() ; ++i) { 8129974SN/A DRAMPacket* dram_pkt = *i; 8139974SN/A const Bank& bank = dram_pkt->bankRef; 81412706Swendy.elsasser@arm.com const Tick col_allowed_at = dram_pkt->isRead ? bank.rdAllowedAt : 81512706Swendy.elsasser@arm.com bank.wrAllowedAt; 81610890Swendy.elsasser@arm.com 81712266Sradhika.jagtap@arm.com // check if rank is not doing a refresh and thus is available, if not, 81812266Sradhika.jagtap@arm.com // jump to the next packet 81912266Sradhika.jagtap@arm.com if (dram_pkt->rankRef.inRefIdleState()) { 82010890Swendy.elsasser@arm.com // check if it is a row hit 82110618SOmar.Naji@arm.com if (bank.openRow == dram_pkt->row) { 82210890Swendy.elsasser@arm.com // no additional rank-to-rank or same bank-group 82310890Swendy.elsasser@arm.com // delays, or we switched read/write and might as well 82410890Swendy.elsasser@arm.com // go for the row hit 82512706Swendy.elsasser@arm.com if (col_allowed_at <= min_col_at) { 82610890Swendy.elsasser@arm.com // FCFS within the hits, giving priority to 82710890Swendy.elsasser@arm.com // commands that can issue seamlessly, without 82810890Swendy.elsasser@arm.com // additional delay, such as same rank accesses 82910890Swendy.elsasser@arm.com // and/or different bank-group accesses 83010890Swendy.elsasser@arm.com DPRINTF(DRAM, "Seamless row buffer hit\n"); 83110618SOmar.Naji@arm.com selected_pkt_it = i; 83210890Swendy.elsasser@arm.com // no need to look through the remaining queue entries 83310618SOmar.Naji@arm.com break; 83410890Swendy.elsasser@arm.com } else if (!found_hidden_bank && !found_prepped_pkt) { 83510890Swendy.elsasser@arm.com // if we did not find a packet to a closed row that can 83610890Swendy.elsasser@arm.com // issue the bank commands without incurring delay, and 83710890Swendy.elsasser@arm.com // did not yet find a packet to a prepped row, remember 83810890Swendy.elsasser@arm.com // the current one 83910618SOmar.Naji@arm.com selected_pkt_it = i; 84010890Swendy.elsasser@arm.com found_prepped_pkt = true; 84110890Swendy.elsasser@arm.com DPRINTF(DRAM, "Prepped row buffer hit\n"); 84210618SOmar.Naji@arm.com } 84310890Swendy.elsasser@arm.com } else if (!found_earliest_pkt) { 84410890Swendy.elsasser@arm.com // if we have not initialised the bank status, do it 84510890Swendy.elsasser@arm.com // now, and only once per scheduling decisions 84612706Swendy.elsasser@arm.com if (!filled_earliest_banks) { 84710890Swendy.elsasser@arm.com // determine entries with earliest bank delay 84812706Swendy.elsasser@arm.com std::tie(earliest_banks, hidden_bank_prep) = 84910890Swendy.elsasser@arm.com minBankPrep(queue, min_col_at); 85012706Swendy.elsasser@arm.com filled_earliest_banks = true; 85110890Swendy.elsasser@arm.com } 85210211Sandreas.hansson@arm.com 85310890Swendy.elsasser@arm.com // bank is amongst first available banks 85410890Swendy.elsasser@arm.com // minBankPrep will give priority to packets that can 85510890Swendy.elsasser@arm.com // issue seamlessly 85612706Swendy.elsasser@arm.com if (bits(earliest_banks[dram_pkt->rank], 85712706Swendy.elsasser@arm.com dram_pkt->bank, dram_pkt->bank)) { 85810618SOmar.Naji@arm.com found_earliest_pkt = true; 85910890Swendy.elsasser@arm.com found_hidden_bank = hidden_bank_prep; 86010890Swendy.elsasser@arm.com 86110890Swendy.elsasser@arm.com // give priority to packets that can issue 86210890Swendy.elsasser@arm.com // bank commands 'behind the scenes' 86310890Swendy.elsasser@arm.com // any additional delay if any will be due to 86410890Swendy.elsasser@arm.com // col-to-col command requirements 86510890Swendy.elsasser@arm.com if (hidden_bank_prep || !found_prepped_pkt) 86610890Swendy.elsasser@arm.com selected_pkt_it = i; 86710618SOmar.Naji@arm.com } 8689974SN/A } 8699974SN/A } 8709974SN/A } 8719974SN/A 87210618SOmar.Naji@arm.com if (selected_pkt_it != queue.end()) { 87310618SOmar.Naji@arm.com DRAMPacket* selected_pkt = *selected_pkt_it; 87410618SOmar.Naji@arm.com queue.erase(selected_pkt_it); 87510618SOmar.Naji@arm.com queue.push_front(selected_pkt); 87610890Swendy.elsasser@arm.com return true; 87710618SOmar.Naji@arm.com } 87810890Swendy.elsasser@arm.com 87910890Swendy.elsasser@arm.com return false; 8809974SN/A} 8819974SN/A 8829974SN/Avoid 88310146Sandreas.hansson@arm.comDRAMCtrl::accessAndRespond(PacketPtr pkt, Tick static_latency) 8849243SN/A{ 8859243SN/A DPRINTF(DRAM, "Responding to Address %lld.. ",pkt->getAddr()); 8869243SN/A 8879243SN/A bool needsResponse = pkt->needsResponse(); 8889243SN/A // do the actual memory access which also turns the packet into a 8899243SN/A // response 8909243SN/A access(pkt); 8919243SN/A 8929243SN/A // turn packet around to go back to requester if response expected 8939243SN/A if (needsResponse) { 8949243SN/A // access already turned the packet into a response 8959243SN/A assert(pkt->isResponse()); 89610721SMarco.Balboni@ARM.com // response_time consumes the static latency and is charged also 89710721SMarco.Balboni@ARM.com // with headerDelay that takes into account the delay provided by 89810721SMarco.Balboni@ARM.com // the xbar and also the payloadDelay that takes into account the 89910721SMarco.Balboni@ARM.com // number of data beats. 90010721SMarco.Balboni@ARM.com Tick response_time = curTick() + static_latency + pkt->headerDelay + 90110721SMarco.Balboni@ARM.com pkt->payloadDelay; 90210721SMarco.Balboni@ARM.com // Here we reset the timing of the packet before sending it out. 90310694SMarco.Balboni@ARM.com pkt->headerDelay = pkt->payloadDelay = 0; 9049549SN/A 9059726SN/A // queue the packet in the response queue to be sent out after 9069726SN/A // the static latency has passed 90711194Sali.jafri@arm.com port.schedTimingResp(pkt, response_time, true); 9089243SN/A } else { 9099587SN/A // @todo the packet is going to be deleted, and the DRAMPacket 9109587SN/A // is still having a pointer to it 91111190Sandreas.hansson@arm.com pendingDelete.reset(pkt); 9129243SN/A } 9139243SN/A 9149243SN/A DPRINTF(DRAM, "Done\n"); 9159243SN/A 9169243SN/A return; 9179243SN/A} 9189243SN/A 9199243SN/Avoid 92010618SOmar.Naji@arm.comDRAMCtrl::activateBank(Rank& rank_ref, Bank& bank_ref, 92110618SOmar.Naji@arm.com Tick act_tick, uint32_t row) 9229488SN/A{ 92310618SOmar.Naji@arm.com assert(rank_ref.actTicks.size() == activationLimit); 9249488SN/A 9259488SN/A DPRINTF(DRAM, "Activate at tick %d\n", act_tick); 9269488SN/A 92710207Sandreas.hansson@arm.com // update the open row 92810618SOmar.Naji@arm.com assert(bank_ref.openRow == Bank::NO_ROW); 92910618SOmar.Naji@arm.com bank_ref.openRow = row; 93010207Sandreas.hansson@arm.com 93110207Sandreas.hansson@arm.com // start counting anew, this covers both the case when we 93210207Sandreas.hansson@arm.com // auto-precharged, and when this access is forced to 93310207Sandreas.hansson@arm.com // precharge 93410618SOmar.Naji@arm.com bank_ref.bytesAccessed = 0; 93510618SOmar.Naji@arm.com bank_ref.rowAccesses = 0; 93610207Sandreas.hansson@arm.com 93710618SOmar.Naji@arm.com ++rank_ref.numBanksActive; 93810618SOmar.Naji@arm.com assert(rank_ref.numBanksActive <= banksPerRank); 93910207Sandreas.hansson@arm.com 94010247Sandreas.hansson@arm.com DPRINTF(DRAM, "Activate bank %d, rank %d at tick %lld, now got %d active\n", 94110618SOmar.Naji@arm.com bank_ref.bank, rank_ref.rank, act_tick, 94210618SOmar.Naji@arm.com ranks[rank_ref.rank]->numBanksActive); 94310247Sandreas.hansson@arm.com 94411675Swendy.elsasser@arm.com rank_ref.cmdList.push_back(Command(MemCommand::ACT, bank_ref.bank, 94511675Swendy.elsasser@arm.com act_tick)); 94610432SOmar.Naji@arm.com 94710432SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,ACT,%d,%d\n", divCeil(act_tick, tCK) - 94810618SOmar.Naji@arm.com timeStampOffset, bank_ref.bank, rank_ref.rank); 9499975SN/A 95010211Sandreas.hansson@arm.com // The next access has to respect tRAS for this bank 95110618SOmar.Naji@arm.com bank_ref.preAllowedAt = act_tick + tRAS; 95210211Sandreas.hansson@arm.com 95312706Swendy.elsasser@arm.com // Respect the row-to-column command delay for both read and write cmds 95412706Swendy.elsasser@arm.com bank_ref.rdAllowedAt = std::max(act_tick + tRCD, bank_ref.rdAllowedAt); 95512706Swendy.elsasser@arm.com bank_ref.wrAllowedAt = std::max(act_tick + tRCD, bank_ref.wrAllowedAt); 95610211Sandreas.hansson@arm.com 9579971SN/A // start by enforcing tRRD 95811321Ssteve.reinhardt@amd.com for (int i = 0; i < banksPerRank; i++) { 95910210Sandreas.hansson@arm.com // next activate to any bank in this rank must not happen 96010210Sandreas.hansson@arm.com // before tRRD 96110618SOmar.Naji@arm.com if (bankGroupArch && (bank_ref.bankgr == rank_ref.banks[i].bankgr)) { 96210394Swendy.elsasser@arm.com // bank group architecture requires longer delays between 96310394Swendy.elsasser@arm.com // ACT commands within the same bank group. Use tRRD_L 96410394Swendy.elsasser@arm.com // in this case 96510618SOmar.Naji@arm.com rank_ref.banks[i].actAllowedAt = std::max(act_tick + tRRD_L, 96610618SOmar.Naji@arm.com rank_ref.banks[i].actAllowedAt); 96710394Swendy.elsasser@arm.com } else { 96810394Swendy.elsasser@arm.com // use shorter tRRD value when either 96910394Swendy.elsasser@arm.com // 1) bank group architecture is not supportted 97010394Swendy.elsasser@arm.com // 2) bank is in a different bank group 97110618SOmar.Naji@arm.com rank_ref.banks[i].actAllowedAt = std::max(act_tick + tRRD, 97210618SOmar.Naji@arm.com rank_ref.banks[i].actAllowedAt); 97310394Swendy.elsasser@arm.com } 9749971SN/A } 97510208Sandreas.hansson@arm.com 9769971SN/A // next, we deal with tXAW, if the activation limit is disabled 97710492SOmar.Naji@arm.com // then we directly schedule an activate power event 97810618SOmar.Naji@arm.com if (!rank_ref.actTicks.empty()) { 97910492SOmar.Naji@arm.com // sanity check 98010618SOmar.Naji@arm.com if (rank_ref.actTicks.back() && 98110618SOmar.Naji@arm.com (act_tick - rank_ref.actTicks.back()) < tXAW) { 98210492SOmar.Naji@arm.com panic("Got %d activates in window %d (%llu - %llu) which " 98310492SOmar.Naji@arm.com "is smaller than %llu\n", activationLimit, act_tick - 98410618SOmar.Naji@arm.com rank_ref.actTicks.back(), act_tick, 98510618SOmar.Naji@arm.com rank_ref.actTicks.back(), tXAW); 98610492SOmar.Naji@arm.com } 9879824SN/A 98810492SOmar.Naji@arm.com // shift the times used for the book keeping, the last element 98910492SOmar.Naji@arm.com // (highest index) is the oldest one and hence the lowest value 99010618SOmar.Naji@arm.com rank_ref.actTicks.pop_back(); 9919488SN/A 99210492SOmar.Naji@arm.com // record an new activation (in the future) 99310618SOmar.Naji@arm.com rank_ref.actTicks.push_front(act_tick); 9949488SN/A 99510492SOmar.Naji@arm.com // cannot activate more than X times in time window tXAW, push the 99610492SOmar.Naji@arm.com // next one (the X + 1'st activate) to be tXAW away from the 99710492SOmar.Naji@arm.com // oldest in our window of X 99810618SOmar.Naji@arm.com if (rank_ref.actTicks.back() && 99910618SOmar.Naji@arm.com (act_tick - rank_ref.actTicks.back()) < tXAW) { 100010492SOmar.Naji@arm.com DPRINTF(DRAM, "Enforcing tXAW with X = %d, next activate " 100110492SOmar.Naji@arm.com "no earlier than %llu\n", activationLimit, 100210618SOmar.Naji@arm.com rank_ref.actTicks.back() + tXAW); 100311321Ssteve.reinhardt@amd.com for (int j = 0; j < banksPerRank; j++) 10049488SN/A // next activate must not happen before end of window 100510618SOmar.Naji@arm.com rank_ref.banks[j].actAllowedAt = 100610618SOmar.Naji@arm.com std::max(rank_ref.actTicks.back() + tXAW, 100710618SOmar.Naji@arm.com rank_ref.banks[j].actAllowedAt); 100810492SOmar.Naji@arm.com } 10099488SN/A } 101010208Sandreas.hansson@arm.com 101110208Sandreas.hansson@arm.com // at the point when this activate takes place, make sure we 101210208Sandreas.hansson@arm.com // transition to the active power state 101310618SOmar.Naji@arm.com if (!rank_ref.activateEvent.scheduled()) 101410618SOmar.Naji@arm.com schedule(rank_ref.activateEvent, act_tick); 101510618SOmar.Naji@arm.com else if (rank_ref.activateEvent.when() > act_tick) 101610208Sandreas.hansson@arm.com // move it sooner in time 101710618SOmar.Naji@arm.com reschedule(rank_ref.activateEvent, act_tick); 101810208Sandreas.hansson@arm.com} 101910208Sandreas.hansson@arm.com 102010208Sandreas.hansson@arm.comvoid 102110618SOmar.Naji@arm.comDRAMCtrl::prechargeBank(Rank& rank_ref, Bank& bank, Tick pre_at, bool trace) 102210207Sandreas.hansson@arm.com{ 102310207Sandreas.hansson@arm.com // make sure the bank has an open row 102410207Sandreas.hansson@arm.com assert(bank.openRow != Bank::NO_ROW); 102510207Sandreas.hansson@arm.com 102610207Sandreas.hansson@arm.com // sample the bytes per activate here since we are closing 102710207Sandreas.hansson@arm.com // the page 102810207Sandreas.hansson@arm.com bytesPerActivate.sample(bank.bytesAccessed); 102910207Sandreas.hansson@arm.com 103010207Sandreas.hansson@arm.com bank.openRow = Bank::NO_ROW; 103110207Sandreas.hansson@arm.com 103210214Sandreas.hansson@arm.com // no precharge allowed before this one 103310214Sandreas.hansson@arm.com bank.preAllowedAt = pre_at; 103410214Sandreas.hansson@arm.com 103510211Sandreas.hansson@arm.com Tick pre_done_at = pre_at + tRP; 103610211Sandreas.hansson@arm.com 103710211Sandreas.hansson@arm.com bank.actAllowedAt = std::max(bank.actAllowedAt, pre_done_at); 103810207Sandreas.hansson@arm.com 103910618SOmar.Naji@arm.com assert(rank_ref.numBanksActive != 0); 104010618SOmar.Naji@arm.com --rank_ref.numBanksActive; 104110207Sandreas.hansson@arm.com 104210247Sandreas.hansson@arm.com DPRINTF(DRAM, "Precharging bank %d, rank %d at tick %lld, now got " 104310618SOmar.Naji@arm.com "%d active\n", bank.bank, rank_ref.rank, pre_at, 104410618SOmar.Naji@arm.com rank_ref.numBanksActive); 104510247Sandreas.hansson@arm.com 104610432SOmar.Naji@arm.com if (trace) { 104710207Sandreas.hansson@arm.com 104811675Swendy.elsasser@arm.com rank_ref.cmdList.push_back(Command(MemCommand::PRE, bank.bank, 104911675Swendy.elsasser@arm.com pre_at)); 105010432SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,PRE,%d,%d\n", divCeil(pre_at, tCK) - 105110618SOmar.Naji@arm.com timeStampOffset, bank.bank, rank_ref.rank); 105210432SOmar.Naji@arm.com } 105310208Sandreas.hansson@arm.com // if we look at the current number of active banks we might be 105410208Sandreas.hansson@arm.com // tempted to think the DRAM is now idle, however this can be 105510208Sandreas.hansson@arm.com // undone by an activate that is scheduled to happen before we 105610208Sandreas.hansson@arm.com // would have reached the idle state, so schedule an event and 105710208Sandreas.hansson@arm.com // rather check once we actually make it to the point in time when 105810208Sandreas.hansson@arm.com // the (last) precharge takes place 105911678Swendy.elsasser@arm.com if (!rank_ref.prechargeEvent.scheduled()) { 106010618SOmar.Naji@arm.com schedule(rank_ref.prechargeEvent, pre_done_at); 106111678Swendy.elsasser@arm.com // New event, increment count 106211678Swendy.elsasser@arm.com ++rank_ref.outstandingEvents; 106311678Swendy.elsasser@arm.com } else if (rank_ref.prechargeEvent.when() < pre_done_at) { 106410618SOmar.Naji@arm.com reschedule(rank_ref.prechargeEvent, pre_done_at); 106511678Swendy.elsasser@arm.com } 106610207Sandreas.hansson@arm.com} 106710207Sandreas.hansson@arm.com 106810207Sandreas.hansson@arm.comvoid 106910146Sandreas.hansson@arm.comDRAMCtrl::doDRAMAccess(DRAMPacket* dram_pkt) 10709243SN/A{ 10719243SN/A DPRINTF(DRAM, "Timing access to addr %lld, rank/bank/row %d %d %d\n", 10729243SN/A dram_pkt->addr, dram_pkt->rank, dram_pkt->bank, dram_pkt->row); 10739243SN/A 107410618SOmar.Naji@arm.com // get the rank 107510618SOmar.Naji@arm.com Rank& rank = dram_pkt->rankRef; 107610618SOmar.Naji@arm.com 107711678Swendy.elsasser@arm.com // are we in or transitioning to a low-power state and have not scheduled 107811678Swendy.elsasser@arm.com // a power-up event? 107911678Swendy.elsasser@arm.com // if so, wake up from power down to issue RD/WR burst 108011678Swendy.elsasser@arm.com if (rank.inLowPowerState) { 108111678Swendy.elsasser@arm.com assert(rank.pwrState != PWR_SREF); 108211678Swendy.elsasser@arm.com rank.scheduleWakeUpEvent(tXP); 108311678Swendy.elsasser@arm.com } 108411678Swendy.elsasser@arm.com 108510211Sandreas.hansson@arm.com // get the bank 10869967SN/A Bank& bank = dram_pkt->bankRef; 10879243SN/A 108810211Sandreas.hansson@arm.com // for the state we need to track if it is a row hit or not 108910211Sandreas.hansson@arm.com bool row_hit = true; 109010211Sandreas.hansson@arm.com 109110211Sandreas.hansson@arm.com // Determine the access latency and update the bank state 109210211Sandreas.hansson@arm.com if (bank.openRow == dram_pkt->row) { 109310211Sandreas.hansson@arm.com // nothing to do 109410209Sandreas.hansson@arm.com } else { 109510211Sandreas.hansson@arm.com row_hit = false; 109610211Sandreas.hansson@arm.com 109710209Sandreas.hansson@arm.com // If there is a page open, precharge it. 109810209Sandreas.hansson@arm.com if (bank.openRow != Bank::NO_ROW) { 109910618SOmar.Naji@arm.com prechargeBank(rank, bank, std::max(bank.preAllowedAt, curTick())); 11009488SN/A } 11019973SN/A 110210211Sandreas.hansson@arm.com // next we need to account for the delay in activating the 110310211Sandreas.hansson@arm.com // page 110410211Sandreas.hansson@arm.com Tick act_tick = std::max(bank.actAllowedAt, curTick()); 11059973SN/A 110610210Sandreas.hansson@arm.com // Record the activation and deal with all the global timing 110710210Sandreas.hansson@arm.com // constraints caused be a new activation (tRRD and tXAW) 110810618SOmar.Naji@arm.com activateBank(rank, bank, act_tick, dram_pkt->row); 110910209Sandreas.hansson@arm.com } 111010209Sandreas.hansson@arm.com 111112706Swendy.elsasser@arm.com // respect any constraints on the command (e.g. tRCD or tCCD) 111212706Swendy.elsasser@arm.com const Tick col_allowed_at = dram_pkt->isRead ? 111312706Swendy.elsasser@arm.com bank.rdAllowedAt : bank.wrAllowedAt; 111412706Swendy.elsasser@arm.com 111510211Sandreas.hansson@arm.com // we need to wait until the bus is available before we can issue 111612706Swendy.elsasser@arm.com // the command; need minimum of tBURST between commands 111712706Swendy.elsasser@arm.com Tick cmd_at = std::max({col_allowed_at, nextBurstAt, curTick()}); 111810211Sandreas.hansson@arm.com 111910211Sandreas.hansson@arm.com // update the packet ready time 112010211Sandreas.hansson@arm.com dram_pkt->readyTime = cmd_at + tCL + tBURST; 112110211Sandreas.hansson@arm.com 112210394Swendy.elsasser@arm.com // update the time for the next read/write burst for each 112312706Swendy.elsasser@arm.com // bank (add a max with tCCD/tCCD_L/tCCD_L_WR here) 112412706Swendy.elsasser@arm.com Tick dly_to_rd_cmd; 112512706Swendy.elsasser@arm.com Tick dly_to_wr_cmd; 112611321Ssteve.reinhardt@amd.com for (int j = 0; j < ranksPerChannel; j++) { 112711321Ssteve.reinhardt@amd.com for (int i = 0; i < banksPerRank; i++) { 112810394Swendy.elsasser@arm.com // next burst to same bank group in this rank must not happen 112910394Swendy.elsasser@arm.com // before tCCD_L. Different bank group timing requirement is 113010394Swendy.elsasser@arm.com // tBURST; Add tCS for different ranks 113110394Swendy.elsasser@arm.com if (dram_pkt->rank == j) { 113210618SOmar.Naji@arm.com if (bankGroupArch && 113310618SOmar.Naji@arm.com (bank.bankgr == ranks[j]->banks[i].bankgr)) { 113410394Swendy.elsasser@arm.com // bank group architecture requires longer delays between 113510394Swendy.elsasser@arm.com // RD/WR burst commands to the same bank group. 113612706Swendy.elsasser@arm.com // tCCD_L is default requirement for same BG timing 113712706Swendy.elsasser@arm.com // tCCD_L_WR is required for write-to-write 113812706Swendy.elsasser@arm.com // Need to also take bus turnaround delays into account 113912706Swendy.elsasser@arm.com dly_to_rd_cmd = dram_pkt->isRead ? 114012706Swendy.elsasser@arm.com tCCD_L : std::max(tCCD_L, wrToRdDly); 114112706Swendy.elsasser@arm.com dly_to_wr_cmd = dram_pkt->isRead ? 114212706Swendy.elsasser@arm.com std::max(tCCD_L, rdToWrDly) : tCCD_L_WR; 114310394Swendy.elsasser@arm.com } else { 114412706Swendy.elsasser@arm.com // tBURST is default requirement for diff BG timing 114512706Swendy.elsasser@arm.com // Need to also take bus turnaround delays into account 114612706Swendy.elsasser@arm.com dly_to_rd_cmd = dram_pkt->isRead ? tBURST : wrToRdDly; 114712706Swendy.elsasser@arm.com dly_to_wr_cmd = dram_pkt->isRead ? rdToWrDly : tBURST; 114810394Swendy.elsasser@arm.com } 114910394Swendy.elsasser@arm.com } else { 115012706Swendy.elsasser@arm.com // different rank is by default in a different bank group and 115112706Swendy.elsasser@arm.com // doesn't require longer tCCD or additional RTW, WTR delays 115212706Swendy.elsasser@arm.com // Need to account for rank-to-rank switching with tCS 115312706Swendy.elsasser@arm.com dly_to_wr_cmd = rankToRankDly; 115412706Swendy.elsasser@arm.com dly_to_rd_cmd = rankToRankDly; 115510394Swendy.elsasser@arm.com } 115612706Swendy.elsasser@arm.com ranks[j]->banks[i].rdAllowedAt = std::max(cmd_at + dly_to_rd_cmd, 115712706Swendy.elsasser@arm.com ranks[j]->banks[i].rdAllowedAt); 115812706Swendy.elsasser@arm.com ranks[j]->banks[i].wrAllowedAt = std::max(cmd_at + dly_to_wr_cmd, 115912706Swendy.elsasser@arm.com ranks[j]->banks[i].wrAllowedAt); 116010394Swendy.elsasser@arm.com } 116110394Swendy.elsasser@arm.com } 116210211Sandreas.hansson@arm.com 116310393Swendy.elsasser@arm.com // Save rank of current access 116410393Swendy.elsasser@arm.com activeRank = dram_pkt->rank; 116510393Swendy.elsasser@arm.com 116610212Sandreas.hansson@arm.com // If this is a write, we also need to respect the write recovery 116710212Sandreas.hansson@arm.com // time before a precharge, in the case of a read, respect the 116810212Sandreas.hansson@arm.com // read to precharge constraint 116910212Sandreas.hansson@arm.com bank.preAllowedAt = std::max(bank.preAllowedAt, 117010212Sandreas.hansson@arm.com dram_pkt->isRead ? cmd_at + tRTP : 117110212Sandreas.hansson@arm.com dram_pkt->readyTime + tWR); 117210210Sandreas.hansson@arm.com 117310209Sandreas.hansson@arm.com // increment the bytes accessed and the accesses per row 117410209Sandreas.hansson@arm.com bank.bytesAccessed += burstSize; 117510209Sandreas.hansson@arm.com ++bank.rowAccesses; 117610209Sandreas.hansson@arm.com 117710209Sandreas.hansson@arm.com // if we reached the max, then issue with an auto-precharge 117810209Sandreas.hansson@arm.com bool auto_precharge = pageMgmt == Enums::close || 117910209Sandreas.hansson@arm.com bank.rowAccesses == maxAccessesPerRow; 118010209Sandreas.hansson@arm.com 118110209Sandreas.hansson@arm.com // if we did not hit the limit, we might still want to 118210209Sandreas.hansson@arm.com // auto-precharge 118310209Sandreas.hansson@arm.com if (!auto_precharge && 118410209Sandreas.hansson@arm.com (pageMgmt == Enums::open_adaptive || 118510209Sandreas.hansson@arm.com pageMgmt == Enums::close_adaptive)) { 118610209Sandreas.hansson@arm.com // a twist on the open and close page policies: 118710209Sandreas.hansson@arm.com // 1) open_adaptive page policy does not blindly keep the 118810209Sandreas.hansson@arm.com // page open, but close it if there are no row hits, and there 118910209Sandreas.hansson@arm.com // are bank conflicts in the queue 119010209Sandreas.hansson@arm.com // 2) close_adaptive page policy does not blindly close the 119110209Sandreas.hansson@arm.com // page, but closes it only if there are no row hits in the queue. 119210209Sandreas.hansson@arm.com // In this case, only force an auto precharge when there 119310209Sandreas.hansson@arm.com // are no same page hits in the queue 119410209Sandreas.hansson@arm.com bool got_more_hits = false; 119510209Sandreas.hansson@arm.com bool got_bank_conflict = false; 119610209Sandreas.hansson@arm.com 119710209Sandreas.hansson@arm.com // either look at the read queue or write queue 119810209Sandreas.hansson@arm.com const deque<DRAMPacket*>& queue = dram_pkt->isRead ? readQueue : 119910209Sandreas.hansson@arm.com writeQueue; 120010209Sandreas.hansson@arm.com auto p = queue.begin(); 120110209Sandreas.hansson@arm.com // make sure we are not considering the packet that we are 120210209Sandreas.hansson@arm.com // currently dealing with (which is the head of the queue) 120310209Sandreas.hansson@arm.com ++p; 120410209Sandreas.hansson@arm.com 120510809Srb639@drexel.edu // keep on looking until we find a hit or reach the end of the queue 120610809Srb639@drexel.edu // 1) if a hit is found, then both open and close adaptive policies keep 120710809Srb639@drexel.edu // the page open 120810809Srb639@drexel.edu // 2) if no hit is found, got_bank_conflict is set to true if a bank 120910809Srb639@drexel.edu // conflict request is waiting in the queue 121010809Srb639@drexel.edu while (!got_more_hits && p != queue.end()) { 121110209Sandreas.hansson@arm.com bool same_rank_bank = (dram_pkt->rank == (*p)->rank) && 121210209Sandreas.hansson@arm.com (dram_pkt->bank == (*p)->bank); 121310209Sandreas.hansson@arm.com bool same_row = dram_pkt->row == (*p)->row; 121410209Sandreas.hansson@arm.com got_more_hits |= same_rank_bank && same_row; 121510209Sandreas.hansson@arm.com got_bank_conflict |= same_rank_bank && !same_row; 12169973SN/A ++p; 121710141SN/A } 121810141SN/A 121910209Sandreas.hansson@arm.com // auto pre-charge when either 122010209Sandreas.hansson@arm.com // 1) open_adaptive policy, we have not got any more hits, and 122110209Sandreas.hansson@arm.com // have a bank conflict 122210209Sandreas.hansson@arm.com // 2) close_adaptive policy and we have not got any more hits 122310209Sandreas.hansson@arm.com auto_precharge = !got_more_hits && 122410209Sandreas.hansson@arm.com (got_bank_conflict || pageMgmt == Enums::close_adaptive); 122510209Sandreas.hansson@arm.com } 122610142SN/A 122710247Sandreas.hansson@arm.com // DRAMPower trace command to be written 122810247Sandreas.hansson@arm.com std::string mem_cmd = dram_pkt->isRead ? "RD" : "WR"; 122910247Sandreas.hansson@arm.com 123010432SOmar.Naji@arm.com // MemCommand required for DRAMPower library 123110432SOmar.Naji@arm.com MemCommand::cmds command = (mem_cmd == "RD") ? MemCommand::RD : 123210432SOmar.Naji@arm.com MemCommand::WR; 123310432SOmar.Naji@arm.com 123412706Swendy.elsasser@arm.com // Update bus state to reflect when previous command was issued 123512706Swendy.elsasser@arm.com nextBurstAt = cmd_at + tBURST; 123612706Swendy.elsasser@arm.com 123712706Swendy.elsasser@arm.com DPRINTF(DRAM, "Access to %lld, ready at %lld next burst at %lld.\n", 123812706Swendy.elsasser@arm.com dram_pkt->addr, dram_pkt->readyTime, nextBurstAt); 123911675Swendy.elsasser@arm.com 124011675Swendy.elsasser@arm.com dram_pkt->rankRef.cmdList.push_back(Command(command, dram_pkt->bank, 124111675Swendy.elsasser@arm.com cmd_at)); 124211675Swendy.elsasser@arm.com 124311675Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,%s,%d,%d\n", divCeil(cmd_at, tCK) - 124411675Swendy.elsasser@arm.com timeStampOffset, mem_cmd, dram_pkt->bank, dram_pkt->rank); 124511675Swendy.elsasser@arm.com 124610209Sandreas.hansson@arm.com // if this access should use auto-precharge, then we are 124711675Swendy.elsasser@arm.com // closing the row after the read/write burst 124810209Sandreas.hansson@arm.com if (auto_precharge) { 124910432SOmar.Naji@arm.com // if auto-precharge push a PRE command at the correct tick to the 125010432SOmar.Naji@arm.com // list used by DRAMPower library to calculate power 125110618SOmar.Naji@arm.com prechargeBank(rank, bank, std::max(curTick(), bank.preAllowedAt)); 12529973SN/A 125310209Sandreas.hansson@arm.com DPRINTF(DRAM, "Auto-precharged bank: %d\n", dram_pkt->bankId); 125410209Sandreas.hansson@arm.com } 12559963SN/A 125610206Sandreas.hansson@arm.com // Update the minimum timing between the requests, this is a 125710206Sandreas.hansson@arm.com // conservative estimate of when we have to schedule the next 125810206Sandreas.hansson@arm.com // request to not introduce any unecessary bubbles. In most cases 125910206Sandreas.hansson@arm.com // we will wake up sooner than we have to. 126012706Swendy.elsasser@arm.com nextReqTime = nextBurstAt - (tRP + tRCD); 12619972SN/A 126210206Sandreas.hansson@arm.com // Update the stats and schedule the next request 12639977SN/A if (dram_pkt->isRead) { 126410147Sandreas.hansson@arm.com ++readsThisTime; 126510211Sandreas.hansson@arm.com if (row_hit) 12669977SN/A readRowHits++; 12679977SN/A bytesReadDRAM += burstSize; 12689977SN/A perBankRdBursts[dram_pkt->bankId]++; 126910206Sandreas.hansson@arm.com 127010206Sandreas.hansson@arm.com // Update latency stats 127110206Sandreas.hansson@arm.com totMemAccLat += dram_pkt->readyTime - dram_pkt->entryTime; 127210206Sandreas.hansson@arm.com totBusLat += tBURST; 127310211Sandreas.hansson@arm.com totQLat += cmd_at - dram_pkt->entryTime; 12749977SN/A } else { 127510147Sandreas.hansson@arm.com ++writesThisTime; 127610211Sandreas.hansson@arm.com if (row_hit) 12779977SN/A writeRowHits++; 12789977SN/A bytesWritten += burstSize; 12799977SN/A perBankWrBursts[dram_pkt->bankId]++; 12809243SN/A } 12819243SN/A} 12829243SN/A 12839243SN/Avoid 128410206Sandreas.hansson@arm.comDRAMCtrl::processNextReqEvent() 12859243SN/A{ 128610618SOmar.Naji@arm.com int busyRanks = 0; 128710618SOmar.Naji@arm.com for (auto r : ranks) { 128812266Sradhika.jagtap@arm.com if (!r->inRefIdleState()) { 128911678Swendy.elsasser@arm.com if (r->pwrState != PWR_SREF) { 129011678Swendy.elsasser@arm.com // rank is busy refreshing 129111678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Rank %d is not available\n", r->rank); 129211678Swendy.elsasser@arm.com busyRanks++; 129311678Swendy.elsasser@arm.com 129411678Swendy.elsasser@arm.com // let the rank know that if it was waiting to drain, it 129511678Swendy.elsasser@arm.com // is now done and ready to proceed 129611678Swendy.elsasser@arm.com r->checkDrainDone(); 129711678Swendy.elsasser@arm.com } 129811678Swendy.elsasser@arm.com 129911678Swendy.elsasser@arm.com // check if we were in self-refresh and haven't started 130011678Swendy.elsasser@arm.com // to transition out 130111678Swendy.elsasser@arm.com if ((r->pwrState == PWR_SREF) && r->inLowPowerState) { 130211678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Rank %d is in self-refresh\n", r->rank); 130311678Swendy.elsasser@arm.com // if we have commands queued to this rank and we don't have 130411678Swendy.elsasser@arm.com // a minimum number of active commands enqueued, 130511678Swendy.elsasser@arm.com // exit self-refresh 130611678Swendy.elsasser@arm.com if (r->forceSelfRefreshExit()) { 130711678Swendy.elsasser@arm.com DPRINTF(DRAMState, "rank %d was in self refresh and" 130811678Swendy.elsasser@arm.com " should wake up\n", r->rank); 130911678Swendy.elsasser@arm.com //wake up from self-refresh 131011678Swendy.elsasser@arm.com r->scheduleWakeUpEvent(tXS); 131111678Swendy.elsasser@arm.com // things are brought back into action once a refresh is 131211678Swendy.elsasser@arm.com // performed after self-refresh 131311678Swendy.elsasser@arm.com // continue with selection for other ranks 131411678Swendy.elsasser@arm.com } 131511678Swendy.elsasser@arm.com } 131610618SOmar.Naji@arm.com } 131710618SOmar.Naji@arm.com } 131810618SOmar.Naji@arm.com 131910618SOmar.Naji@arm.com if (busyRanks == ranksPerChannel) { 132010618SOmar.Naji@arm.com // if all ranks are refreshing wait for them to finish 132110618SOmar.Naji@arm.com // and stall this state machine without taking any further 132210618SOmar.Naji@arm.com // action, and do not schedule a new nextReqEvent 132310618SOmar.Naji@arm.com return; 132410618SOmar.Naji@arm.com } 132510618SOmar.Naji@arm.com 132611678Swendy.elsasser@arm.com // pre-emptively set to false. Overwrite if in transitioning to 132711678Swendy.elsasser@arm.com // a new state 132810393Swendy.elsasser@arm.com bool switched_cmd_type = false; 132911678Swendy.elsasser@arm.com if (busState != busStateNext) { 133011678Swendy.elsasser@arm.com if (busState == READ) { 133111678Swendy.elsasser@arm.com DPRINTF(DRAM, "Switching to writes after %d reads with %d reads " 133211678Swendy.elsasser@arm.com "waiting\n", readsThisTime, readQueue.size()); 133311678Swendy.elsasser@arm.com 133411678Swendy.elsasser@arm.com // sample and reset the read-related stats as we are now 133511678Swendy.elsasser@arm.com // transitioning to writes, and all reads are done 133611678Swendy.elsasser@arm.com rdPerTurnAround.sample(readsThisTime); 133711678Swendy.elsasser@arm.com readsThisTime = 0; 133811678Swendy.elsasser@arm.com 133911678Swendy.elsasser@arm.com // now proceed to do the actual writes 134011678Swendy.elsasser@arm.com switched_cmd_type = true; 134111678Swendy.elsasser@arm.com } else { 134211678Swendy.elsasser@arm.com DPRINTF(DRAM, "Switching to reads after %d writes with %d writes " 134311678Swendy.elsasser@arm.com "waiting\n", writesThisTime, writeQueue.size()); 134411678Swendy.elsasser@arm.com 134511678Swendy.elsasser@arm.com wrPerTurnAround.sample(writesThisTime); 134611678Swendy.elsasser@arm.com writesThisTime = 0; 134711678Swendy.elsasser@arm.com 134811678Swendy.elsasser@arm.com switched_cmd_type = true; 134911678Swendy.elsasser@arm.com } 135011678Swendy.elsasser@arm.com // update busState to match next state until next transition 135111678Swendy.elsasser@arm.com busState = busStateNext; 135210206Sandreas.hansson@arm.com } 135310206Sandreas.hansson@arm.com 135410206Sandreas.hansson@arm.com // when we get here it is either a read or a write 135510206Sandreas.hansson@arm.com if (busState == READ) { 135610206Sandreas.hansson@arm.com 135710206Sandreas.hansson@arm.com // track if we should switch or not 135810206Sandreas.hansson@arm.com bool switch_to_writes = false; 135910206Sandreas.hansson@arm.com 136010206Sandreas.hansson@arm.com if (readQueue.empty()) { 136110206Sandreas.hansson@arm.com // In the case there is no read request to go next, 136210206Sandreas.hansson@arm.com // trigger writes if we have passed the low threshold (or 136310206Sandreas.hansson@arm.com // if we are draining) 136410206Sandreas.hansson@arm.com if (!writeQueue.empty() && 136510913Sandreas.sandberg@arm.com (drainState() == DrainState::Draining || 136610913Sandreas.sandberg@arm.com writeQueue.size() > writeLowThreshold)) { 136710206Sandreas.hansson@arm.com 136810206Sandreas.hansson@arm.com switch_to_writes = true; 136910206Sandreas.hansson@arm.com } else { 137010206Sandreas.hansson@arm.com // check if we are drained 137111676Swendy.elsasser@arm.com // not done draining until in PWR_IDLE state 137211676Swendy.elsasser@arm.com // ensuring all banks are closed and 137311676Swendy.elsasser@arm.com // have exited low power states 137410913Sandreas.sandberg@arm.com if (drainState() == DrainState::Draining && 137511676Swendy.elsasser@arm.com respQueue.empty() && allRanksDrained()) { 137610913Sandreas.sandberg@arm.com 137710509SAli.Saidi@ARM.com DPRINTF(Drain, "DRAM controller done draining\n"); 137810913Sandreas.sandberg@arm.com signalDrainDone(); 137910206Sandreas.hansson@arm.com } 138010206Sandreas.hansson@arm.com 138110206Sandreas.hansson@arm.com // nothing to do, not even any point in scheduling an 138210206Sandreas.hansson@arm.com // event for the next request 138310206Sandreas.hansson@arm.com return; 138410206Sandreas.hansson@arm.com } 138510206Sandreas.hansson@arm.com } else { 138610618SOmar.Naji@arm.com // bool to check if there is a read to a free rank 138710618SOmar.Naji@arm.com bool found_read = false; 138810618SOmar.Naji@arm.com 138910206Sandreas.hansson@arm.com // Figure out which read request goes next, and move it to the 139010206Sandreas.hansson@arm.com // front of the read queue 139110890Swendy.elsasser@arm.com // If we are changing command type, incorporate the minimum 139210890Swendy.elsasser@arm.com // bus turnaround delay which will be tCS (different rank) case 139312706Swendy.elsasser@arm.com found_read = chooseNext(readQueue, switched_cmd_type ? tCS : 0); 139410618SOmar.Naji@arm.com 139510618SOmar.Naji@arm.com // if no read to an available rank is found then return 139610618SOmar.Naji@arm.com // at this point. There could be writes to the available ranks 139710618SOmar.Naji@arm.com // which are above the required threshold. However, to 139810618SOmar.Naji@arm.com // avoid adding more complexity to the code, return and wait 139910618SOmar.Naji@arm.com // for a refresh event to kick things into action again. 140010618SOmar.Naji@arm.com if (!found_read) 140110618SOmar.Naji@arm.com return; 140210206Sandreas.hansson@arm.com 140310215Sandreas.hansson@arm.com DRAMPacket* dram_pkt = readQueue.front(); 140412266Sradhika.jagtap@arm.com assert(dram_pkt->rankRef.inRefIdleState()); 140511678Swendy.elsasser@arm.com 140610215Sandreas.hansson@arm.com doDRAMAccess(dram_pkt); 140710206Sandreas.hansson@arm.com 140810206Sandreas.hansson@arm.com // At this point we're done dealing with the request 140910215Sandreas.hansson@arm.com readQueue.pop_front(); 141010215Sandreas.hansson@arm.com 141111678Swendy.elsasser@arm.com // Every respQueue which will generate an event, increment count 141211678Swendy.elsasser@arm.com ++dram_pkt->rankRef.outstandingEvents; 141311678Swendy.elsasser@arm.com 141410215Sandreas.hansson@arm.com // sanity check 141510215Sandreas.hansson@arm.com assert(dram_pkt->size <= burstSize); 141610215Sandreas.hansson@arm.com assert(dram_pkt->readyTime >= curTick()); 141710215Sandreas.hansson@arm.com 141810215Sandreas.hansson@arm.com // Insert into response queue. It will be sent back to the 141910215Sandreas.hansson@arm.com // requestor at its readyTime 142010215Sandreas.hansson@arm.com if (respQueue.empty()) { 142110215Sandreas.hansson@arm.com assert(!respondEvent.scheduled()); 142210215Sandreas.hansson@arm.com schedule(respondEvent, dram_pkt->readyTime); 142310215Sandreas.hansson@arm.com } else { 142410215Sandreas.hansson@arm.com assert(respQueue.back()->readyTime <= dram_pkt->readyTime); 142510215Sandreas.hansson@arm.com assert(respondEvent.scheduled()); 142610215Sandreas.hansson@arm.com } 142710215Sandreas.hansson@arm.com 142810215Sandreas.hansson@arm.com respQueue.push_back(dram_pkt); 142910206Sandreas.hansson@arm.com 143010206Sandreas.hansson@arm.com // we have so many writes that we have to transition 143110206Sandreas.hansson@arm.com if (writeQueue.size() > writeHighThreshold) { 143210206Sandreas.hansson@arm.com switch_to_writes = true; 143310206Sandreas.hansson@arm.com } 143410206Sandreas.hansson@arm.com } 143510206Sandreas.hansson@arm.com 143610206Sandreas.hansson@arm.com // switching to writes, either because the read queue is empty 143710206Sandreas.hansson@arm.com // and the writes have passed the low threshold (or we are 143810206Sandreas.hansson@arm.com // draining), or because the writes hit the hight threshold 143910206Sandreas.hansson@arm.com if (switch_to_writes) { 144010206Sandreas.hansson@arm.com // transition to writing 144111678Swendy.elsasser@arm.com busStateNext = WRITE; 144210206Sandreas.hansson@arm.com } 14439352SN/A } else { 144410618SOmar.Naji@arm.com // bool to check if write to free rank is found 144510618SOmar.Naji@arm.com bool found_write = false; 144610618SOmar.Naji@arm.com 144710890Swendy.elsasser@arm.com // If we are changing command type, incorporate the minimum 144810890Swendy.elsasser@arm.com // bus turnaround delay 144910890Swendy.elsasser@arm.com found_write = chooseNext(writeQueue, 145010890Swendy.elsasser@arm.com switched_cmd_type ? std::min(tRTW, tCS) : 0); 145110618SOmar.Naji@arm.com 145212266Sradhika.jagtap@arm.com // if there are no writes to a rank that is available to service 145312266Sradhika.jagtap@arm.com // requests (i.e. rank is in refresh idle state) are found then 145412266Sradhika.jagtap@arm.com // return. There could be reads to the available ranks. However, to 145512266Sradhika.jagtap@arm.com // avoid adding more complexity to the code, return at this point and 145612266Sradhika.jagtap@arm.com // wait for a refresh event to kick things into action again. 145710618SOmar.Naji@arm.com if (!found_write) 145810618SOmar.Naji@arm.com return; 145910618SOmar.Naji@arm.com 146010206Sandreas.hansson@arm.com DRAMPacket* dram_pkt = writeQueue.front(); 146112266Sradhika.jagtap@arm.com assert(dram_pkt->rankRef.inRefIdleState()); 146210206Sandreas.hansson@arm.com // sanity check 146310206Sandreas.hansson@arm.com assert(dram_pkt->size <= burstSize); 146410393Swendy.elsasser@arm.com 146510206Sandreas.hansson@arm.com doDRAMAccess(dram_pkt); 146610206Sandreas.hansson@arm.com 146710206Sandreas.hansson@arm.com writeQueue.pop_front(); 146811678Swendy.elsasser@arm.com 146911678Swendy.elsasser@arm.com // removed write from queue, decrement count 147011678Swendy.elsasser@arm.com --dram_pkt->rankRef.writeEntries; 147111678Swendy.elsasser@arm.com 147211678Swendy.elsasser@arm.com // Schedule write done event to decrement event count 147311678Swendy.elsasser@arm.com // after the readyTime has been reached 147411678Swendy.elsasser@arm.com // Only schedule latest write event to minimize events 147511678Swendy.elsasser@arm.com // required; only need to ensure that final event scheduled covers 147611678Swendy.elsasser@arm.com // the time that writes are outstanding and bus is active 147711678Swendy.elsasser@arm.com // to holdoff power-down entry events 147811678Swendy.elsasser@arm.com if (!dram_pkt->rankRef.writeDoneEvent.scheduled()) { 147911678Swendy.elsasser@arm.com schedule(dram_pkt->rankRef.writeDoneEvent, dram_pkt->readyTime); 148011678Swendy.elsasser@arm.com // New event, increment count 148111678Swendy.elsasser@arm.com ++dram_pkt->rankRef.outstandingEvents; 148211678Swendy.elsasser@arm.com 148311678Swendy.elsasser@arm.com } else if (dram_pkt->rankRef.writeDoneEvent.when() < 148411678Swendy.elsasser@arm.com dram_pkt-> readyTime) { 148511678Swendy.elsasser@arm.com reschedule(dram_pkt->rankRef.writeDoneEvent, dram_pkt->readyTime); 148611678Swendy.elsasser@arm.com } 148711678Swendy.elsasser@arm.com 148810889Sandreas.hansson@arm.com isInWriteQueue.erase(burstAlign(dram_pkt->addr)); 148910206Sandreas.hansson@arm.com delete dram_pkt; 149010206Sandreas.hansson@arm.com 149110206Sandreas.hansson@arm.com // If we emptied the write queue, or got sufficiently below the 149210206Sandreas.hansson@arm.com // threshold (using the minWritesPerSwitch as the hysteresis) and 149310206Sandreas.hansson@arm.com // are not draining, or we have reads waiting and have done enough 149410206Sandreas.hansson@arm.com // writes, then switch to reads. 149510206Sandreas.hansson@arm.com if (writeQueue.empty() || 149610206Sandreas.hansson@arm.com (writeQueue.size() + minWritesPerSwitch < writeLowThreshold && 149710913Sandreas.sandberg@arm.com drainState() != DrainState::Draining) || 149810206Sandreas.hansson@arm.com (!readQueue.empty() && writesThisTime >= minWritesPerSwitch)) { 149910206Sandreas.hansson@arm.com // turn the bus back around for reads again 150011678Swendy.elsasser@arm.com busStateNext = READ; 150110206Sandreas.hansson@arm.com 150210206Sandreas.hansson@arm.com // note that the we switch back to reads also in the idle 150310206Sandreas.hansson@arm.com // case, which eventually will check for any draining and 150410206Sandreas.hansson@arm.com // also pause any further scheduling if there is really 150510206Sandreas.hansson@arm.com // nothing to do 150610206Sandreas.hansson@arm.com } 150710206Sandreas.hansson@arm.com } 150810618SOmar.Naji@arm.com // It is possible that a refresh to another rank kicks things back into 150910618SOmar.Naji@arm.com // action before reaching this point. 151010618SOmar.Naji@arm.com if (!nextReqEvent.scheduled()) 151110618SOmar.Naji@arm.com schedule(nextReqEvent, std::max(nextReqTime, curTick())); 151210206Sandreas.hansson@arm.com 151310206Sandreas.hansson@arm.com // If there is space available and we have writes waiting then let 151410206Sandreas.hansson@arm.com // them retry. This is done here to ensure that the retry does not 151510206Sandreas.hansson@arm.com // cause a nextReqEvent to be scheduled before we do so as part of 151610206Sandreas.hansson@arm.com // the next request processing 151710206Sandreas.hansson@arm.com if (retryWrReq && writeQueue.size() < writeBufferSize) { 151810206Sandreas.hansson@arm.com retryWrReq = false; 151910713Sandreas.hansson@arm.com port.sendRetryReq(); 15209352SN/A } 15219243SN/A} 15229243SN/A 152312706Swendy.elsasser@arm.compair<vector<uint32_t>, bool> 152410393Swendy.elsasser@arm.comDRAMCtrl::minBankPrep(const deque<DRAMPacket*>& queue, 152510890Swendy.elsasser@arm.com Tick min_col_at) const 15269967SN/A{ 152710211Sandreas.hansson@arm.com Tick min_act_at = MaxTick; 152812706Swendy.elsasser@arm.com vector<uint32_t> bank_mask(ranksPerChannel, 0); 15299967SN/A 153010890Swendy.elsasser@arm.com // latest Tick for which ACT can occur without incurring additoinal 153110890Swendy.elsasser@arm.com // delay on the data bus 153210890Swendy.elsasser@arm.com const Tick hidden_act_max = std::max(min_col_at - tRCD, curTick()); 153310393Swendy.elsasser@arm.com 153410890Swendy.elsasser@arm.com // Flag condition when burst can issue back-to-back with previous burst 153510890Swendy.elsasser@arm.com bool found_seamless_bank = false; 153610890Swendy.elsasser@arm.com 153710890Swendy.elsasser@arm.com // Flag condition when bank can be opened without incurring additional 153810890Swendy.elsasser@arm.com // delay on the data bus 153910890Swendy.elsasser@arm.com bool hidden_bank_prep = false; 154010393Swendy.elsasser@arm.com 154110393Swendy.elsasser@arm.com // determine if we have queued transactions targetting the 15429967SN/A // bank in question 15439967SN/A vector<bool> got_waiting(ranksPerChannel * banksPerRank, false); 154410618SOmar.Naji@arm.com for (const auto& p : queue) { 154512266Sradhika.jagtap@arm.com if (p->rankRef.inRefIdleState()) 154610618SOmar.Naji@arm.com got_waiting[p->bankId] = true; 15479967SN/A } 15489967SN/A 154910890Swendy.elsasser@arm.com // Find command with optimal bank timing 155010890Swendy.elsasser@arm.com // Will prioritize commands that can issue seamlessly. 15519967SN/A for (int i = 0; i < ranksPerChannel; i++) { 15529967SN/A for (int j = 0; j < banksPerRank; j++) { 155310618SOmar.Naji@arm.com uint16_t bank_id = i * banksPerRank + j; 155410211Sandreas.hansson@arm.com 15559967SN/A // if we have waiting requests for the bank, and it is 15569967SN/A // amongst the first available, update the mask 155710211Sandreas.hansson@arm.com if (got_waiting[bank_id]) { 155810618SOmar.Naji@arm.com // make sure this rank is not currently refreshing. 155912266Sradhika.jagtap@arm.com assert(ranks[i]->inRefIdleState()); 156010211Sandreas.hansson@arm.com // simplistic approximation of when the bank can issue 156110211Sandreas.hansson@arm.com // an activate, ignoring any rank-to-rank switching 156210393Swendy.elsasser@arm.com // cost in this calculation 156310618SOmar.Naji@arm.com Tick act_at = ranks[i]->banks[j].openRow == Bank::NO_ROW ? 156410890Swendy.elsasser@arm.com std::max(ranks[i]->banks[j].actAllowedAt, curTick()) : 156510618SOmar.Naji@arm.com std::max(ranks[i]->banks[j].preAllowedAt, curTick()) + tRP; 156610211Sandreas.hansson@arm.com 156710890Swendy.elsasser@arm.com // When is the earliest the R/W burst can issue? 156812706Swendy.elsasser@arm.com const Tick col_allowed_at = (busState == READ) ? 156912706Swendy.elsasser@arm.com ranks[i]->banks[j].rdAllowedAt : 157012706Swendy.elsasser@arm.com ranks[i]->banks[j].wrAllowedAt; 157112706Swendy.elsasser@arm.com Tick col_at = std::max(col_allowed_at, act_at + tRCD); 157210393Swendy.elsasser@arm.com 157310890Swendy.elsasser@arm.com // bank can issue burst back-to-back (seamlessly) with 157410890Swendy.elsasser@arm.com // previous burst 157510890Swendy.elsasser@arm.com bool new_seamless_bank = col_at <= min_col_at; 157610393Swendy.elsasser@arm.com 157710890Swendy.elsasser@arm.com // if we found a new seamless bank or we have no 157810890Swendy.elsasser@arm.com // seamless banks, and got a bank with an earlier 157910890Swendy.elsasser@arm.com // activate time, it should be added to the bit mask 158010890Swendy.elsasser@arm.com if (new_seamless_bank || 158110890Swendy.elsasser@arm.com (!found_seamless_bank && act_at <= min_act_at)) { 158210890Swendy.elsasser@arm.com // if we did not have a seamless bank before, and 158310890Swendy.elsasser@arm.com // we do now, reset the bank mask, also reset it 158410890Swendy.elsasser@arm.com // if we have not yet found a seamless bank and 158510890Swendy.elsasser@arm.com // the activate time is smaller than what we have 158610890Swendy.elsasser@arm.com // seen so far 158710890Swendy.elsasser@arm.com if (!found_seamless_bank && 158810890Swendy.elsasser@arm.com (new_seamless_bank || act_at < min_act_at)) { 158912706Swendy.elsasser@arm.com std::fill(bank_mask.begin(), bank_mask.end(), 0); 159010393Swendy.elsasser@arm.com } 159110890Swendy.elsasser@arm.com 159210890Swendy.elsasser@arm.com found_seamless_bank |= new_seamless_bank; 159310890Swendy.elsasser@arm.com 159410890Swendy.elsasser@arm.com // ACT can occur 'behind the scenes' 159510890Swendy.elsasser@arm.com hidden_bank_prep = act_at <= hidden_act_max; 159610890Swendy.elsasser@arm.com 159710890Swendy.elsasser@arm.com // set the bit corresponding to the available bank 159812706Swendy.elsasser@arm.com replaceBits(bank_mask[i], j, j, 1); 159910890Swendy.elsasser@arm.com min_act_at = act_at; 160010211Sandreas.hansson@arm.com } 16019967SN/A } 16029967SN/A } 16039967SN/A } 160410211Sandreas.hansson@arm.com 160510890Swendy.elsasser@arm.com return make_pair(bank_mask, hidden_bank_prep); 16069967SN/A} 16079967SN/A 160812081Sspwilson2@wisc.eduDRAMCtrl::Rank::Rank(DRAMCtrl& _memory, const DRAMCtrlParams* _p, int rank) 160910618SOmar.Naji@arm.com : EventManager(&_memory), memory(_memory), 161011678Swendy.elsasser@arm.com pwrStateTrans(PWR_IDLE), pwrStatePostRefresh(PWR_IDLE), 161111678Swendy.elsasser@arm.com pwrStateTick(0), refreshDueAt(0), pwrState(PWR_IDLE), 161212081Sspwilson2@wisc.edu refreshState(REF_IDLE), inLowPowerState(false), rank(rank), 161311678Swendy.elsasser@arm.com readEntries(0), writeEntries(0), outstandingEvents(0), 161412081Sspwilson2@wisc.edu wakeUpAllowedAt(0), power(_p, false), banks(_p->banks_per_rank), 161512081Sspwilson2@wisc.edu numBanksActive(0), actTicks(_p->activation_limit, 0), 161612084Sspwilson2@wisc.edu writeDoneEvent([this]{ processWriteDoneEvent(); }, name()), 161712084Sspwilson2@wisc.edu activateEvent([this]{ processActivateEvent(); }, name()), 161812084Sspwilson2@wisc.edu prechargeEvent([this]{ processPrechargeEvent(); }, name()), 161912084Sspwilson2@wisc.edu refreshEvent([this]{ processRefreshEvent(); }, name()), 162012084Sspwilson2@wisc.edu powerEvent([this]{ processPowerEvent(); }, name()), 162112084Sspwilson2@wisc.edu wakeUpEvent([this]{ processWakeUpEvent(); }, name()) 162212081Sspwilson2@wisc.edu{ 162312081Sspwilson2@wisc.edu for (int b = 0; b < _p->banks_per_rank; b++) { 162412081Sspwilson2@wisc.edu banks[b].bank = b; 162512081Sspwilson2@wisc.edu // GDDR addressing of banks to BG is linear. 162612081Sspwilson2@wisc.edu // Here we assume that all DRAM generations address bank groups as 162712081Sspwilson2@wisc.edu // follows: 162812081Sspwilson2@wisc.edu if (_p->bank_groups_per_rank > 0) { 162912081Sspwilson2@wisc.edu // Simply assign lower bits to bank group in order to 163012081Sspwilson2@wisc.edu // rotate across bank groups as banks are incremented 163112081Sspwilson2@wisc.edu // e.g. with 4 banks per bank group and 16 banks total: 163212081Sspwilson2@wisc.edu // banks 0,4,8,12 are in bank group 0 163312081Sspwilson2@wisc.edu // banks 1,5,9,13 are in bank group 1 163412081Sspwilson2@wisc.edu // banks 2,6,10,14 are in bank group 2 163512081Sspwilson2@wisc.edu // banks 3,7,11,15 are in bank group 3 163612081Sspwilson2@wisc.edu banks[b].bankgr = b % _p->bank_groups_per_rank; 163712081Sspwilson2@wisc.edu } else { 163812081Sspwilson2@wisc.edu // No bank groups; simply assign to bank number 163912081Sspwilson2@wisc.edu banks[b].bankgr = b; 164012081Sspwilson2@wisc.edu } 164112081Sspwilson2@wisc.edu } 164212081Sspwilson2@wisc.edu} 164310618SOmar.Naji@arm.com 16449243SN/Avoid 164510618SOmar.Naji@arm.comDRAMCtrl::Rank::startup(Tick ref_tick) 164610618SOmar.Naji@arm.com{ 164710618SOmar.Naji@arm.com assert(ref_tick > curTick()); 164810618SOmar.Naji@arm.com 164910618SOmar.Naji@arm.com pwrStateTick = curTick(); 165010618SOmar.Naji@arm.com 165110618SOmar.Naji@arm.com // kick off the refresh, and give ourselves enough time to 165210618SOmar.Naji@arm.com // precharge 165310618SOmar.Naji@arm.com schedule(refreshEvent, ref_tick); 165410618SOmar.Naji@arm.com} 165510618SOmar.Naji@arm.com 165610618SOmar.Naji@arm.comvoid 165710619Sandreas.hansson@arm.comDRAMCtrl::Rank::suspend() 165810619Sandreas.hansson@arm.com{ 165910619Sandreas.hansson@arm.com deschedule(refreshEvent); 166011676Swendy.elsasser@arm.com 166111676Swendy.elsasser@arm.com // Update the stats 166211676Swendy.elsasser@arm.com updatePowerStats(); 166311678Swendy.elsasser@arm.com 166411678Swendy.elsasser@arm.com // don't automatically transition back to LP state after next REF 166511678Swendy.elsasser@arm.com pwrStatePostRefresh = PWR_IDLE; 166611678Swendy.elsasser@arm.com} 166711678Swendy.elsasser@arm.com 166811678Swendy.elsasser@arm.combool 166912705Swendy.elsasser@arm.comDRAMCtrl::Rank::isQueueEmpty() const 167011678Swendy.elsasser@arm.com{ 167112705Swendy.elsasser@arm.com // check commmands in Q based on current bus direction 167211678Swendy.elsasser@arm.com bool no_queued_cmds = ((memory.busStateNext == READ) && (readEntries == 0)) 167311678Swendy.elsasser@arm.com || ((memory.busStateNext == WRITE) && 167411678Swendy.elsasser@arm.com (writeEntries == 0)); 167512705Swendy.elsasser@arm.com return no_queued_cmds; 167610619Sandreas.hansson@arm.com} 167710619Sandreas.hansson@arm.com 167810619Sandreas.hansson@arm.comvoid 167910618SOmar.Naji@arm.comDRAMCtrl::Rank::checkDrainDone() 168010618SOmar.Naji@arm.com{ 168110618SOmar.Naji@arm.com // if this rank was waiting to drain it is now able to proceed to 168210618SOmar.Naji@arm.com // precharge 168310618SOmar.Naji@arm.com if (refreshState == REF_DRAIN) { 168410618SOmar.Naji@arm.com DPRINTF(DRAM, "Refresh drain done, now precharging\n"); 168510618SOmar.Naji@arm.com 168611678Swendy.elsasser@arm.com refreshState = REF_PD_EXIT; 168710618SOmar.Naji@arm.com 168810618SOmar.Naji@arm.com // hand control back to the refresh event loop 168910618SOmar.Naji@arm.com schedule(refreshEvent, curTick()); 169010618SOmar.Naji@arm.com } 169110618SOmar.Naji@arm.com} 169210618SOmar.Naji@arm.com 169310618SOmar.Naji@arm.comvoid 169411675Swendy.elsasser@arm.comDRAMCtrl::Rank::flushCmdList() 169511675Swendy.elsasser@arm.com{ 169611675Swendy.elsasser@arm.com // at the moment sort the list of commands and update the counters 169711675Swendy.elsasser@arm.com // for DRAMPower libray when doing a refresh 169811675Swendy.elsasser@arm.com sort(cmdList.begin(), cmdList.end(), DRAMCtrl::sortTime); 169911675Swendy.elsasser@arm.com 170011675Swendy.elsasser@arm.com auto next_iter = cmdList.begin(); 170111675Swendy.elsasser@arm.com // push to commands to DRAMPower 170211675Swendy.elsasser@arm.com for ( ; next_iter != cmdList.end() ; ++next_iter) { 170311675Swendy.elsasser@arm.com Command cmd = *next_iter; 170411675Swendy.elsasser@arm.com if (cmd.timeStamp <= curTick()) { 170511675Swendy.elsasser@arm.com // Move all commands at or before curTick to DRAMPower 170611675Swendy.elsasser@arm.com power.powerlib.doCommand(cmd.type, cmd.bank, 170711675Swendy.elsasser@arm.com divCeil(cmd.timeStamp, memory.tCK) - 170811675Swendy.elsasser@arm.com memory.timeStampOffset); 170911675Swendy.elsasser@arm.com } else { 171011675Swendy.elsasser@arm.com // done - found all commands at or before curTick() 171111675Swendy.elsasser@arm.com // next_iter references the 1st command after curTick 171211675Swendy.elsasser@arm.com break; 171311675Swendy.elsasser@arm.com } 171411675Swendy.elsasser@arm.com } 171511675Swendy.elsasser@arm.com // reset cmdList to only contain commands after curTick 171611675Swendy.elsasser@arm.com // if there are no commands after curTick, updated cmdList will be empty 171711675Swendy.elsasser@arm.com // in this case, next_iter is cmdList.end() 171811675Swendy.elsasser@arm.com cmdList.assign(next_iter, cmdList.end()); 171911675Swendy.elsasser@arm.com} 172011675Swendy.elsasser@arm.com 172111675Swendy.elsasser@arm.comvoid 172210618SOmar.Naji@arm.comDRAMCtrl::Rank::processActivateEvent() 172310618SOmar.Naji@arm.com{ 172410618SOmar.Naji@arm.com // we should transition to the active state as soon as any bank is active 172510618SOmar.Naji@arm.com if (pwrState != PWR_ACT) 172610618SOmar.Naji@arm.com // note that at this point numBanksActive could be back at 172710618SOmar.Naji@arm.com // zero again due to a precharge scheduled in the future 172810618SOmar.Naji@arm.com schedulePowerEvent(PWR_ACT, curTick()); 172910618SOmar.Naji@arm.com} 173010618SOmar.Naji@arm.com 173110618SOmar.Naji@arm.comvoid 173210618SOmar.Naji@arm.comDRAMCtrl::Rank::processPrechargeEvent() 173310618SOmar.Naji@arm.com{ 173411678Swendy.elsasser@arm.com // counter should at least indicate one outstanding request 173511678Swendy.elsasser@arm.com // for this precharge 173611678Swendy.elsasser@arm.com assert(outstandingEvents > 0); 173711678Swendy.elsasser@arm.com // precharge complete, decrement count 173811678Swendy.elsasser@arm.com --outstandingEvents; 173911678Swendy.elsasser@arm.com 174010618SOmar.Naji@arm.com // if we reached zero, then special conditions apply as we track 174110618SOmar.Naji@arm.com // if all banks are precharged for the power models 174210618SOmar.Naji@arm.com if (numBanksActive == 0) { 174311678Swendy.elsasser@arm.com // no reads to this rank in the Q and no pending 174411678Swendy.elsasser@arm.com // RD/WR or refresh commands 174512705Swendy.elsasser@arm.com if (isQueueEmpty() && outstandingEvents == 0) { 174611678Swendy.elsasser@arm.com // should still be in ACT state since bank still open 174711678Swendy.elsasser@arm.com assert(pwrState == PWR_ACT); 174811678Swendy.elsasser@arm.com 174911678Swendy.elsasser@arm.com // All banks closed - switch to precharge power down state. 175011678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Rank %d sleep at tick %d\n", 175111678Swendy.elsasser@arm.com rank, curTick()); 175211678Swendy.elsasser@arm.com powerDownSleep(PWR_PRE_PDN, curTick()); 175311678Swendy.elsasser@arm.com } else { 175411678Swendy.elsasser@arm.com // we should transition to the idle state when the last bank 175511678Swendy.elsasser@arm.com // is precharged 175611678Swendy.elsasser@arm.com schedulePowerEvent(PWR_IDLE, curTick()); 175711678Swendy.elsasser@arm.com } 175810618SOmar.Naji@arm.com } 175910618SOmar.Naji@arm.com} 176010618SOmar.Naji@arm.com 176110618SOmar.Naji@arm.comvoid 176211678Swendy.elsasser@arm.comDRAMCtrl::Rank::processWriteDoneEvent() 176311678Swendy.elsasser@arm.com{ 176411678Swendy.elsasser@arm.com // counter should at least indicate one outstanding request 176511678Swendy.elsasser@arm.com // for this write 176611678Swendy.elsasser@arm.com assert(outstandingEvents > 0); 176711678Swendy.elsasser@arm.com // Write transfer on bus has completed 176811678Swendy.elsasser@arm.com // decrement per rank counter 176911678Swendy.elsasser@arm.com --outstandingEvents; 177011678Swendy.elsasser@arm.com} 177111678Swendy.elsasser@arm.com 177211678Swendy.elsasser@arm.comvoid 177310618SOmar.Naji@arm.comDRAMCtrl::Rank::processRefreshEvent() 17749243SN/A{ 177510207Sandreas.hansson@arm.com // when first preparing the refresh, remember when it was due 177611678Swendy.elsasser@arm.com if ((refreshState == REF_IDLE) || (refreshState == REF_SREF_EXIT)) { 177710207Sandreas.hansson@arm.com // remember when the refresh is due 177810207Sandreas.hansson@arm.com refreshDueAt = curTick(); 17799243SN/A 178010207Sandreas.hansson@arm.com // proceed to drain 178110207Sandreas.hansson@arm.com refreshState = REF_DRAIN; 17829243SN/A 178311678Swendy.elsasser@arm.com // make nonzero while refresh is pending to ensure 178411678Swendy.elsasser@arm.com // power down and self-refresh are not entered 178511678Swendy.elsasser@arm.com ++outstandingEvents; 178611678Swendy.elsasser@arm.com 178710207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh due\n"); 178810207Sandreas.hansson@arm.com } 178910207Sandreas.hansson@arm.com 179010618SOmar.Naji@arm.com // let any scheduled read or write to the same rank go ahead, 179110618SOmar.Naji@arm.com // after which it will 179210207Sandreas.hansson@arm.com // hand control back to this event loop 179310207Sandreas.hansson@arm.com if (refreshState == REF_DRAIN) { 179410618SOmar.Naji@arm.com // if a request is at the moment being handled and this request is 179510618SOmar.Naji@arm.com // accessing the current rank then wait for it to finish 179610618SOmar.Naji@arm.com if ((rank == memory.activeRank) 179710618SOmar.Naji@arm.com && (memory.nextReqEvent.scheduled())) { 179810207Sandreas.hansson@arm.com // hand control over to the request loop until it is 179910207Sandreas.hansson@arm.com // evaluated next 180010207Sandreas.hansson@arm.com DPRINTF(DRAM, "Refresh awaiting draining\n"); 180110207Sandreas.hansson@arm.com 180210207Sandreas.hansson@arm.com return; 180310207Sandreas.hansson@arm.com } else { 180411678Swendy.elsasser@arm.com refreshState = REF_PD_EXIT; 180511678Swendy.elsasser@arm.com } 180611678Swendy.elsasser@arm.com } 180711678Swendy.elsasser@arm.com 180811678Swendy.elsasser@arm.com // at this point, ensure that rank is not in a power-down state 180911678Swendy.elsasser@arm.com if (refreshState == REF_PD_EXIT) { 181011678Swendy.elsasser@arm.com // if rank was sleeping and we have't started exit process, 181111678Swendy.elsasser@arm.com // wake-up for refresh 181211678Swendy.elsasser@arm.com if (inLowPowerState) { 181311678Swendy.elsasser@arm.com DPRINTF(DRAM, "Wake Up for refresh\n"); 181411678Swendy.elsasser@arm.com // save state and return after refresh completes 181511678Swendy.elsasser@arm.com scheduleWakeUpEvent(memory.tXP); 181611678Swendy.elsasser@arm.com return; 181711678Swendy.elsasser@arm.com } else { 181810207Sandreas.hansson@arm.com refreshState = REF_PRE; 181910207Sandreas.hansson@arm.com } 182010207Sandreas.hansson@arm.com } 182110207Sandreas.hansson@arm.com 182210207Sandreas.hansson@arm.com // at this point, ensure that all banks are precharged 182310207Sandreas.hansson@arm.com if (refreshState == REF_PRE) { 182411678Swendy.elsasser@arm.com // precharge any active bank 182511678Swendy.elsasser@arm.com if (numBanksActive != 0) { 182610214Sandreas.hansson@arm.com // at the moment, we use a precharge all even if there is 182710214Sandreas.hansson@arm.com // only a single bank open 182810208Sandreas.hansson@arm.com DPRINTF(DRAM, "Precharging all\n"); 182910214Sandreas.hansson@arm.com 183010214Sandreas.hansson@arm.com // first determine when we can precharge 183110214Sandreas.hansson@arm.com Tick pre_at = curTick(); 183210618SOmar.Naji@arm.com 183310618SOmar.Naji@arm.com for (auto &b : banks) { 183410618SOmar.Naji@arm.com // respect both causality and any existing bank 183510618SOmar.Naji@arm.com // constraints, some banks could already have a 183610618SOmar.Naji@arm.com // (auto) precharge scheduled 183710618SOmar.Naji@arm.com pre_at = std::max(b.preAllowedAt, pre_at); 183810618SOmar.Naji@arm.com } 183910618SOmar.Naji@arm.com 184010618SOmar.Naji@arm.com // make sure all banks per rank are precharged, and for those that 184110618SOmar.Naji@arm.com // already are, update their availability 184210618SOmar.Naji@arm.com Tick act_allowed_at = pre_at + memory.tRP; 184310618SOmar.Naji@arm.com 184410618SOmar.Naji@arm.com for (auto &b : banks) { 184510618SOmar.Naji@arm.com if (b.openRow != Bank::NO_ROW) { 184610618SOmar.Naji@arm.com memory.prechargeBank(*this, b, pre_at, false); 184710618SOmar.Naji@arm.com } else { 184810618SOmar.Naji@arm.com b.actAllowedAt = std::max(b.actAllowedAt, act_allowed_at); 184910618SOmar.Naji@arm.com b.preAllowedAt = std::max(b.preAllowedAt, pre_at); 185010214Sandreas.hansson@arm.com } 185110214Sandreas.hansson@arm.com } 185210214Sandreas.hansson@arm.com 185310618SOmar.Naji@arm.com // precharge all banks in rank 185411675Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::PREA, 0, pre_at)); 185510214Sandreas.hansson@arm.com 185610618SOmar.Naji@arm.com DPRINTF(DRAMPower, "%llu,PREA,0,%d\n", 185710618SOmar.Naji@arm.com divCeil(pre_at, memory.tCK) - 185810618SOmar.Naji@arm.com memory.timeStampOffset, rank); 185911678Swendy.elsasser@arm.com } else if ((pwrState == PWR_IDLE) && (outstandingEvents == 1)) { 186011678Swendy.elsasser@arm.com // Banks are closed, have transitioned to IDLE state, and 186111678Swendy.elsasser@arm.com // no outstanding ACT,RD/WR,Auto-PRE sequence scheduled 186210208Sandreas.hansson@arm.com DPRINTF(DRAM, "All banks already precharged, starting refresh\n"); 186310208Sandreas.hansson@arm.com 186411678Swendy.elsasser@arm.com // go ahead and kick the power state machine into gear since 186510208Sandreas.hansson@arm.com // we are already idle 186610208Sandreas.hansson@arm.com schedulePowerEvent(PWR_REF, curTick()); 186711678Swendy.elsasser@arm.com } else { 186811678Swendy.elsasser@arm.com // banks state is closed but haven't transitioned pwrState to IDLE 186911678Swendy.elsasser@arm.com // or have outstanding ACT,RD/WR,Auto-PRE sequence scheduled 187011678Swendy.elsasser@arm.com // should have outstanding precharge event in this case 187111678Swendy.elsasser@arm.com assert(prechargeEvent.scheduled()); 187211678Swendy.elsasser@arm.com // will start refresh when pwrState transitions to IDLE 18739975SN/A } 18749975SN/A 187510208Sandreas.hansson@arm.com assert(numBanksActive == 0); 18769243SN/A 187710208Sandreas.hansson@arm.com // wait for all banks to be precharged, at which point the 187810208Sandreas.hansson@arm.com // power state machine will transition to the idle state, and 187910208Sandreas.hansson@arm.com // automatically move to a refresh, at that point it will also 188010208Sandreas.hansson@arm.com // call this method to get the refresh event loop going again 188110207Sandreas.hansson@arm.com return; 188210207Sandreas.hansson@arm.com } 188310207Sandreas.hansson@arm.com 188410207Sandreas.hansson@arm.com // last but not least we perform the actual refresh 188511678Swendy.elsasser@arm.com if (refreshState == REF_START) { 188611678Swendy.elsasser@arm.com // should never get here with any banks active 188711678Swendy.elsasser@arm.com assert(numBanksActive == 0); 188811678Swendy.elsasser@arm.com assert(pwrState == PWR_REF); 188911678Swendy.elsasser@arm.com 189011678Swendy.elsasser@arm.com Tick ref_done_at = curTick() + memory.tRFC; 189111678Swendy.elsasser@arm.com 189211678Swendy.elsasser@arm.com for (auto &b : banks) { 189311678Swendy.elsasser@arm.com b.actAllowedAt = ref_done_at; 189411678Swendy.elsasser@arm.com } 189511678Swendy.elsasser@arm.com 189611678Swendy.elsasser@arm.com // at the moment this affects all ranks 189711678Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::REF, 0, curTick())); 189811678Swendy.elsasser@arm.com 189911678Swendy.elsasser@arm.com // Update the stats 190011678Swendy.elsasser@arm.com updatePowerStats(); 190111678Swendy.elsasser@arm.com 190211678Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,REF,0,%d\n", divCeil(curTick(), memory.tCK) - 190311678Swendy.elsasser@arm.com memory.timeStampOffset, rank); 190411678Swendy.elsasser@arm.com 190511678Swendy.elsasser@arm.com // Update for next refresh 190611678Swendy.elsasser@arm.com refreshDueAt += memory.tREFI; 190711678Swendy.elsasser@arm.com 190811678Swendy.elsasser@arm.com // make sure we did not wait so long that we cannot make up 190911678Swendy.elsasser@arm.com // for it 191011678Swendy.elsasser@arm.com if (refreshDueAt < ref_done_at) { 191111678Swendy.elsasser@arm.com fatal("Refresh was delayed so long we cannot catch up\n"); 191211678Swendy.elsasser@arm.com } 191311678Swendy.elsasser@arm.com 191411678Swendy.elsasser@arm.com // Run the refresh and schedule event to transition power states 191511678Swendy.elsasser@arm.com // when refresh completes 191611678Swendy.elsasser@arm.com refreshState = REF_RUN; 191711678Swendy.elsasser@arm.com schedule(refreshEvent, ref_done_at); 191811678Swendy.elsasser@arm.com return; 191911678Swendy.elsasser@arm.com } 192011678Swendy.elsasser@arm.com 192110207Sandreas.hansson@arm.com if (refreshState == REF_RUN) { 192210207Sandreas.hansson@arm.com // should never get here with any banks active 192310207Sandreas.hansson@arm.com assert(numBanksActive == 0); 192410208Sandreas.hansson@arm.com assert(pwrState == PWR_REF); 192510207Sandreas.hansson@arm.com 192611678Swendy.elsasser@arm.com assert(!powerEvent.scheduled()); 192711678Swendy.elsasser@arm.com 192811678Swendy.elsasser@arm.com if ((memory.drainState() == DrainState::Draining) || 192911678Swendy.elsasser@arm.com (memory.drainState() == DrainState::Drained)) { 193011678Swendy.elsasser@arm.com // if draining, do not re-enter low-power mode. 193111678Swendy.elsasser@arm.com // simply go to IDLE and wait 193211678Swendy.elsasser@arm.com schedulePowerEvent(PWR_IDLE, curTick()); 193311678Swendy.elsasser@arm.com } else { 193411678Swendy.elsasser@arm.com // At the moment, we sleep when the refresh ends and wait to be 193511678Swendy.elsasser@arm.com // woken up again if previously in a low-power state. 193611678Swendy.elsasser@arm.com if (pwrStatePostRefresh != PWR_IDLE) { 193711678Swendy.elsasser@arm.com // power State should be power Refresh 193811678Swendy.elsasser@arm.com assert(pwrState == PWR_REF); 193911678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Rank %d sleeping after refresh and was in " 194011678Swendy.elsasser@arm.com "power state %d before refreshing\n", rank, 194111678Swendy.elsasser@arm.com pwrStatePostRefresh); 194211678Swendy.elsasser@arm.com powerDownSleep(pwrState, curTick()); 194311678Swendy.elsasser@arm.com 194411678Swendy.elsasser@arm.com // Force PRE power-down if there are no outstanding commands 194511678Swendy.elsasser@arm.com // in Q after refresh. 194612705Swendy.elsasser@arm.com } else if (isQueueEmpty()) { 194712705Swendy.elsasser@arm.com // still have refresh event outstanding but there should 194812705Swendy.elsasser@arm.com // be no other events outstanding 194912705Swendy.elsasser@arm.com assert(outstandingEvents == 1); 195011678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Rank %d sleeping after refresh but was NOT" 195111678Swendy.elsasser@arm.com " in a low power state before refreshing\n", rank); 195211678Swendy.elsasser@arm.com powerDownSleep(PWR_PRE_PDN, curTick()); 195311678Swendy.elsasser@arm.com 195411678Swendy.elsasser@arm.com } else { 195511678Swendy.elsasser@arm.com // move to the idle power state once the refresh is done, this 195611678Swendy.elsasser@arm.com // will also move the refresh state machine to the refresh 195711678Swendy.elsasser@arm.com // idle state 195811678Swendy.elsasser@arm.com schedulePowerEvent(PWR_IDLE, curTick()); 195911678Swendy.elsasser@arm.com } 196010618SOmar.Naji@arm.com } 196110247Sandreas.hansson@arm.com 196212705Swendy.elsasser@arm.com // At this point, we have completed the current refresh. 196312705Swendy.elsasser@arm.com // In the SREF bypass case, we do not get to this state in the 196412705Swendy.elsasser@arm.com // refresh STM and therefore can always schedule next event. 196512705Swendy.elsasser@arm.com // Compensate for the delay in actually performing the refresh 196612705Swendy.elsasser@arm.com // when scheduling the next one 196712705Swendy.elsasser@arm.com schedule(refreshEvent, refreshDueAt - memory.tRP); 196812705Swendy.elsasser@arm.com 196912705Swendy.elsasser@arm.com DPRINTF(DRAMState, "Refresh done at %llu and next refresh" 197012705Swendy.elsasser@arm.com " at %llu\n", curTick(), refreshDueAt); 197110208Sandreas.hansson@arm.com } 197210208Sandreas.hansson@arm.com} 197310208Sandreas.hansson@arm.com 197410208Sandreas.hansson@arm.comvoid 197510618SOmar.Naji@arm.comDRAMCtrl::Rank::schedulePowerEvent(PowerState pwr_state, Tick tick) 197610208Sandreas.hansson@arm.com{ 197710208Sandreas.hansson@arm.com // respect causality 197810208Sandreas.hansson@arm.com assert(tick >= curTick()); 197910208Sandreas.hansson@arm.com 198010208Sandreas.hansson@arm.com if (!powerEvent.scheduled()) { 198110208Sandreas.hansson@arm.com DPRINTF(DRAMState, "Scheduling power event at %llu to state %d\n", 198210208Sandreas.hansson@arm.com tick, pwr_state); 198310208Sandreas.hansson@arm.com 198410208Sandreas.hansson@arm.com // insert the new transition 198510208Sandreas.hansson@arm.com pwrStateTrans = pwr_state; 198610208Sandreas.hansson@arm.com 198710208Sandreas.hansson@arm.com schedule(powerEvent, tick); 198810208Sandreas.hansson@arm.com } else { 198910208Sandreas.hansson@arm.com panic("Scheduled power event at %llu to state %d, " 199010208Sandreas.hansson@arm.com "with scheduled event at %llu to %d\n", tick, pwr_state, 199110208Sandreas.hansson@arm.com powerEvent.when(), pwrStateTrans); 199210208Sandreas.hansson@arm.com } 199310208Sandreas.hansson@arm.com} 199410208Sandreas.hansson@arm.com 199510208Sandreas.hansson@arm.comvoid 199611678Swendy.elsasser@arm.comDRAMCtrl::Rank::powerDownSleep(PowerState pwr_state, Tick tick) 199711678Swendy.elsasser@arm.com{ 199811678Swendy.elsasser@arm.com // if low power state is active low, schedule to active low power state. 199911678Swendy.elsasser@arm.com // in reality tCKE is needed to enter active low power. This is neglected 200011678Swendy.elsasser@arm.com // here and could be added in the future. 200111678Swendy.elsasser@arm.com if (pwr_state == PWR_ACT_PDN) { 200211678Swendy.elsasser@arm.com schedulePowerEvent(pwr_state, tick); 200311678Swendy.elsasser@arm.com // push command to DRAMPower 200411678Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::PDN_F_ACT, 0, tick)); 200511678Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,PDN_F_ACT,0,%d\n", divCeil(tick, 200611678Swendy.elsasser@arm.com memory.tCK) - memory.timeStampOffset, rank); 200711678Swendy.elsasser@arm.com } else if (pwr_state == PWR_PRE_PDN) { 200811678Swendy.elsasser@arm.com // if low power state is precharge low, schedule to precharge low 200911678Swendy.elsasser@arm.com // power state. In reality tCKE is needed to enter active low power. 201011678Swendy.elsasser@arm.com // This is neglected here. 201111678Swendy.elsasser@arm.com schedulePowerEvent(pwr_state, tick); 201211678Swendy.elsasser@arm.com //push Command to DRAMPower 201311678Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::PDN_F_PRE, 0, tick)); 201411678Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,PDN_F_PRE,0,%d\n", divCeil(tick, 201511678Swendy.elsasser@arm.com memory.tCK) - memory.timeStampOffset, rank); 201611678Swendy.elsasser@arm.com } else if (pwr_state == PWR_REF) { 201712705Swendy.elsasser@arm.com // if a refresh just occurred 201811678Swendy.elsasser@arm.com // transition to PRE_PDN now that all banks are closed 201912705Swendy.elsasser@arm.com // precharge power down requires tCKE to enter. For simplicity 202012705Swendy.elsasser@arm.com // this is not considered. 202112705Swendy.elsasser@arm.com schedulePowerEvent(PWR_PRE_PDN, tick); 202212705Swendy.elsasser@arm.com //push Command to DRAMPower 202312705Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::PDN_F_PRE, 0, tick)); 202412705Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,PDN_F_PRE,0,%d\n", divCeil(tick, 202512705Swendy.elsasser@arm.com memory.tCK) - memory.timeStampOffset, rank); 202612705Swendy.elsasser@arm.com } else if (pwr_state == PWR_SREF) { 202712705Swendy.elsasser@arm.com // should only enter SREF after PRE-PD wakeup to do a refresh 202812705Swendy.elsasser@arm.com assert(pwrStatePostRefresh == PWR_PRE_PDN); 202912705Swendy.elsasser@arm.com // self refresh requires time tCKESR to enter. For simplicity, 203012705Swendy.elsasser@arm.com // this is not considered. 203112705Swendy.elsasser@arm.com schedulePowerEvent(PWR_SREF, tick); 203212705Swendy.elsasser@arm.com // push Command to DRAMPower 203312705Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::SREN, 0, tick)); 203412705Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,SREN,0,%d\n", divCeil(tick, 203512705Swendy.elsasser@arm.com memory.tCK) - memory.timeStampOffset, rank); 203611678Swendy.elsasser@arm.com } 203711678Swendy.elsasser@arm.com // Ensure that we don't power-down and back up in same tick 203811678Swendy.elsasser@arm.com // Once we commit to PD entry, do it and wait for at least 1tCK 203911678Swendy.elsasser@arm.com // This could be replaced with tCKE if/when that is added to the model 204011678Swendy.elsasser@arm.com wakeUpAllowedAt = tick + memory.tCK; 204111678Swendy.elsasser@arm.com 204211678Swendy.elsasser@arm.com // Transitioning to a low power state, set flag 204311678Swendy.elsasser@arm.com inLowPowerState = true; 204411678Swendy.elsasser@arm.com} 204511678Swendy.elsasser@arm.com 204611678Swendy.elsasser@arm.comvoid 204711678Swendy.elsasser@arm.comDRAMCtrl::Rank::scheduleWakeUpEvent(Tick exit_delay) 204811678Swendy.elsasser@arm.com{ 204911678Swendy.elsasser@arm.com Tick wake_up_tick = std::max(curTick(), wakeUpAllowedAt); 205011678Swendy.elsasser@arm.com 205111678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Scheduling wake-up for rank %d at tick %d\n", 205211678Swendy.elsasser@arm.com rank, wake_up_tick); 205311678Swendy.elsasser@arm.com 205411678Swendy.elsasser@arm.com // if waking for refresh, hold previous state 205511678Swendy.elsasser@arm.com // else reset state back to IDLE 205611678Swendy.elsasser@arm.com if (refreshState == REF_PD_EXIT) { 205711678Swendy.elsasser@arm.com pwrStatePostRefresh = pwrState; 205811678Swendy.elsasser@arm.com } else { 205911678Swendy.elsasser@arm.com // don't automatically transition back to LP state after next REF 206011678Swendy.elsasser@arm.com pwrStatePostRefresh = PWR_IDLE; 206111678Swendy.elsasser@arm.com } 206211678Swendy.elsasser@arm.com 206311678Swendy.elsasser@arm.com // schedule wake-up with event to ensure entry has completed before 206411678Swendy.elsasser@arm.com // we try to wake-up 206511678Swendy.elsasser@arm.com schedule(wakeUpEvent, wake_up_tick); 206611678Swendy.elsasser@arm.com 206711678Swendy.elsasser@arm.com for (auto &b : banks) { 206811678Swendy.elsasser@arm.com // respect both causality and any existing bank 206911678Swendy.elsasser@arm.com // constraints, some banks could already have a 207011678Swendy.elsasser@arm.com // (auto) precharge scheduled 207112706Swendy.elsasser@arm.com b.wrAllowedAt = std::max(wake_up_tick + exit_delay, b.wrAllowedAt); 207212706Swendy.elsasser@arm.com b.rdAllowedAt = std::max(wake_up_tick + exit_delay, b.rdAllowedAt); 207311678Swendy.elsasser@arm.com b.preAllowedAt = std::max(wake_up_tick + exit_delay, b.preAllowedAt); 207411678Swendy.elsasser@arm.com b.actAllowedAt = std::max(wake_up_tick + exit_delay, b.actAllowedAt); 207511678Swendy.elsasser@arm.com } 207611678Swendy.elsasser@arm.com // Transitioning out of low power state, clear flag 207711678Swendy.elsasser@arm.com inLowPowerState = false; 207811678Swendy.elsasser@arm.com 207911678Swendy.elsasser@arm.com // push to DRAMPower 208011678Swendy.elsasser@arm.com // use pwrStateTrans for cases where we have a power event scheduled 208111678Swendy.elsasser@arm.com // to enter low power that has not yet been processed 208211678Swendy.elsasser@arm.com if (pwrStateTrans == PWR_ACT_PDN) { 208311678Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::PUP_ACT, 0, wake_up_tick)); 208411678Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,PUP_ACT,0,%d\n", divCeil(wake_up_tick, 208511678Swendy.elsasser@arm.com memory.tCK) - memory.timeStampOffset, rank); 208611678Swendy.elsasser@arm.com 208711678Swendy.elsasser@arm.com } else if (pwrStateTrans == PWR_PRE_PDN) { 208811678Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::PUP_PRE, 0, wake_up_tick)); 208911678Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,PUP_PRE,0,%d\n", divCeil(wake_up_tick, 209011678Swendy.elsasser@arm.com memory.tCK) - memory.timeStampOffset, rank); 209111678Swendy.elsasser@arm.com } else if (pwrStateTrans == PWR_SREF) { 209211678Swendy.elsasser@arm.com cmdList.push_back(Command(MemCommand::SREX, 0, wake_up_tick)); 209311678Swendy.elsasser@arm.com DPRINTF(DRAMPower, "%llu,SREX,0,%d\n", divCeil(wake_up_tick, 209411678Swendy.elsasser@arm.com memory.tCK) - memory.timeStampOffset, rank); 209511678Swendy.elsasser@arm.com } 209611678Swendy.elsasser@arm.com} 209711678Swendy.elsasser@arm.com 209811678Swendy.elsasser@arm.comvoid 209911678Swendy.elsasser@arm.comDRAMCtrl::Rank::processWakeUpEvent() 210011678Swendy.elsasser@arm.com{ 210111678Swendy.elsasser@arm.com // Should be in a power-down or self-refresh state 210211678Swendy.elsasser@arm.com assert((pwrState == PWR_ACT_PDN) || (pwrState == PWR_PRE_PDN) || 210311678Swendy.elsasser@arm.com (pwrState == PWR_SREF)); 210411678Swendy.elsasser@arm.com 210511678Swendy.elsasser@arm.com // Check current state to determine transition state 210611678Swendy.elsasser@arm.com if (pwrState == PWR_ACT_PDN) { 210711678Swendy.elsasser@arm.com // banks still open, transition to PWR_ACT 210811678Swendy.elsasser@arm.com schedulePowerEvent(PWR_ACT, curTick()); 210911678Swendy.elsasser@arm.com } else { 211011678Swendy.elsasser@arm.com // transitioning from a precharge power-down or self-refresh state 211111678Swendy.elsasser@arm.com // banks are closed - transition to PWR_IDLE 211211678Swendy.elsasser@arm.com schedulePowerEvent(PWR_IDLE, curTick()); 211311678Swendy.elsasser@arm.com } 211411678Swendy.elsasser@arm.com} 211511678Swendy.elsasser@arm.com 211611678Swendy.elsasser@arm.comvoid 211710618SOmar.Naji@arm.comDRAMCtrl::Rank::processPowerEvent() 211810208Sandreas.hansson@arm.com{ 211911678Swendy.elsasser@arm.com assert(curTick() >= pwrStateTick); 212010208Sandreas.hansson@arm.com // remember where we were, and for how long 212110208Sandreas.hansson@arm.com Tick duration = curTick() - pwrStateTick; 212210208Sandreas.hansson@arm.com PowerState prev_state = pwrState; 212310208Sandreas.hansson@arm.com 212410208Sandreas.hansson@arm.com // update the accounting 212510208Sandreas.hansson@arm.com pwrStateTime[prev_state] += duration; 212610208Sandreas.hansson@arm.com 212711678Swendy.elsasser@arm.com // track to total idle time 212811678Swendy.elsasser@arm.com if ((prev_state == PWR_PRE_PDN) || (prev_state == PWR_ACT_PDN) || 212911678Swendy.elsasser@arm.com (prev_state == PWR_SREF)) { 213011678Swendy.elsasser@arm.com totalIdleTime += duration; 213111678Swendy.elsasser@arm.com } 213211678Swendy.elsasser@arm.com 213310208Sandreas.hansson@arm.com pwrState = pwrStateTrans; 213410208Sandreas.hansson@arm.com pwrStateTick = curTick(); 213510208Sandreas.hansson@arm.com 213611678Swendy.elsasser@arm.com // if rank was refreshing, make sure to start scheduling requests again 213711678Swendy.elsasser@arm.com if (prev_state == PWR_REF) { 213811678Swendy.elsasser@arm.com // bus IDLED prior to REF 213911678Swendy.elsasser@arm.com // counter should be one for refresh command only 214011678Swendy.elsasser@arm.com assert(outstandingEvents == 1); 214112705Swendy.elsasser@arm.com // REF complete, decrement count and go back to IDLE 214211678Swendy.elsasser@arm.com --outstandingEvents; 214312705Swendy.elsasser@arm.com refreshState = REF_IDLE; 214411678Swendy.elsasser@arm.com 214511678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Was refreshing for %llu ticks\n", duration); 214612705Swendy.elsasser@arm.com // if moving back to power-down after refresh 214711678Swendy.elsasser@arm.com if (pwrState != PWR_IDLE) { 214812705Swendy.elsasser@arm.com assert(pwrState == PWR_PRE_PDN); 214911678Swendy.elsasser@arm.com DPRINTF(DRAMState, "Switching to power down state after refreshing" 215011678Swendy.elsasser@arm.com " rank %d at %llu tick\n", rank, curTick()); 215111678Swendy.elsasser@arm.com } 215212705Swendy.elsasser@arm.com 215312705Swendy.elsasser@arm.com // completed refresh event, ensure next request is scheduled 215411678Swendy.elsasser@arm.com if (!memory.nextReqEvent.scheduled()) { 215512705Swendy.elsasser@arm.com DPRINTF(DRAM, "Scheduling next request after refreshing" 215612705Swendy.elsasser@arm.com " rank %d\n", rank); 215711678Swendy.elsasser@arm.com schedule(memory.nextReqEvent, curTick()); 215811678Swendy.elsasser@arm.com } 215912705Swendy.elsasser@arm.com } 216012705Swendy.elsasser@arm.com 216112705Swendy.elsasser@arm.com if ((pwrState == PWR_ACT) && (refreshState == REF_PD_EXIT)) { 216212705Swendy.elsasser@arm.com // have exited ACT PD 216312705Swendy.elsasser@arm.com assert(prev_state == PWR_ACT_PDN); 216412705Swendy.elsasser@arm.com 216512705Swendy.elsasser@arm.com // go back to REF event and close banks 216612705Swendy.elsasser@arm.com refreshState = REF_PRE; 216712705Swendy.elsasser@arm.com schedule(refreshEvent, curTick()); 216811678Swendy.elsasser@arm.com } else if (pwrState == PWR_IDLE) { 216910208Sandreas.hansson@arm.com DPRINTF(DRAMState, "All banks precharged\n"); 217011678Swendy.elsasser@arm.com if (prev_state == PWR_SREF) { 217112266Sradhika.jagtap@arm.com // set refresh state to REF_SREF_EXIT, ensuring inRefIdleState 217211678Swendy.elsasser@arm.com // continues to return false during tXS after SREF exit 217311678Swendy.elsasser@arm.com // Schedule a refresh which kicks things back into action 217411678Swendy.elsasser@arm.com // when it finishes 217511678Swendy.elsasser@arm.com refreshState = REF_SREF_EXIT; 217611678Swendy.elsasser@arm.com schedule(refreshEvent, curTick() + memory.tXS); 217710208Sandreas.hansson@arm.com } else { 217810208Sandreas.hansson@arm.com // if we have a pending refresh, and are now moving to 217912705Swendy.elsasser@arm.com // the idle state, directly transition to, or schedule refresh 218011678Swendy.elsasser@arm.com if ((refreshState == REF_PRE) || (refreshState == REF_PD_EXIT)) { 218111678Swendy.elsasser@arm.com // ensure refresh is restarted only after final PRE command. 218211678Swendy.elsasser@arm.com // do not restart refresh if controller is in an intermediate 218311678Swendy.elsasser@arm.com // state, after PRE_PDN exit, when banks are IDLE but an 218411678Swendy.elsasser@arm.com // ACT is scheduled. 218511678Swendy.elsasser@arm.com if (!activateEvent.scheduled()) { 218611678Swendy.elsasser@arm.com // there should be nothing waiting at this point 218711678Swendy.elsasser@arm.com assert(!powerEvent.scheduled()); 218812705Swendy.elsasser@arm.com if (refreshState == REF_PD_EXIT) { 218912705Swendy.elsasser@arm.com // exiting PRE PD, will be in IDLE until tXP expires 219012705Swendy.elsasser@arm.com // and then should transition to PWR_REF state 219112705Swendy.elsasser@arm.com assert(prev_state == PWR_PRE_PDN); 219212705Swendy.elsasser@arm.com schedulePowerEvent(PWR_REF, curTick() + memory.tXP); 219312705Swendy.elsasser@arm.com } else if (refreshState == REF_PRE) { 219412705Swendy.elsasser@arm.com // can directly move to PWR_REF state and proceed below 219512705Swendy.elsasser@arm.com pwrState = PWR_REF; 219612705Swendy.elsasser@arm.com } 219711678Swendy.elsasser@arm.com } else { 219811678Swendy.elsasser@arm.com // must have PRE scheduled to transition back to IDLE 219911678Swendy.elsasser@arm.com // and re-kick off refresh 220011678Swendy.elsasser@arm.com assert(prechargeEvent.scheduled()); 220111678Swendy.elsasser@arm.com } 220210208Sandreas.hansson@arm.com } 220312705Swendy.elsasser@arm.com } 220410208Sandreas.hansson@arm.com } 220510208Sandreas.hansson@arm.com 220612705Swendy.elsasser@arm.com // transition to the refresh state and re-start refresh process 220712705Swendy.elsasser@arm.com // refresh state machine will schedule the next power state transition 220810208Sandreas.hansson@arm.com if (pwrState == PWR_REF) { 220912705Swendy.elsasser@arm.com // completed final PRE for refresh or exiting power-down 221011678Swendy.elsasser@arm.com assert(refreshState == REF_PRE || refreshState == REF_PD_EXIT); 221112705Swendy.elsasser@arm.com 221212705Swendy.elsasser@arm.com // exited PRE PD for refresh, with no pending commands 221312705Swendy.elsasser@arm.com // bypass auto-refresh and go straight to SREF, where memory 221412705Swendy.elsasser@arm.com // will issue refresh immediately upon entry 221512705Swendy.elsasser@arm.com if (pwrStatePostRefresh == PWR_PRE_PDN && isQueueEmpty() && 221612705Swendy.elsasser@arm.com (memory.drainState() != DrainState::Draining) && 221712705Swendy.elsasser@arm.com (memory.drainState() != DrainState::Drained)) { 221812705Swendy.elsasser@arm.com DPRINTF(DRAMState, "Rank %d bypassing refresh and transitioning " 221912705Swendy.elsasser@arm.com "to self refresh at %11u tick\n", rank, curTick()); 222012705Swendy.elsasser@arm.com powerDownSleep(PWR_SREF, curTick()); 222112705Swendy.elsasser@arm.com 222212705Swendy.elsasser@arm.com // Since refresh was bypassed, remove event by decrementing count 222312705Swendy.elsasser@arm.com assert(outstandingEvents == 1); 222412705Swendy.elsasser@arm.com --outstandingEvents; 222512705Swendy.elsasser@arm.com 222612705Swendy.elsasser@arm.com // reset state back to IDLE temporarily until SREF is entered 222712705Swendy.elsasser@arm.com pwrState = PWR_IDLE; 222812705Swendy.elsasser@arm.com 222912705Swendy.elsasser@arm.com // Not bypassing refresh for SREF entry 223011678Swendy.elsasser@arm.com } else { 223112705Swendy.elsasser@arm.com DPRINTF(DRAMState, "Refreshing\n"); 223212705Swendy.elsasser@arm.com 223312705Swendy.elsasser@arm.com // there should be nothing waiting at this point 223412705Swendy.elsasser@arm.com assert(!powerEvent.scheduled()); 223512705Swendy.elsasser@arm.com 223612705Swendy.elsasser@arm.com // kick the refresh event loop into action again, and that 223712705Swendy.elsasser@arm.com // in turn will schedule a transition to the idle power 223812705Swendy.elsasser@arm.com // state once the refresh is done 223911678Swendy.elsasser@arm.com schedule(refreshEvent, curTick()); 224012705Swendy.elsasser@arm.com 224112705Swendy.elsasser@arm.com // Banks transitioned to IDLE, start REF 224212705Swendy.elsasser@arm.com refreshState = REF_START; 224311678Swendy.elsasser@arm.com } 224410207Sandreas.hansson@arm.com } 224512705Swendy.elsasser@arm.com 22469243SN/A} 22479243SN/A 22489243SN/Avoid 224910618SOmar.Naji@arm.comDRAMCtrl::Rank::updatePowerStats() 225010432SOmar.Naji@arm.com{ 225111676Swendy.elsasser@arm.com // All commands up to refresh have completed 225211676Swendy.elsasser@arm.com // flush cmdList to DRAMPower 225311676Swendy.elsasser@arm.com flushCmdList(); 225411676Swendy.elsasser@arm.com 225512266Sradhika.jagtap@arm.com // Call the function that calculates window energy at intermediate update 225612266Sradhika.jagtap@arm.com // events like at refresh, stats dump as well as at simulation exit. 225712266Sradhika.jagtap@arm.com // Window starts at the last time the calcWindowEnergy function was called 225812266Sradhika.jagtap@arm.com // and is upto current time. 225912266Sradhika.jagtap@arm.com power.powerlib.calcWindowEnergy(divCeil(curTick(), memory.tCK) - 226012266Sradhika.jagtap@arm.com memory.timeStampOffset); 226112266Sradhika.jagtap@arm.com 226212266Sradhika.jagtap@arm.com // Get the energy from DRAMPower 226312266Sradhika.jagtap@arm.com Data::MemoryPowerModel::Energy energy = power.powerlib.getEnergy(); 226412266Sradhika.jagtap@arm.com 226512266Sradhika.jagtap@arm.com // The energy components inside the power lib are calculated over 226612266Sradhika.jagtap@arm.com // the window so accumulate into the corresponding gem5 stat 226712266Sradhika.jagtap@arm.com actEnergy += energy.act_energy * memory.devicesPerRank; 226812266Sradhika.jagtap@arm.com preEnergy += energy.pre_energy * memory.devicesPerRank; 226912266Sradhika.jagtap@arm.com readEnergy += energy.read_energy * memory.devicesPerRank; 227012266Sradhika.jagtap@arm.com writeEnergy += energy.write_energy * memory.devicesPerRank; 227112266Sradhika.jagtap@arm.com refreshEnergy += energy.ref_energy * memory.devicesPerRank; 227212266Sradhika.jagtap@arm.com actBackEnergy += energy.act_stdby_energy * memory.devicesPerRank; 227312266Sradhika.jagtap@arm.com preBackEnergy += energy.pre_stdby_energy * memory.devicesPerRank; 227412266Sradhika.jagtap@arm.com actPowerDownEnergy += energy.f_act_pd_energy * memory.devicesPerRank; 227512266Sradhika.jagtap@arm.com prePowerDownEnergy += energy.f_pre_pd_energy * memory.devicesPerRank; 227612266Sradhika.jagtap@arm.com selfRefreshEnergy += energy.sref_energy * memory.devicesPerRank; 227712266Sradhika.jagtap@arm.com 227812266Sradhika.jagtap@arm.com // Accumulate window energy into the total energy. 227912266Sradhika.jagtap@arm.com totalEnergy += energy.window_energy * memory.devicesPerRank; 228012266Sradhika.jagtap@arm.com // Average power must not be accumulated but calculated over the time 228112266Sradhika.jagtap@arm.com // since last stats reset. SimClock::Frequency is tick period not tick 228212266Sradhika.jagtap@arm.com // frequency. 228312266Sradhika.jagtap@arm.com // energy (pJ) 1e-9 228412266Sradhika.jagtap@arm.com // power (mW) = ----------- * ---------- 228512266Sradhika.jagtap@arm.com // time (tick) tick_frequency 228612266Sradhika.jagtap@arm.com averagePower = (totalEnergy.value() / 228712266Sradhika.jagtap@arm.com (curTick() - memory.lastStatsResetTick)) * 228812266Sradhika.jagtap@arm.com (SimClock::Frequency / 1000000000.0); 228910432SOmar.Naji@arm.com} 229010432SOmar.Naji@arm.com 229110432SOmar.Naji@arm.comvoid 229211677Swendy.elsasser@arm.comDRAMCtrl::Rank::computeStats() 229311677Swendy.elsasser@arm.com{ 229412266Sradhika.jagtap@arm.com DPRINTF(DRAM,"Computing stats due to a dump callback\n"); 229511677Swendy.elsasser@arm.com 229611677Swendy.elsasser@arm.com // Update the stats 229711677Swendy.elsasser@arm.com updatePowerStats(); 229811677Swendy.elsasser@arm.com 229911677Swendy.elsasser@arm.com // final update of power state times 230011677Swendy.elsasser@arm.com pwrStateTime[pwrState] += (curTick() - pwrStateTick); 230111677Swendy.elsasser@arm.com pwrStateTick = curTick(); 230211677Swendy.elsasser@arm.com 230311677Swendy.elsasser@arm.com} 230411677Swendy.elsasser@arm.com 230511677Swendy.elsasser@arm.comvoid 230612266Sradhika.jagtap@arm.comDRAMCtrl::Rank::resetStats() { 230712266Sradhika.jagtap@arm.com // The only way to clear the counters in DRAMPower is to call 230812266Sradhika.jagtap@arm.com // calcWindowEnergy function as that then calls clearCounters. The 230912266Sradhika.jagtap@arm.com // clearCounters method itself is private. 231012266Sradhika.jagtap@arm.com power.powerlib.calcWindowEnergy(divCeil(curTick(), memory.tCK) - 231112266Sradhika.jagtap@arm.com memory.timeStampOffset); 231212266Sradhika.jagtap@arm.com 231312266Sradhika.jagtap@arm.com} 231412266Sradhika.jagtap@arm.com 231512266Sradhika.jagtap@arm.comvoid 231610618SOmar.Naji@arm.comDRAMCtrl::Rank::regStats() 231710618SOmar.Naji@arm.com{ 231810618SOmar.Naji@arm.com pwrStateTime 231911678Swendy.elsasser@arm.com .init(6) 232010618SOmar.Naji@arm.com .name(name() + ".memoryStateTime") 232110618SOmar.Naji@arm.com .desc("Time in different power states"); 232210618SOmar.Naji@arm.com pwrStateTime.subname(0, "IDLE"); 232310618SOmar.Naji@arm.com pwrStateTime.subname(1, "REF"); 232411678Swendy.elsasser@arm.com pwrStateTime.subname(2, "SREF"); 232511678Swendy.elsasser@arm.com pwrStateTime.subname(3, "PRE_PDN"); 232611678Swendy.elsasser@arm.com pwrStateTime.subname(4, "ACT"); 232711678Swendy.elsasser@arm.com pwrStateTime.subname(5, "ACT_PDN"); 232810618SOmar.Naji@arm.com 232910618SOmar.Naji@arm.com actEnergy 233010618SOmar.Naji@arm.com .name(name() + ".actEnergy") 233110618SOmar.Naji@arm.com .desc("Energy for activate commands per rank (pJ)"); 233210618SOmar.Naji@arm.com 233310618SOmar.Naji@arm.com preEnergy 233410618SOmar.Naji@arm.com .name(name() + ".preEnergy") 233510618SOmar.Naji@arm.com .desc("Energy for precharge commands per rank (pJ)"); 233610618SOmar.Naji@arm.com 233710618SOmar.Naji@arm.com readEnergy 233810618SOmar.Naji@arm.com .name(name() + ".readEnergy") 233910618SOmar.Naji@arm.com .desc("Energy for read commands per rank (pJ)"); 234010618SOmar.Naji@arm.com 234110618SOmar.Naji@arm.com writeEnergy 234210618SOmar.Naji@arm.com .name(name() + ".writeEnergy") 234310618SOmar.Naji@arm.com .desc("Energy for write commands per rank (pJ)"); 234410618SOmar.Naji@arm.com 234510618SOmar.Naji@arm.com refreshEnergy 234610618SOmar.Naji@arm.com .name(name() + ".refreshEnergy") 234710618SOmar.Naji@arm.com .desc("Energy for refresh commands per rank (pJ)"); 234810618SOmar.Naji@arm.com 234910618SOmar.Naji@arm.com actBackEnergy 235010618SOmar.Naji@arm.com .name(name() + ".actBackEnergy") 235110618SOmar.Naji@arm.com .desc("Energy for active background per rank (pJ)"); 235210618SOmar.Naji@arm.com 235310618SOmar.Naji@arm.com preBackEnergy 235410618SOmar.Naji@arm.com .name(name() + ".preBackEnergy") 235510618SOmar.Naji@arm.com .desc("Energy for precharge background per rank (pJ)"); 235610618SOmar.Naji@arm.com 235711678Swendy.elsasser@arm.com actPowerDownEnergy 235811678Swendy.elsasser@arm.com .name(name() + ".actPowerDownEnergy") 235911678Swendy.elsasser@arm.com .desc("Energy for active power-down per rank (pJ)"); 236011678Swendy.elsasser@arm.com 236111678Swendy.elsasser@arm.com prePowerDownEnergy 236211678Swendy.elsasser@arm.com .name(name() + ".prePowerDownEnergy") 236311678Swendy.elsasser@arm.com .desc("Energy for precharge power-down per rank (pJ)"); 236411678Swendy.elsasser@arm.com 236511678Swendy.elsasser@arm.com selfRefreshEnergy 236611678Swendy.elsasser@arm.com .name(name() + ".selfRefreshEnergy") 236711678Swendy.elsasser@arm.com .desc("Energy for self refresh per rank (pJ)"); 236811678Swendy.elsasser@arm.com 236910618SOmar.Naji@arm.com totalEnergy 237010618SOmar.Naji@arm.com .name(name() + ".totalEnergy") 237110618SOmar.Naji@arm.com .desc("Total energy per rank (pJ)"); 237210618SOmar.Naji@arm.com 237310618SOmar.Naji@arm.com averagePower 237410618SOmar.Naji@arm.com .name(name() + ".averagePower") 237510618SOmar.Naji@arm.com .desc("Core power per rank (mW)"); 237611677Swendy.elsasser@arm.com 237711678Swendy.elsasser@arm.com totalIdleTime 237811678Swendy.elsasser@arm.com .name(name() + ".totalIdleTime") 237911678Swendy.elsasser@arm.com .desc("Total Idle time Per DRAM Rank"); 238011678Swendy.elsasser@arm.com 238112637Sodanrc@yahoo.com.br Stats::registerDumpCallback(new RankDumpCallback(this)); 238212637Sodanrc@yahoo.com.br Stats::registerResetCallback(new RankResetCallback(this)); 238310618SOmar.Naji@arm.com} 238410618SOmar.Naji@arm.comvoid 238510146Sandreas.hansson@arm.comDRAMCtrl::regStats() 23869243SN/A{ 23879243SN/A using namespace Stats; 23889243SN/A 23899243SN/A AbstractMemory::regStats(); 23909243SN/A 239110618SOmar.Naji@arm.com for (auto r : ranks) { 239210618SOmar.Naji@arm.com r->regStats(); 239310618SOmar.Naji@arm.com } 239410618SOmar.Naji@arm.com 239512266Sradhika.jagtap@arm.com registerResetCallback(new MemResetCallback(this)); 239612266Sradhika.jagtap@arm.com 23979243SN/A readReqs 23989243SN/A .name(name() + ".readReqs") 23999977SN/A .desc("Number of read requests accepted"); 24009243SN/A 24019243SN/A writeReqs 24029243SN/A .name(name() + ".writeReqs") 24039977SN/A .desc("Number of write requests accepted"); 24049831SN/A 24059831SN/A readBursts 24069831SN/A .name(name() + ".readBursts") 24079977SN/A .desc("Number of DRAM read bursts, " 24089977SN/A "including those serviced by the write queue"); 24099831SN/A 24109831SN/A writeBursts 24119831SN/A .name(name() + ".writeBursts") 24129977SN/A .desc("Number of DRAM write bursts, " 24139977SN/A "including those merged in the write queue"); 24149243SN/A 24159243SN/A servicedByWrQ 24169243SN/A .name(name() + ".servicedByWrQ") 24179977SN/A .desc("Number of DRAM read bursts serviced by the write queue"); 24189977SN/A 24199977SN/A mergedWrBursts 24209977SN/A .name(name() + ".mergedWrBursts") 24219977SN/A .desc("Number of DRAM write bursts merged with an existing one"); 24229243SN/A 24239243SN/A neitherReadNorWrite 24249977SN/A .name(name() + ".neitherReadNorWriteReqs") 24259977SN/A .desc("Number of requests that are neither read nor write"); 24269243SN/A 24279977SN/A perBankRdBursts 24289243SN/A .init(banksPerRank * ranksPerChannel) 24299977SN/A .name(name() + ".perBankRdBursts") 24309977SN/A .desc("Per bank write bursts"); 24319243SN/A 24329977SN/A perBankWrBursts 24339243SN/A .init(banksPerRank * ranksPerChannel) 24349977SN/A .name(name() + ".perBankWrBursts") 24359977SN/A .desc("Per bank write bursts"); 24369243SN/A 24379243SN/A avgRdQLen 24389243SN/A .name(name() + ".avgRdQLen") 24399977SN/A .desc("Average read queue length when enqueuing") 24409243SN/A .precision(2); 24419243SN/A 24429243SN/A avgWrQLen 24439243SN/A .name(name() + ".avgWrQLen") 24449977SN/A .desc("Average write queue length when enqueuing") 24459243SN/A .precision(2); 24469243SN/A 24479243SN/A totQLat 24489243SN/A .name(name() + ".totQLat") 24499977SN/A .desc("Total ticks spent queuing"); 24509243SN/A 24519243SN/A totBusLat 24529243SN/A .name(name() + ".totBusLat") 24539977SN/A .desc("Total ticks spent in databus transfers"); 24549243SN/A 24559243SN/A totMemAccLat 24569243SN/A .name(name() + ".totMemAccLat") 24579977SN/A .desc("Total ticks spent from burst creation until serviced " 24589977SN/A "by the DRAM"); 24599243SN/A 24609243SN/A avgQLat 24619243SN/A .name(name() + ".avgQLat") 24629977SN/A .desc("Average queueing delay per DRAM burst") 24639243SN/A .precision(2); 24649243SN/A 24659831SN/A avgQLat = totQLat / (readBursts - servicedByWrQ); 24669243SN/A 24679243SN/A avgBusLat 24689243SN/A .name(name() + ".avgBusLat") 24699977SN/A .desc("Average bus latency per DRAM burst") 24709243SN/A .precision(2); 24719243SN/A 24729831SN/A avgBusLat = totBusLat / (readBursts - servicedByWrQ); 24739243SN/A 24749243SN/A avgMemAccLat 24759243SN/A .name(name() + ".avgMemAccLat") 24769977SN/A .desc("Average memory access latency per DRAM burst") 24779243SN/A .precision(2); 24789243SN/A 24799831SN/A avgMemAccLat = totMemAccLat / (readBursts - servicedByWrQ); 24809243SN/A 24819243SN/A numRdRetry 24829243SN/A .name(name() + ".numRdRetry") 24839977SN/A .desc("Number of times read queue was full causing retry"); 24849243SN/A 24859243SN/A numWrRetry 24869243SN/A .name(name() + ".numWrRetry") 24879977SN/A .desc("Number of times write queue was full causing retry"); 24889243SN/A 24899243SN/A readRowHits 24909243SN/A .name(name() + ".readRowHits") 24919243SN/A .desc("Number of row buffer hits during reads"); 24929243SN/A 24939243SN/A writeRowHits 24949243SN/A .name(name() + ".writeRowHits") 24959243SN/A .desc("Number of row buffer hits during writes"); 24969243SN/A 24979243SN/A readRowHitRate 24989243SN/A .name(name() + ".readRowHitRate") 24999243SN/A .desc("Row buffer hit rate for reads") 25009243SN/A .precision(2); 25019243SN/A 25029831SN/A readRowHitRate = (readRowHits / (readBursts - servicedByWrQ)) * 100; 25039243SN/A 25049243SN/A writeRowHitRate 25059243SN/A .name(name() + ".writeRowHitRate") 25069243SN/A .desc("Row buffer hit rate for writes") 25079243SN/A .precision(2); 25089243SN/A 25099977SN/A writeRowHitRate = (writeRowHits / (writeBursts - mergedWrBursts)) * 100; 25109243SN/A 25119243SN/A readPktSize 25129831SN/A .init(ceilLog2(burstSize) + 1) 25139243SN/A .name(name() + ".readPktSize") 25149977SN/A .desc("Read request sizes (log2)"); 25159243SN/A 25169243SN/A writePktSize 25179831SN/A .init(ceilLog2(burstSize) + 1) 25189243SN/A .name(name() + ".writePktSize") 25199977SN/A .desc("Write request sizes (log2)"); 25209243SN/A 25219243SN/A rdQLenPdf 25229567SN/A .init(readBufferSize) 25239243SN/A .name(name() + ".rdQLenPdf") 25249243SN/A .desc("What read queue length does an incoming req see"); 25259243SN/A 25269243SN/A wrQLenPdf 25279567SN/A .init(writeBufferSize) 25289243SN/A .name(name() + ".wrQLenPdf") 25299243SN/A .desc("What write queue length does an incoming req see"); 25309243SN/A 25319727SN/A bytesPerActivate 253210141SN/A .init(maxAccessesPerRow) 25339727SN/A .name(name() + ".bytesPerActivate") 25349727SN/A .desc("Bytes accessed per row activation") 25359727SN/A .flags(nozero); 25369243SN/A 253710147Sandreas.hansson@arm.com rdPerTurnAround 253810147Sandreas.hansson@arm.com .init(readBufferSize) 253910147Sandreas.hansson@arm.com .name(name() + ".rdPerTurnAround") 254010147Sandreas.hansson@arm.com .desc("Reads before turning the bus around for writes") 254110147Sandreas.hansson@arm.com .flags(nozero); 254210147Sandreas.hansson@arm.com 254310147Sandreas.hansson@arm.com wrPerTurnAround 254410147Sandreas.hansson@arm.com .init(writeBufferSize) 254510147Sandreas.hansson@arm.com .name(name() + ".wrPerTurnAround") 254610147Sandreas.hansson@arm.com .desc("Writes before turning the bus around for reads") 254710147Sandreas.hansson@arm.com .flags(nozero); 254810147Sandreas.hansson@arm.com 25499975SN/A bytesReadDRAM 25509975SN/A .name(name() + ".bytesReadDRAM") 25519975SN/A .desc("Total number of bytes read from DRAM"); 25529975SN/A 25539975SN/A bytesReadWrQ 25549975SN/A .name(name() + ".bytesReadWrQ") 25559975SN/A .desc("Total number of bytes read from write queue"); 25569243SN/A 25579243SN/A bytesWritten 25589243SN/A .name(name() + ".bytesWritten") 25599977SN/A .desc("Total number of bytes written to DRAM"); 25609243SN/A 25619977SN/A bytesReadSys 25629977SN/A .name(name() + ".bytesReadSys") 25639977SN/A .desc("Total read bytes from the system interface side"); 25649243SN/A 25659977SN/A bytesWrittenSys 25669977SN/A .name(name() + ".bytesWrittenSys") 25679977SN/A .desc("Total written bytes from the system interface side"); 25689243SN/A 25699243SN/A avgRdBW 25709243SN/A .name(name() + ".avgRdBW") 25719977SN/A .desc("Average DRAM read bandwidth in MiByte/s") 25729243SN/A .precision(2); 25739243SN/A 25749977SN/A avgRdBW = (bytesReadDRAM / 1000000) / simSeconds; 25759243SN/A 25769243SN/A avgWrBW 25779243SN/A .name(name() + ".avgWrBW") 25789977SN/A .desc("Average achieved write bandwidth in MiByte/s") 25799243SN/A .precision(2); 25809243SN/A 25819243SN/A avgWrBW = (bytesWritten / 1000000) / simSeconds; 25829243SN/A 25839977SN/A avgRdBWSys 25849977SN/A .name(name() + ".avgRdBWSys") 25859977SN/A .desc("Average system read bandwidth in MiByte/s") 25869243SN/A .precision(2); 25879243SN/A 25889977SN/A avgRdBWSys = (bytesReadSys / 1000000) / simSeconds; 25899243SN/A 25909977SN/A avgWrBWSys 25919977SN/A .name(name() + ".avgWrBWSys") 25929977SN/A .desc("Average system write bandwidth in MiByte/s") 25939243SN/A .precision(2); 25949243SN/A 25959977SN/A avgWrBWSys = (bytesWrittenSys / 1000000) / simSeconds; 25969243SN/A 25979243SN/A peakBW 25989243SN/A .name(name() + ".peakBW") 25999977SN/A .desc("Theoretical peak bandwidth in MiByte/s") 26009243SN/A .precision(2); 26019243SN/A 26029831SN/A peakBW = (SimClock::Frequency / tBURST) * burstSize / 1000000; 26039243SN/A 26049243SN/A busUtil 26059243SN/A .name(name() + ".busUtil") 26069243SN/A .desc("Data bus utilization in percentage") 26079243SN/A .precision(2); 26089243SN/A busUtil = (avgRdBW + avgWrBW) / peakBW * 100; 26099243SN/A 26109243SN/A totGap 26119243SN/A .name(name() + ".totGap") 26129243SN/A .desc("Total gap between requests"); 26139243SN/A 26149243SN/A avgGap 26159243SN/A .name(name() + ".avgGap") 26169243SN/A .desc("Average gap between requests") 26179243SN/A .precision(2); 26189243SN/A 26199243SN/A avgGap = totGap / (readReqs + writeReqs); 26209975SN/A 26219975SN/A // Stats for DRAM Power calculation based on Micron datasheet 26229975SN/A busUtilRead 26239975SN/A .name(name() + ".busUtilRead") 26249975SN/A .desc("Data bus utilization in percentage for reads") 26259975SN/A .precision(2); 26269975SN/A 26279975SN/A busUtilRead = avgRdBW / peakBW * 100; 26289975SN/A 26299975SN/A busUtilWrite 26309975SN/A .name(name() + ".busUtilWrite") 26319975SN/A .desc("Data bus utilization in percentage for writes") 26329975SN/A .precision(2); 26339975SN/A 26349975SN/A busUtilWrite = avgWrBW / peakBW * 100; 26359975SN/A 26369975SN/A pageHitRate 26379975SN/A .name(name() + ".pageHitRate") 26389975SN/A .desc("Row buffer hit rate, read and write combined") 26399975SN/A .precision(2); 26409975SN/A 26419977SN/A pageHitRate = (writeRowHits + readRowHits) / 26429977SN/A (writeBursts - mergedWrBursts + readBursts - servicedByWrQ) * 100; 26439243SN/A} 26449243SN/A 26459243SN/Avoid 264610146Sandreas.hansson@arm.comDRAMCtrl::recvFunctional(PacketPtr pkt) 26479243SN/A{ 26489243SN/A // rely on the abstract memory 26499243SN/A functionalAccess(pkt); 26509243SN/A} 26519243SN/A 26529294SN/ABaseSlavePort& 265310146Sandreas.hansson@arm.comDRAMCtrl::getSlavePort(const string &if_name, PortID idx) 26549243SN/A{ 26559243SN/A if (if_name != "port") { 26569243SN/A return MemObject::getSlavePort(if_name, idx); 26579243SN/A } else { 26589243SN/A return port; 26599243SN/A } 26609243SN/A} 26619243SN/A 266210913Sandreas.sandberg@arm.comDrainState 266310913Sandreas.sandberg@arm.comDRAMCtrl::drain() 26649243SN/A{ 26659243SN/A // if there is anything in any of our internal queues, keep track 26669243SN/A // of that as well 266711676Swendy.elsasser@arm.com if (!(writeQueue.empty() && readQueue.empty() && respQueue.empty() && 266811676Swendy.elsasser@arm.com allRanksDrained())) { 266911676Swendy.elsasser@arm.com 26709352SN/A DPRINTF(Drain, "DRAM controller not drained, write: %d, read: %d," 26719567SN/A " resp: %d\n", writeQueue.size(), readQueue.size(), 26729567SN/A respQueue.size()); 267310206Sandreas.hansson@arm.com 267411678Swendy.elsasser@arm.com // the only queue that is not drained automatically over time 267510206Sandreas.hansson@arm.com // is the write queue, thus kick things into action if needed 267610206Sandreas.hansson@arm.com if (!writeQueue.empty() && !nextReqEvent.scheduled()) { 267710206Sandreas.hansson@arm.com schedule(nextReqEvent, curTick()); 267810206Sandreas.hansson@arm.com } 267911678Swendy.elsasser@arm.com 268011678Swendy.elsasser@arm.com // also need to kick off events to exit self-refresh 268111678Swendy.elsasser@arm.com for (auto r : ranks) { 268211678Swendy.elsasser@arm.com // force self-refresh exit, which in turn will issue auto-refresh 268311678Swendy.elsasser@arm.com if (r->pwrState == PWR_SREF) { 268411678Swendy.elsasser@arm.com DPRINTF(DRAM,"Rank%d: Forcing self-refresh wakeup in drain\n", 268511678Swendy.elsasser@arm.com r->rank); 268611678Swendy.elsasser@arm.com r->scheduleWakeUpEvent(tXS); 268711678Swendy.elsasser@arm.com } 268811678Swendy.elsasser@arm.com } 268911678Swendy.elsasser@arm.com 269010913Sandreas.sandberg@arm.com return DrainState::Draining; 269110912Sandreas.sandberg@arm.com } else { 269210913Sandreas.sandberg@arm.com return DrainState::Drained; 26939243SN/A } 26949243SN/A} 26959243SN/A 269611676Swendy.elsasser@arm.combool 269711676Swendy.elsasser@arm.comDRAMCtrl::allRanksDrained() const 269811676Swendy.elsasser@arm.com{ 269911676Swendy.elsasser@arm.com // true until proven false 270011676Swendy.elsasser@arm.com bool all_ranks_drained = true; 270111676Swendy.elsasser@arm.com for (auto r : ranks) { 270212266Sradhika.jagtap@arm.com // then verify that the power state is IDLE ensuring all banks are 270312266Sradhika.jagtap@arm.com // closed and rank is not in a low power state. Also verify that rank 270412266Sradhika.jagtap@arm.com // is idle from a refresh point of view. 270512266Sradhika.jagtap@arm.com all_ranks_drained = r->inPwrIdleState() && r->inRefIdleState() && 270612266Sradhika.jagtap@arm.com all_ranks_drained; 270711676Swendy.elsasser@arm.com } 270811676Swendy.elsasser@arm.com return all_ranks_drained; 270911676Swendy.elsasser@arm.com} 271011676Swendy.elsasser@arm.com 271110619Sandreas.hansson@arm.comvoid 271210619Sandreas.hansson@arm.comDRAMCtrl::drainResume() 271310619Sandreas.hansson@arm.com{ 271410619Sandreas.hansson@arm.com if (!isTimingMode && system()->isTimingMode()) { 271510619Sandreas.hansson@arm.com // if we switched to timing mode, kick things into action, 271610619Sandreas.hansson@arm.com // and behave as if we restored from a checkpoint 271710619Sandreas.hansson@arm.com startup(); 271810619Sandreas.hansson@arm.com } else if (isTimingMode && !system()->isTimingMode()) { 271910619Sandreas.hansson@arm.com // if we switch from timing mode, stop the refresh events to 272010619Sandreas.hansson@arm.com // not cause issues with KVM 272110619Sandreas.hansson@arm.com for (auto r : ranks) { 272210619Sandreas.hansson@arm.com r->suspend(); 272310619Sandreas.hansson@arm.com } 272410619Sandreas.hansson@arm.com } 272510619Sandreas.hansson@arm.com 272610619Sandreas.hansson@arm.com // update the mode 272710619Sandreas.hansson@arm.com isTimingMode = system()->isTimingMode(); 272810619Sandreas.hansson@arm.com} 272910619Sandreas.hansson@arm.com 273010146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::MemoryPort(const std::string& name, DRAMCtrl& _memory) 27319243SN/A : QueuedSlavePort(name, &_memory, queue), queue(_memory, *this), 27329243SN/A memory(_memory) 27339243SN/A{ } 27349243SN/A 27359243SN/AAddrRangeList 273610146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::getAddrRanges() const 27379243SN/A{ 27389243SN/A AddrRangeList ranges; 27399243SN/A ranges.push_back(memory.getAddrRange()); 27409243SN/A return ranges; 27419243SN/A} 27429243SN/A 27439243SN/Avoid 274410146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvFunctional(PacketPtr pkt) 27459243SN/A{ 27469243SN/A pkt->pushLabel(memory.name()); 27479243SN/A 27489243SN/A if (!queue.checkFunctional(pkt)) { 27499243SN/A // Default implementation of SimpleTimingPort::recvFunctional() 27509243SN/A // calls recvAtomic() and throws away the latency; we can save a 27519243SN/A // little here by just not calculating the latency. 27529243SN/A memory.recvFunctional(pkt); 27539243SN/A } 27549243SN/A 27559243SN/A pkt->popLabel(); 27569243SN/A} 27579243SN/A 27589243SN/ATick 275910146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvAtomic(PacketPtr pkt) 27609243SN/A{ 27619243SN/A return memory.recvAtomic(pkt); 27629243SN/A} 27639243SN/A 27649243SN/Abool 276510146Sandreas.hansson@arm.comDRAMCtrl::MemoryPort::recvTimingReq(PacketPtr pkt) 27669243SN/A{ 27679243SN/A // pass it to the memory controller 27689243SN/A return memory.recvTimingReq(pkt); 27699243SN/A} 27709243SN/A 277110146Sandreas.hansson@arm.comDRAMCtrl* 277210146Sandreas.hansson@arm.comDRAMCtrlParams::create() 27739243SN/A{ 277410146Sandreas.hansson@arm.com return new DRAMCtrl(this); 27759243SN/A} 2776