mshr.cc revision 4666
1360SN/A/* 21458SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 3360SN/A * All rights reserved. 4360SN/A * 5360SN/A * Redistribution and use in source and binary forms, with or without 6360SN/A * modification, are permitted provided that the following conditions are 7360SN/A * met: redistributions of source code must retain the above copyright 8360SN/A * notice, this list of conditions and the following disclaimer; 9360SN/A * redistributions in binary form must reproduce the above copyright 10360SN/A * notice, this list of conditions and the following disclaimer in the 11360SN/A * documentation and/or other materials provided with the distribution; 12360SN/A * neither the name of the copyright holders nor the names of its 13360SN/A * contributors may be used to endorse or promote products derived from 14360SN/A * this software without specific prior written permission. 15360SN/A * 16360SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17360SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18360SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19360SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20360SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21360SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22360SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23360SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24360SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25360SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26360SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Erik Hallnor 292665Ssaidi@eecs.umich.edu * Dave Greene 30360SN/A */ 31360SN/A 321354SN/A/** 331354SN/A * @file 34360SN/A * Miss Status and Handling Register (MSHR) definitions. 352764Sstever@eecs.umich.edu */ 362764Sstever@eecs.umich.edu 372064SN/A#include <assert.h> 38360SN/A#include <string> 39360SN/A#include <vector> 40360SN/A#include <algorithm> 41360SN/A 42360SN/A#include "mem/cache/miss/mshr.hh" 43360SN/A#include "sim/core.hh" // for curTick 441354SN/A#include "sim/host.hh" 45360SN/A#include "base/misc.hh" 461809SN/A#include "mem/cache/cache.hh" 471809SN/A 481809SN/Ausing namespace std; 493113Sgblack@eecs.umich.edu 503113Sgblack@eecs.umich.eduMSHR::MSHR() 511999SN/A{ 52360SN/A inService = false; 533113Sgblack@eecs.umich.edu ntargets = 0; 542474SN/A threadNum = -1; 55360SN/A} 562462SN/A 571354SN/Avoid 582474SN/AMSHR::allocate(Addr _addr, int _size, PacketPtr target, 592680Sktlim@umich.edu Tick when, Counter _order) 602474SN/A{ 612474SN/A addr = _addr; 621354SN/A size = _size; 63360SN/A readyTick = when; 64360SN/A order = _order; 65360SN/A assert(target); 66360SN/A isCacheFill = false; 67360SN/A needsExclusive = target->needsExclusive(); 68360SN/A _isUncacheable = target->req->isUncacheable(); 69360SN/A inService = false; 70360SN/A threadNum = 0; 71378SN/A ntargets = 1; 721450SN/A // Don't know of a case where we would allocate a new MSHR for a 733114Sgblack@eecs.umich.edu // snoop (mem-side request), so set cpuSide to true here. 74360SN/A targets.push_back(Target(target, when, _order, true)); 75360SN/A assert(deferredTargets.empty()); 76360SN/A deferredNeedsExclusive = false; 77360SN/A pendingInvalidate = false; 78360SN/A} 79360SN/A 80360SN/Avoid 81360SN/AMSHR::deallocate() 82360SN/A{ 832680Sktlim@umich.edu assert(targets.empty()); 84360SN/A assert(deferredTargets.empty()); 85360SN/A assert(ntargets == 0); 86360SN/A inService = false; 87360SN/A //allocIter = NULL; 88360SN/A //readyIter = NULL; 89360SN/A} 90360SN/A 91360SN/A/* 92360SN/A * Adds a target to an MSHR 93360SN/A */ 94360SN/Avoid 953114Sgblack@eecs.umich.eduMSHR::allocateTarget(PacketPtr target, Tick when, Counter _order) 96360SN/A{ 97360SN/A if (inService) { 98360SN/A if (!deferredTargets.empty() || pendingInvalidate || 99360SN/A (!needsExclusive && target->needsExclusive())) { 100360SN/A // need to put on deferred list 101360SN/A deferredTargets.push_back(Target(target, when, _order, true)); 102360SN/A if (target->needsExclusive()) { 103360SN/A deferredNeedsExclusive = true; 104360SN/A } 105360SN/A } else { 106360SN/A // still OK to append to outstanding request 107360SN/A targets.push_back(Target(target, when, _order, true)); 108360SN/A } 109360SN/A } else { 110360SN/A if (target->needsExclusive()) { 111360SN/A needsExclusive = true; 112360SN/A } 113360SN/A 114360SN/A targets.push_back(Target(target, when, _order, true)); 115360SN/A } 116360SN/A 1172400SN/A ++ntargets; 118360SN/A} 1192461SN/A 120360SN/Avoid 121360SN/AMSHR::allocateSnoopTarget(PacketPtr target, Tick when, Counter _order) 122360SN/A{ 123360SN/A assert(inService); // don't bother to call otherwise 124360SN/A 125360SN/A if (pendingInvalidate) { 1262400SN/A // a prior snoop has already appended an invalidation, so 127360SN/A // logically we don't have the block anymore... 1282461SN/A return; 129360SN/A } 130360SN/A 131360SN/A if (needsExclusive) { 132360SN/A // We're awaiting an exclusive copy, so ownership is pending. 133360SN/A // It's up to us to respond once the data arrives. 134360SN/A target->assertMemInhibit(); 135360SN/A } else if (target->needsExclusive()) { 136360SN/A // This transaction will take away our pending copy 137360SN/A pendingInvalidate = true; 138360SN/A } else { 139360SN/A // If we're not going to supply data or perform an 140360SN/A // invalidation, we don't need to save this. 141360SN/A return; 142360SN/A } 143360SN/A 144360SN/A targets.push_back(Target(target, when, _order, false)); 145360SN/A ++ntargets; 146360SN/A} 147360SN/A 148360SN/A 149360SN/Abool 150360SN/AMSHR::promoteDeferredTargets() 151360SN/A{ 152360SN/A if (deferredTargets.empty()) { 153360SN/A return false; 154360SN/A } 155360SN/A 156360SN/A assert(targets.empty()); 157360SN/A targets = deferredTargets; 158360SN/A deferredTargets.clear(); 159360SN/A assert(targets.size() == ntargets); 160360SN/A 161502SN/A needsExclusive = deferredNeedsExclusive; 162360SN/A pendingInvalidate = false; 163502SN/A deferredNeedsExclusive = false; 164360SN/A order = targets.front().order; 165360SN/A readyTick = std::max(curTick, targets.front().time); 166360SN/A 167360SN/A return true; 168360SN/A} 169360SN/A 170360SN/A 171360SN/Avoid 172360SN/AMSHR::dump() 173360SN/A{ 174360SN/A ccprintf(cerr, 175378SN/A "inService: %d thread: %d\n" 1761706SN/A "Addr: %x ntargets %d\n" 1773114Sgblack@eecs.umich.edu "Targets:\n", 178378SN/A inService, threadNum, addr, ntargets); 179378SN/A 180378SN/A TargetListIterator tar_it = targets.begin(); 181378SN/A for (int i = 0; i < ntargets; i++) { 182378SN/A assert(tar_it != targets.end()); 1831706SN/A 1843114Sgblack@eecs.umich.edu ccprintf(cerr, "\t%d: Addr: %x cmd: %s\n", 185360SN/A i, tar_it->pkt->getAddr(), tar_it->pkt->cmdString()); 186378SN/A 1871706SN/A tar_it++; 1883114Sgblack@eecs.umich.edu } 189378SN/A ccprintf(cerr, "\n"); 190378SN/A} 1911706SN/A 1923114Sgblack@eecs.umich.eduMSHR::~MSHR() 193378SN/A{ 194378SN/A} 1951706SN/A