mshr.cc revision 4665
1803SN/A/*
21363SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
3803SN/A * All rights reserved.
4803SN/A *
5803SN/A * Redistribution and use in source and binary forms, with or without
6803SN/A * modification, are permitted provided that the following conditions are
7803SN/A * met: redistributions of source code must retain the above copyright
8803SN/A * notice, this list of conditions and the following disclaimer;
9803SN/A * redistributions in binary form must reproduce the above copyright
10803SN/A * notice, this list of conditions and the following disclaimer in the
11803SN/A * documentation and/or other materials provided with the distribution;
12803SN/A * neither the name of the copyright holders nor the names of its
13803SN/A * contributors may be used to endorse or promote products derived from
14803SN/A * this software without specific prior written permission.
15803SN/A *
16803SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17803SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18803SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19803SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20803SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21803SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22803SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23803SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24803SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25803SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26803SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665SN/A *
282665SN/A * Authors: Erik Hallnor
292665SN/A *          Dave Greene
302665SN/A */
31803SN/A
32768SN/A/**
331730SN/A * @file
34773SN/A * Miss Status and Handling Register (MSHR) definitions.
35768SN/A */
36768SN/A
37773SN/A#include <assert.h>
38773SN/A#include <string>
39768SN/A#include <vector>
40768SN/A
41768SN/A#include "mem/cache/miss/mshr.hh"
42768SN/A#include "sim/core.hh" // for curTick
434762Snate@binkert.org#include "sim/host.hh"
44768SN/A#include "base/misc.hh"
456658Snate@binkert.org#include "mem/cache/cache.hh"
468232Snate@binkert.org
478229Snate@binkert.orgusing namespace std;
483540Sgblack@eecs.umich.edu
493540Sgblack@eecs.umich.eduMSHR::MSHR()
503540Sgblack@eecs.umich.edu{
518229Snate@binkert.org    inService = false;
523348SN/A    ntargets = 0;
533348SN/A    threadNum = -1;
542542SN/A}
552542SN/A
56768SN/Avoid
57768SN/AMSHR::allocate(Addr _addr, int _size, PacketPtr target)
582107SN/A{
592107SN/A    addr = _addr;
60773SN/A    size = _size;
615606Snate@binkert.org    assert(target);
625606Snate@binkert.org    isCacheFill = false;
635606Snate@binkert.org    needsExclusive = target->needsExclusive();
641817SN/A    _isUncacheable = target->req->isUncacheable();
65772SN/A    inService = false;
66772SN/A    threadNum = 0;
674762Snate@binkert.org    ntargets = 1;
685606Snate@binkert.org    // Don't know of a case where we would allocate a new MSHR for a
695606Snate@binkert.org    // snoop (mem0-side request), so set cpuSide to true here.
70768SN/A    targets.push_back(Target(target, true));
713846Shsul@eecs.umich.edu    assert(deferredTargets.empty());
72909SN/A    deferredNeedsExclusive = false;
73803SN/A    pendingInvalidate = false;
74803SN/A}
75803SN/A
76771SN/Avoid
77777SN/AMSHR::deallocate()
78777SN/A{
79773SN/A    assert(targets.empty());
80773SN/A    assert(deferredTargets.empty());
811634SN/A    assert(ntargets == 0);
821634SN/A    inService = false;
831634SN/A    //allocIter = NULL;
847064Snate@binkert.org    //readyIter = NULL;
851634SN/A}
861634SN/A
872542SN/A/*
883349SN/A * Adds a target to an MSHR
89768SN/A */
902641SN/Avoid
91768SN/AMSHR::allocateTarget(PacketPtr target)
922641SN/A{
93865SN/A    if (inService) {
942641SN/A        if (!deferredTargets.empty() || pendingInvalidate ||
952641SN/A            (!needsExclusive && target->needsExclusive())) {
96771SN/A            // need to put on deferred list
972630SN/A            deferredTargets.push_back(Target(target, true));
982539SN/A            if (target->needsExclusive()) {
992641SN/A                deferredNeedsExclusive = true;
100803SN/A            }
1011817SN/A        } else {
1021817SN/A            // still OK to append to outstanding request
1032630SN/A            targets.push_back(Target(target, true));
1042539SN/A        }
1051817SN/A    } else {
1062630SN/A        if (target->needsExclusive()) {
1072539SN/A            needsExclusive = true;
108865SN/A        }
109865SN/A
110865SN/A        targets.push_back(Target(target, true));
111865SN/A    }
1122630SN/A
1132539SN/A    ++ntargets;
114865SN/A}
115865SN/A
1162630SN/Avoid
1172539SN/AMSHR::allocateSnoopTarget(PacketPtr target)
1181817SN/A{
1195635Sgblack@eecs.umich.edu    assert(inService); // don't bother to call otherwise
1202542SN/A
1211817SN/A    if (pendingInvalidate) {
1225635Sgblack@eecs.umich.edu        // a prior snoop has already appended an invalidation, so
1232542SN/A        // logically we don't have the block anymore...
1241817SN/A        return;
1255635Sgblack@eecs.umich.edu    }
1262539SN/A
127803SN/A    if (needsExclusive) {
1285392Sgblack@eecs.umich.edu        // We're awaiting an exclusive copy, so ownership is pending.
1292539SN/A        // It's up to us to respond once the data arrives.
1301817SN/A        target->assertMemInhibit();
1315635Sgblack@eecs.umich.edu    } else if (target->needsExclusive()) {
1322630SN/A        // This transaction will take away our pending copy
1331817SN/A        pendingInvalidate = true;
1342630SN/A    } else {
1352539SN/A        // If we're not going to supply data or perform an
136803SN/A        // invalidation, we don't need to save this.
1372641SN/A        return;
138803SN/A    }
1392641SN/A
1402539SN/A    targets.push_back(Target(target, false));
1412630SN/A    ++ntargets;
1422539SN/A}
1432539SN/A
1442641SN/A
1452539SN/Abool
1462641SN/AMSHR::promoteDeferredTargets()
147771SN/A{
1484870Sstever@eecs.umich.edu    if (deferredTargets.empty()) {
1492539SN/A        return false;
150768SN/A    }
151768SN/A
1522539SN/A    assert(targets.empty());
1533349SN/A    targets = deferredTargets;
154768SN/A    deferredTargets.clear();
1552641SN/A    assert(targets.size() == ntargets);
1562641SN/A
157779SN/A    needsExclusive = deferredNeedsExclusive;
158779SN/A    pendingInvalidate = false;
1592641SN/A    deferredNeedsExclusive = false;
160768SN/A
1612641SN/A    return true;
162769SN/A}
1632539SN/A
1642539SN/A
1652630SN/Avoid
1662539SN/AMSHR::dump()
1672539SN/A{
1682539SN/A    ccprintf(cerr,
1692539SN/A             "inService: %d thread: %d\n"
170803SN/A             "Addr: %x ntargets %d\n"
1712539SN/A             "Targets:\n",
1722539SN/A             inService, threadNum, addr, ntargets);
1732539SN/A
1742539SN/A    TargetListIterator tar_it = targets.begin();
1752539SN/A    for (int i = 0; i < ntargets; i++) {
1762539SN/A        assert(tar_it != targets.end());
1772539SN/A
1782630SN/A        ccprintf(cerr, "\t%d: Addr: %x cmd: %s\n",
1792539SN/A                 i, tar_it->pkt->getAddr(), tar_it->pkt->cmdString());
1802539SN/A
1812539SN/A        tar_it++;
1822539SN/A    }
1832630SN/A    ccprintf(cerr, "\n");
1842539SN/A}
1852539SN/A
1862539SN/AMSHR::~MSHR()
1872539SN/A{
1882630SN/A}
1892539SN/A