mshr.cc revision 4665
12810SN/A/*
212501Snikos.nikoleris@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan
39663Suri.wiener@arm.com * All rights reserved.
49663Suri.wiener@arm.com *
59663Suri.wiener@arm.com * Redistribution and use in source and binary forms, with or without
69663Suri.wiener@arm.com * modification, are permitted provided that the following conditions are
79663Suri.wiener@arm.com * met: redistributions of source code must retain the above copyright
89663Suri.wiener@arm.com * notice, this list of conditions and the following disclaimer;
99663Suri.wiener@arm.com * redistributions in binary form must reproduce the above copyright
109663Suri.wiener@arm.com * notice, this list of conditions and the following disclaimer in the
119663Suri.wiener@arm.com * documentation and/or other materials provided with the distribution;
129663Suri.wiener@arm.com * neither the name of the copyright holders nor the names of its
139663Suri.wiener@arm.com * contributors may be used to endorse or promote products derived from
142810SN/A * this software without specific prior written permission.
157636Ssteve.reinhardt@amd.com *
162810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272810SN/A *
282810SN/A * Authors: Erik Hallnor
292810SN/A *          Dave Greene
302810SN/A */
312810SN/A
322810SN/A/**
332810SN/A * @file
342810SN/A * Miss Status and Handling Register (MSHR) definitions.
352810SN/A */
362810SN/A
372810SN/A#include <assert.h>
382810SN/A#include <string>
392810SN/A#include <vector>
402810SN/A
412810SN/A#include "mem/cache/miss/mshr.hh"
422810SN/A#include "sim/core.hh" // for curTick
432810SN/A#include "sim/host.hh"
442810SN/A#include "base/misc.hh"
452810SN/A#include "mem/cache/cache.hh"
462810SN/A
472810SN/Ausing namespace std;
482810SN/A
492810SN/AMSHR::MSHR()
5011486Snikos.nikoleris@arm.com{
5111486Snikos.nikoleris@arm.com    inService = false;
526216Snate@binkert.org    ntargets = 0;
532810SN/A    threadNum = -1;
542810SN/A}
5512334Sgabeblack@google.com
5612727Snikos.nikoleris@arm.comvoid
576216Snate@binkert.orgMSHR::allocate(Addr _addr, int _size, PacketPtr target)
588232Snate@binkert.org{
5912727Snikos.nikoleris@arm.com    addr = _addr;
6012727Snikos.nikoleris@arm.com    size = _size;
616216Snate@binkert.org    assert(target);
622810SN/A    isCacheFill = false;
6311375Sandreas.hansson@arm.com    needsExclusive = target->needsExclusive();
6411284Sandreas.hansson@arm.com    _isUncacheable = target->req->isUncacheable();
6510503SCurtis.Dunham@arm.com    inService = false;
6611741Snikos.nikoleris@arm.com    threadNum = 0;
672810SN/A    ntargets = 1;
682810SN/A    // Don't know of a case where we would allocate a new MSHR for a
692810SN/A    // snoop (mem0-side request), so set cpuSide to true here.
704903SN/A    targets.push_back(Target(target, true));
7112715Snikos.nikoleris@arm.com    assert(deferredTargets.empty());
7212715Snikos.nikoleris@arm.com    deferredNeedsExclusive = false;
734903SN/A    pendingInvalidate = false;
744903SN/A}
754903SN/A
7611740Snikos.nikoleris@arm.comvoid
7711741Snikos.nikoleris@arm.comMSHR::deallocate()
7811741Snikos.nikoleris@arm.com{
794903SN/A    assert(targets.empty());
805875Ssteve.reinhardt@amd.com    assert(deferredTargets.empty());
8111284Sandreas.hansson@arm.com    assert(ntargets == 0);
8211284Sandreas.hansson@arm.com    inService = false;
834903SN/A    //allocIter = NULL;
844903SN/A    //readyIter = NULL;
857669Ssteve.reinhardt@amd.com}
867669Ssteve.reinhardt@amd.com
877669Ssteve.reinhardt@amd.com/*
887669Ssteve.reinhardt@amd.com * Adds a target to an MSHR
894903SN/A */
904903SN/Avoid
9111741Snikos.nikoleris@arm.comMSHR::allocateTarget(PacketPtr target)
9211741Snikos.nikoleris@arm.com{
9311741Snikos.nikoleris@arm.com    if (inService) {
9411741Snikos.nikoleris@arm.com        if (!deferredTargets.empty() || pendingInvalidate ||
9512715Snikos.nikoleris@arm.com            (!needsExclusive && target->needsExclusive())) {
9612715Snikos.nikoleris@arm.com            // need to put on deferred list
9712715Snikos.nikoleris@arm.com            deferredTargets.push_back(Target(target, true));
9812715Snikos.nikoleris@arm.com            if (target->needsExclusive()) {
995318SN/A                deferredNeedsExclusive = true;
10011740Snikos.nikoleris@arm.com            }
1014908SN/A        } else {
10211740Snikos.nikoleris@arm.com            // still OK to append to outstanding request
10311740Snikos.nikoleris@arm.com            targets.push_back(Target(target, true));
10411740Snikos.nikoleris@arm.com        }
10511740Snikos.nikoleris@arm.com    } else {
10611740Snikos.nikoleris@arm.com        if (target->needsExclusive()) {
10711741Snikos.nikoleris@arm.com            needsExclusive = true;
10811740Snikos.nikoleris@arm.com        }
10911740Snikos.nikoleris@arm.com
11011740Snikos.nikoleris@arm.com        targets.push_back(Target(target, true));
11111740Snikos.nikoleris@arm.com    }
11211740Snikos.nikoleris@arm.com
11311741Snikos.nikoleris@arm.com    ++ntargets;
11411741Snikos.nikoleris@arm.com}
11511740Snikos.nikoleris@arm.com
11611741Snikos.nikoleris@arm.comvoid
1175318SN/AMSHR::allocateSnoopTarget(PacketPtr target)
1189543Ssascha.bischoff@arm.com{
1199543Ssascha.bischoff@arm.com    assert(inService); // don't bother to call otherwise
1209543Ssascha.bischoff@arm.com
1219543Ssascha.bischoff@arm.com    if (pendingInvalidate) {
12211484Snikos.nikoleris@arm.com        // a prior snoop has already appended an invalidation, so
1234908SN/A        // logically we don't have the block anymore...
1244908SN/A        return;
12511083Sandreas.hansson@arm.com    }
12611083Sandreas.hansson@arm.com
12711083Sandreas.hansson@arm.com    if (needsExclusive) {
1284908SN/A        // We're awaiting an exclusive copy, so ownership is pending.
1294903SN/A        // It's up to us to respond once the data arrives.
1304903SN/A        target->assertMemInhibit();
13111741Snikos.nikoleris@arm.com    } else if (target->needsExclusive()) {
1324903SN/A        // This transaction will take away our pending copy
1334903SN/A        pendingInvalidate = true;
1344903SN/A    } else {
1357667Ssteve.reinhardt@amd.com        // If we're not going to supply data or perform an
1367667Ssteve.reinhardt@amd.com        // invalidation, we don't need to save this.
1377667Ssteve.reinhardt@amd.com        return;
13811286Sandreas.hansson@arm.com    }
13911286Sandreas.hansson@arm.com
14011286Sandreas.hansson@arm.com    targets.push_back(Target(target, false));
1417667Ssteve.reinhardt@amd.com    ++ntargets;
1427667Ssteve.reinhardt@amd.com}
1437667Ssteve.reinhardt@amd.com
1447667Ssteve.reinhardt@amd.com
1457667Ssteve.reinhardt@amd.combool
1467667Ssteve.reinhardt@amd.comMSHR::promoteDeferredTargets()
1477669Ssteve.reinhardt@amd.com{
1487669Ssteve.reinhardt@amd.com    if (deferredTargets.empty()) {
1497669Ssteve.reinhardt@amd.com        return false;
1507667Ssteve.reinhardt@amd.com    }
15111286Sandreas.hansson@arm.com
15211286Sandreas.hansson@arm.com    assert(targets.empty());
15311286Sandreas.hansson@arm.com    targets = deferredTargets;
15411286Sandreas.hansson@arm.com    deferredTargets.clear();
15511286Sandreas.hansson@arm.com    assert(targets.size() == ntargets);
15611286Sandreas.hansson@arm.com
15711286Sandreas.hansson@arm.com    needsExclusive = deferredNeedsExclusive;
15811286Sandreas.hansson@arm.com    pendingInvalidate = false;
15911286Sandreas.hansson@arm.com    deferredNeedsExclusive = false;
16011286Sandreas.hansson@arm.com
16111286Sandreas.hansson@arm.com    return true;
16211286Sandreas.hansson@arm.com}
16311286Sandreas.hansson@arm.com
1647667Ssteve.reinhardt@amd.com
1657667Ssteve.reinhardt@amd.comvoid
1667667Ssteve.reinhardt@amd.comMSHR::dump()
1674903SN/A{
1684903SN/A    ccprintf(cerr,
1694903SN/A             "inService: %d thread: %d\n"
1704903SN/A             "Addr: %x ntargets %d\n"
1714903SN/A             "Targets:\n",
1724903SN/A             inService, threadNum, addr, ntargets);
17310766Sandreas.hansson@arm.com
17410766Sandreas.hansson@arm.com    TargetListIterator tar_it = targets.begin();
1754903SN/A    for (int i = 0; i < ntargets; i++) {
1764903SN/A        assert(tar_it != targets.end());
1774903SN/A
1784903SN/A        ccprintf(cerr, "\t%d: Addr: %x cmd: %s\n",
1794903SN/A                 i, tar_it->pkt->getAddr(), tar_it->pkt->cmdString());
1804903SN/A
1812810SN/A        tar_it++;
1824908SN/A    }
1834908SN/A    ccprintf(cerr, "\n");
18410766Sandreas.hansson@arm.com}
18510766Sandreas.hansson@arm.com
1869543Ssascha.bischoff@arm.comMSHR::~MSHR()
1879543Ssascha.bischoff@arm.com{
1889543Ssascha.bischoff@arm.com}
1899543Ssascha.bischoff@arm.com