mshr.cc revision 4626
12221SN/A/* 22221SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32221SN/A * All rights reserved. 42221SN/A * 52221SN/A * Redistribution and use in source and binary forms, with or without 62221SN/A * modification, are permitted provided that the following conditions are 72221SN/A * met: redistributions of source code must retain the above copyright 82221SN/A * notice, this list of conditions and the following disclaimer; 92221SN/A * redistributions in binary form must reproduce the above copyright 102221SN/A * notice, this list of conditions and the following disclaimer in the 112221SN/A * documentation and/or other materials provided with the distribution; 122221SN/A * neither the name of the copyright holders nor the names of its 132221SN/A * contributors may be used to endorse or promote products derived from 142221SN/A * this software without specific prior written permission. 152221SN/A * 162221SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172221SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182221SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192221SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202221SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212221SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222221SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232221SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242221SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252221SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262221SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Erik Hallnor 292665Ssaidi@eecs.umich.edu * Dave Greene 302221SN/A */ 312221SN/A 323415Sgblack@eecs.umich.edu/** 333415Sgblack@eecs.umich.edu * @file 342223SN/A * Miss Status and Handling Register (MSHR) definitions. 353415Sgblack@eecs.umich.edu */ 363578Sgblack@eecs.umich.edu 373415Sgblack@eecs.umich.edu#include <assert.h> 383415Sgblack@eecs.umich.edu#include <string> 393523Sgblack@eecs.umich.edu#include <vector> 403415Sgblack@eecs.umich.edu 412680Sktlim@umich.edu#include "mem/cache/miss/mshr.hh" 422800Ssaidi@eecs.umich.edu#include "sim/core.hh" // for curTick 433523Sgblack@eecs.umich.edu#include "sim/host.hh" 443415Sgblack@eecs.umich.edu#include "base/misc.hh" 452800Ssaidi@eecs.umich.edu#include "mem/cache/cache.hh" 462800Ssaidi@eecs.umich.edu 472221SN/Ausing namespace std; 483415Sgblack@eecs.umich.edu 493415Sgblack@eecs.umich.eduMSHR::MSHR() 502223SN/A{ 512221SN/A inService = false; 522221SN/A ntargets = 0; 533573Sgblack@eecs.umich.edu threadNum = -1; 543576Sgblack@eecs.umich.edu} 553576Sgblack@eecs.umich.edu 562221SN/Avoid 573573Sgblack@eecs.umich.eduMSHR::allocate(Addr _addr, int _size, PacketPtr target, bool cacheFill) 583576Sgblack@eecs.umich.edu{ 593576Sgblack@eecs.umich.edu addr = _addr; 602221SN/A size = _size; 613573Sgblack@eecs.umich.edu assert(target); 623576Sgblack@eecs.umich.edu isCacheFill = cacheFill; 633576Sgblack@eecs.umich.edu needsExclusive = target->needsExclusive(); 642221SN/A _isUncacheable = target->req->isUncacheable(); 653573Sgblack@eecs.umich.edu inService = false; 663576Sgblack@eecs.umich.edu threadNum = 0; 673576Sgblack@eecs.umich.edu ntargets = 1; 682221SN/A // Don't know of a case where we would allocate a new MSHR for a 693573Sgblack@eecs.umich.edu // snoop (mem0-side request), so set cpuSide to true here. 703576Sgblack@eecs.umich.edu targets.push_back(Target(target, true)); 713576Sgblack@eecs.umich.edu} 722221SN/A 733573Sgblack@eecs.umich.eduvoid 743576Sgblack@eecs.umich.eduMSHR::deallocate() 753576Sgblack@eecs.umich.edu{ 762221SN/A assert(targets.empty()); 773573Sgblack@eecs.umich.edu assert(ntargets == 0); 783576Sgblack@eecs.umich.edu inService = false; 793576Sgblack@eecs.umich.edu //allocIter = NULL; 803576Sgblack@eecs.umich.edu //readyIter = NULL; 813576Sgblack@eecs.umich.edu} 823576Sgblack@eecs.umich.edu 833576Sgblack@eecs.umich.edu/* 843576Sgblack@eecs.umich.edu * Adds a target to an MSHR 852221SN/A */ 863573Sgblack@eecs.umich.eduvoid 873576Sgblack@eecs.umich.eduMSHR::allocateTarget(PacketPtr target, bool cpuSide) 883576Sgblack@eecs.umich.edu{ 892221SN/A //If we append an invalidate and we issued a read to the bus, 903573Sgblack@eecs.umich.edu //but now have some pending writes, we need to move 913576Sgblack@eecs.umich.edu //the invalidate to before the first non-read 923576Sgblack@eecs.umich.edu if (inService && !inServiceForExclusive && needsExclusive 932221SN/A && !cpuSide && target->isInvalidate()) { 943573Sgblack@eecs.umich.edu std::list<Target> temp; 953576Sgblack@eecs.umich.edu 963576Sgblack@eecs.umich.edu while (!targets.empty()) { 973576Sgblack@eecs.umich.edu if (targets.front().pkt->needsExclusive()) break; 983576Sgblack@eecs.umich.edu //Place on top of temp stack 993576Sgblack@eecs.umich.edu temp.push_front(targets.front()); 1003576Sgblack@eecs.umich.edu //Remove from targets 1013576Sgblack@eecs.umich.edu targets.pop_front(); 1023576Sgblack@eecs.umich.edu } 1033576Sgblack@eecs.umich.edu 1043576Sgblack@eecs.umich.edu //Now that we have all the reads off until first non-read, we can 1053576Sgblack@eecs.umich.edu //place the invalidate on 1063576Sgblack@eecs.umich.edu targets.push_front(Target(target, cpuSide)); 1072221SN/A 1083573Sgblack@eecs.umich.edu //Now we pop off the temp_stack and put them back 1093576Sgblack@eecs.umich.edu while (!temp.empty()) { 1103576Sgblack@eecs.umich.edu targets.push_front(temp.front()); 1112221SN/A temp.pop_front(); 1123573Sgblack@eecs.umich.edu } 1133576Sgblack@eecs.umich.edu } 1143576Sgblack@eecs.umich.edu else { 1152221SN/A targets.push_back(Target(target, cpuSide)); 1163573Sgblack@eecs.umich.edu } 1173576Sgblack@eecs.umich.edu 1183576Sgblack@eecs.umich.edu ++ntargets; 1192221SN/A assert(targets.size() == ntargets); 1203573Sgblack@eecs.umich.edu 1213576Sgblack@eecs.umich.edu needsExclusive = needsExclusive || target->needsExclusive(); 1223576Sgblack@eecs.umich.edu} 1232221SN/A 1243573Sgblack@eecs.umich.edu 1253576Sgblack@eecs.umich.eduvoid 1263576Sgblack@eecs.umich.eduMSHR::dump() 1272221SN/A{ 1283573Sgblack@eecs.umich.edu ccprintf(cerr, 1293576Sgblack@eecs.umich.edu "inService: %d thread: %d\n" 1303576Sgblack@eecs.umich.edu "Addr: %x ntargets %d\n" 1312223SN/A "Targets:\n", 1323573Sgblack@eecs.umich.edu inService, threadNum, addr, ntargets); 1333576Sgblack@eecs.umich.edu 1343576Sgblack@eecs.umich.edu TargetListIterator tar_it = targets.begin(); 1352223SN/A for (int i = 0; i < ntargets; i++) { 1363573Sgblack@eecs.umich.edu assert(tar_it != targets.end()); 1373576Sgblack@eecs.umich.edu 1383576Sgblack@eecs.umich.edu ccprintf(cerr, "\t%d: Addr: %x cmd: %s\n", 1392223SN/A i, tar_it->pkt->getAddr(), tar_it->pkt->cmdString()); 1403573Sgblack@eecs.umich.edu 1413576Sgblack@eecs.umich.edu tar_it++; 1423576Sgblack@eecs.umich.edu } 1432223SN/A ccprintf(cerr, "\n"); 1443573Sgblack@eecs.umich.edu} 1453576Sgblack@eecs.umich.edu 1463576Sgblack@eecs.umich.eduMSHR::~MSHR() 1473576Sgblack@eecs.umich.edu{ 1483576Sgblack@eecs.umich.edu} 1493576Sgblack@eecs.umich.edu