mshr.cc revision 4626 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 *          Dave Greene
30 */
31
32/**
33 * @file
34 * Miss Status and Handling Register (MSHR) definitions.
35 */
36
37#include <assert.h>
38#include <string>
39#include <vector>
40
41#include "mem/cache/miss/mshr.hh"
42#include "sim/core.hh" // for curTick
43#include "sim/host.hh"
44#include "base/misc.hh"
45#include "mem/cache/cache.hh"
46
47using namespace std;
48
49MSHR::MSHR()
50{
51    inService = false;
52    ntargets = 0;
53    threadNum = -1;
54}
55
56void
57MSHR::allocate(Addr _addr, int _size, PacketPtr target, bool cacheFill)
58{
59    addr = _addr;
60    size = _size;
61    assert(target);
62    isCacheFill = cacheFill;
63    needsExclusive = target->needsExclusive();
64    _isUncacheable = target->req->isUncacheable();
65    inService = false;
66    threadNum = 0;
67    ntargets = 1;
68    // Don't know of a case where we would allocate a new MSHR for a
69    // snoop (mem0-side request), so set cpuSide to true here.
70    targets.push_back(Target(target, true));
71}
72
73void
74MSHR::deallocate()
75{
76    assert(targets.empty());
77    assert(ntargets == 0);
78    inService = false;
79    //allocIter = NULL;
80    //readyIter = NULL;
81}
82
83/*
84 * Adds a target to an MSHR
85 */
86void
87MSHR::allocateTarget(PacketPtr target, bool cpuSide)
88{
89    //If we append an invalidate and we issued a read to the bus,
90    //but now have some pending writes, we need to move
91    //the invalidate to before the first non-read
92    if (inService && !inServiceForExclusive && needsExclusive
93        && !cpuSide && target->isInvalidate()) {
94        std::list<Target> temp;
95
96        while (!targets.empty()) {
97            if (targets.front().pkt->needsExclusive()) break;
98            //Place on top of temp stack
99            temp.push_front(targets.front());
100            //Remove from targets
101            targets.pop_front();
102        }
103
104        //Now that we have all the reads off until first non-read, we can
105        //place the invalidate on
106        targets.push_front(Target(target, cpuSide));
107
108        //Now we pop off the temp_stack and put them back
109        while (!temp.empty()) {
110            targets.push_front(temp.front());
111            temp.pop_front();
112        }
113    }
114    else {
115        targets.push_back(Target(target, cpuSide));
116    }
117
118    ++ntargets;
119    assert(targets.size() == ntargets);
120
121    needsExclusive = needsExclusive || target->needsExclusive();
122}
123
124
125void
126MSHR::dump()
127{
128    ccprintf(cerr,
129             "inService: %d thread: %d\n"
130             "Addr: %x ntargets %d\n"
131             "Targets:\n",
132             inService, threadNum, addr, ntargets);
133
134    TargetListIterator tar_it = targets.begin();
135    for (int i = 0; i < ntargets; i++) {
136        assert(tar_it != targets.end());
137
138        ccprintf(cerr, "\t%d: Addr: %x cmd: %s\n",
139                 i, tar_it->pkt->getAddr(), tar_it->pkt->cmdString());
140
141        tar_it++;
142    }
143    ccprintf(cerr, "\n");
144}
145
146MSHR::~MSHR()
147{
148}
149