DRAMCtrl.py revision 9971
12158SN/A# Copyright (c) 2012-2013 ARM Limited 22158SN/A# All rights reserved. 32158SN/A# 42158SN/A# The license below extends only to copyright in the software and shall 52158SN/A# not be construed as granting a license to any other intellectual 62158SN/A# property including but not limited to intellectual property relating 72158SN/A# to a hardware implementation of the functionality of the software 82158SN/A# licensed hereunder. You may use the software subject to the license 92158SN/A# terms below provided that you ensure that this notice is replicated 102158SN/A# unmodified and in its entirety in all distributions of the software, 112158SN/A# modified or unmodified, in source code or in binary form. 122158SN/A# 132158SN/A# Copyright (c) 2013 Amin Farmahini-Farahani 142158SN/A# All rights reserved. 152158SN/A# 162158SN/A# Redistribution and use in source and binary forms, with or without 172158SN/A# modification, are permitted provided that the following conditions are 182158SN/A# met: redistributions of source code must retain the above copyright 192158SN/A# notice, this list of conditions and the following disclaimer; 202158SN/A# redistributions in binary form must reproduce the above copyright 212158SN/A# notice, this list of conditions and the following disclaimer in the 222158SN/A# documentation and/or other materials provided with the distribution; 232158SN/A# neither the name of the copyright holders nor the names of its 242158SN/A# contributors may be used to endorse or promote products derived from 252158SN/A# this software without specific prior written permission. 262158SN/A# 272665Ssaidi@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 282665Ssaidi@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 292760Sbinkertn@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 302158SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 312158SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 322432SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 332158SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 342215SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 352158SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 362158SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 372158SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 382158SN/A# 392521SN/A# Authors: Andreas Hansson 402158SN/A# Ani Udipi 412158SN/A 422158SN/Afrom m5.params import * 432158SN/Afrom AbstractMemory import * 442158SN/A 452158SN/A# Enum for memory scheduling algorithms, currently First-Come 462158SN/A# First-Served and a First-Row Hit then First-Come First-Served 472158SN/Aclass MemSched(Enum): vals = ['fcfs', 'frfcfs'] 482158SN/A 492158SN/A# Enum for the address mapping. With Ra, Co, Ba and Ch denoting rank, 502158SN/A# column, bank and channel, respectively, and going from MSB to LSB. 512158SN/A# Available are RaBaChCo and RaBaCoCh, that are suitable for an 522158SN/A# open-page policy, optimising for sequential accesses hitting in the 532158SN/A# open row. For a closed-page policy, CoRaBaCh maximises parallelism. 542158SN/Aclass AddrMap(Enum): vals = ['RaBaChCo', 'RaBaCoCh', 'CoRaBaCh'] 552158SN/A 562158SN/A# Enum for the page policy, either open or close. 572158SN/Aclass PageManage(Enum): vals = ['open', 'close'] 582158SN/A 592158SN/A# SimpleDRAM is a single-channel single-ported DRAM controller model 602158SN/A# that aims to model the most important system-level performance 612158SN/A# effects of a DRAM without getting into too much detail of the DRAM 622158SN/A# itself. 632158SN/Aclass SimpleDRAM(AbstractMemory): 642158SN/A type = 'SimpleDRAM' 652158SN/A cxx_header = "mem/simple_dram.hh" 662158SN/A 672158SN/A # single-ported on the system interface side, instantiate with a 682521SN/A # bus in front of the controller for multiple ports 692521SN/A port = SlavePort("Slave port") 702158SN/A 712158SN/A # the basic configuration of the controller architecture 722158SN/A write_buffer_size = Param.Unsigned(32, "Number of read queue entries") 732158SN/A read_buffer_size = Param.Unsigned(32, "Number of write queue entries") 742158SN/A 752158SN/A # threshold in percent for when to trigger writes and start 762158SN/A # emptying the write buffer as it starts to get full 772158SN/A write_thresh_perc = Param.Percent(70, "Threshold to trigger writes") 782158SN/A 792158SN/A # scheduler, address map and page policy 802158SN/A mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy") 812158SN/A addr_mapping = Param.AddrMap('RaBaChCo', "Address mapping policy") 822158SN/A page_policy = Param.PageManage('open', "Page closure management policy") 832158SN/A 842158SN/A # pipeline latency of the controller and PHY, split into a 852158SN/A # frontend part and a backend part, with reads and writes serviced 862158SN/A # by the queues only seeing the frontend contribution, and reads 872158SN/A # serviced by the memory seeing the sum of the two 882158SN/A static_frontend_latency = Param.Latency("10ns", "Static frontend latency") 892158SN/A static_backend_latency = Param.Latency("10ns", "Static backend latency") 902158SN/A 912158SN/A # the physical organisation of the DRAM 922158SN/A device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\ 932158SN/A "device/chip") 942158SN/A burst_length = Param.Unsigned("Burst lenght (BL) in beats") 952158SN/A device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\ 962158SN/A "device/chip") 972158SN/A devices_per_rank = Param.Unsigned("Number of devices/chips per rank") 982158SN/A ranks_per_channel = Param.Unsigned("Number of ranks per channel") 992158SN/A banks_per_rank = Param.Unsigned("Number of banks per rank") 1002158SN/A # only used for the address mapping as the controller by 1012158SN/A # construction is a single channel and multiple controllers have 1022521SN/A # to be instantiated for a multi-channel configuration 1032521SN/A channels = Param.Unsigned(1, "Number of channels") 1042158SN/A 1052158SN/A # timing behaviour and constraints - all in nanoseconds 1062158SN/A 1072158SN/A # the amount of time in nanoseconds from issuing an activate command 1082158SN/A # to the data being available in the row buffer for a read/write 1092158SN/A tRCD = Param.Latency("RAS to CAS delay") 1102158SN/A 1112521SN/A # the time from issuing a read/write command to seeing the actual data 1122521SN/A tCL = Param.Latency("CAS latency") 1132549SN/A 1142521SN/A # minimum time between a precharge and subsequent activate 1152549SN/A tRP = Param.Latency("Row precharge time") 1162158SN/A 1172158SN/A # minimum time between an activate and a precharge to the same row 1182158SN/A tRAS = Param.Latency("ACT to PRE delay") 1192158SN/A 1202158SN/A # time to complete a burst transfer, typically the burst length 1212158SN/A # divided by two due to the DDR bus, but by making it a parameter 1222158SN/A # it is easier to also evaluate SDR memories like WideIO. 1232158SN/A # This parameter has to account for burst length. 1242158SN/A # Read/Write requests with data size larger than one full burst are broken 1252158SN/A # down into multiple requests in the SimpleDRAM controller 1262158SN/A tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)") 1272158SN/A 1282158SN/A # time taken to complete one refresh cycle (N rows in all banks) 1292158SN/A tRFC = Param.Latency("Refresh cycle time") 1302158SN/A 1312158SN/A # refresh command interval, how often a "ref" command needs 1322158SN/A # to be sent. It is 7.8 us for a 64ms refresh requirement 1332158SN/A tREFI = Param.Latency("Refresh command interval") 1342158SN/A 1352158SN/A # write-to-read turn around penalty, assumed same as read-to-write 1362158SN/A tWTR = Param.Latency("Write to read switching time") 1372158SN/A 1382158SN/A # minimum row activate to row activate delay time 1392158SN/A tRRD = Param.Latency("ACT to ACT delay") 1402158SN/A 1412158SN/A # time window in which a maximum number of activates are allowed 1422158SN/A # to take place, set to 0 to disable 1432158SN/A tXAW = Param.Latency("X activation window") 1442158SN/A activation_limit = Param.Unsigned("Max number of activates in window") 1452158SN/A 1462158SN/A # Currently rolled into other params 1472158SN/A ###################################################################### 1482158SN/A 1492158SN/A # tRC - assumed to be tRAS + tRP 1502158SN/A 1512158SN/A# A single DDR3 x64 interface (one command and address bus), with 1522158SN/A# default timings based on DDR3-1600 4 Gbit parts in an 8x8 1532158SN/A# configuration, which would amount to 4 Gbyte of memory. 1542158SN/Aclass DDR3_1600_x64(SimpleDRAM): 1552158SN/A # 8x8 configuration, 8 devices each with an 8-bit interface 1562158SN/A device_bus_width = 8 1572158SN/A 1582158SN/A # DDR3 is a BL8 device 1592158SN/A burst_length = 8 1602158SN/A 1612158SN/A # Each device has a page (row buffer) size of 1KB 1622158SN/A # (this depends on the memory density) 1632158SN/A device_rowbuffer_size = '1kB' 1642158SN/A 1652158SN/A # 8x8 configuration, so 8 devices 1662158SN/A devices_per_rank = 8 1672158SN/A 1682158SN/A # Use two ranks 1692158SN/A ranks_per_channel = 2 1702158SN/A 1712158SN/A # DDR3 has 8 banks in all configurations 1722521SN/A banks_per_rank = 8 1732521SN/A 1742158SN/A # DDR3-1600 11-11-11-28 1752158SN/A tRCD = '13.75ns' 1762158SN/A tCL = '13.75ns' 1772521SN/A tRP = '13.75ns' 1782158SN/A tRAS = '35ns' 1792158SN/A 1802158SN/A # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz. 1812158SN/A # Note this is a BL8 DDR device. 1822158SN/A tBURST = '5ns' 1832158SN/A 1842158SN/A # DDR3, 4 Gbit has a tRFC of 240 CK and tCK = 1.25 ns 1852158SN/A tRFC = '300ns' 1862158SN/A 1872158SN/A # DDR3, <=85C, half for >85C 1882158SN/A tREFI = '7.8us' 1892158SN/A 1902158SN/A # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns 1912521SN/A tWTR = '7.5ns' 1922158SN/A 1932158SN/A # Assume 5 CK for activate to activate for different banks 1942158SN/A tRRD = '6.25ns' 1952158SN/A 1962158SN/A # With a 2kbyte page size, DDR3-1600 lands around 40 ns 1972158SN/A tXAW = '40ns' 1982158SN/A activation_limit = 4 1992158SN/A 2002158SN/A 2012158SN/A# A single LPDDR2-S4 x32 interface (one command/address bus), with 2022158SN/A# default timings based on a LPDDR2-1066 4 Gbit part in a 1x32 2032158SN/A# configuration. 2042158SN/Aclass LPDDR2_S4_1066_x32(SimpleDRAM): 2052158SN/A # 1x32 configuration, 1 device with a 32-bit interface 2062158SN/A device_bus_width = 32 2072158SN/A 2082158SN/A # LPDDR2_S4 is a BL4 and BL8 device 2092158SN/A burst_length = 8 2102158SN/A 2112158SN/A # Each device has a page (row buffer) size of 1KB 2122158SN/A # (this depends on the memory density) 2132158SN/A device_rowbuffer_size = '1kB' 2142158SN/A 2152158SN/A # 1x32 configuration, so 1 device 2162158SN/A devices_per_rank = 1 2172158SN/A 2182158SN/A # Use a single rank 2192158SN/A ranks_per_channel = 1 2202158SN/A 2212158SN/A # LPDDR2-S4 has 8 banks in all configurations 2222158SN/A banks_per_rank = 8 2232158SN/A 2242158SN/A # Fixed at 15 ns 2252158SN/A tRCD = '15ns' 2262158SN/A 2272158SN/A # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time 2282158SN/A tCL = '15ns' 2292158SN/A 2302158SN/A # Pre-charge one bank 15 ns (all banks 18 ns) 2312158SN/A tRP = '15ns' 2322158SN/A 2332158SN/A tRAS = '42ns' 2342158SN/A 2352158SN/A # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz. 2362158SN/A # Note this is a BL8 DDR device. 2372158SN/A # Requests larger than 32 bytes are broken down into multiple requests 2382158SN/A # in the SimpleDRAM controller 2392158SN/A tBURST = '7.5ns' 2402158SN/A 2412158SN/A # LPDDR2-S4, 4 Gbit 2422158SN/A tRFC = '130ns' 2432158SN/A tREFI = '3.9us' 2442158SN/A 2452158SN/A # Irrespective of speed grade, tWTR is 7.5 ns 2462158SN/A tWTR = '7.5ns' 2472158SN/A 2482158SN/A # Activate to activate irrespective of density and speed grade 2492158SN/A tRRD = '10.0ns' 2502343SN/A 2512158SN/A # Irrespective of density, tFAW is 50 ns 2522158SN/A tXAW = '50ns' 2532158SN/A activation_limit = 4 2542158SN/A 2552158SN/A# A single WideIO x128 interface (one command and address bus), with 2562158SN/A# default timings based on an estimated WIO-200 8 Gbit part. 2572158SN/Aclass WideIO_200_x128(SimpleDRAM): 2582158SN/A # 1x128 configuration, 1 device with a 128-bit interface 2592158SN/A device_bus_width = 128 2602158SN/A 2612158SN/A # This is a BL4 device 2622158SN/A burst_length = 4 2632158SN/A 2642158SN/A # Each device has a page (row buffer) size of 4KB 2652158SN/A # (this depends on the memory density) 2662158SN/A device_rowbuffer_size = '4kB' 2672158SN/A 2682158SN/A # 1x128 configuration, so 1 device 2692158SN/A devices_per_rank = 1 2702158SN/A 2712158SN/A # Use one rank for a one-high die stack 2722158SN/A ranks_per_channel = 1 2732158SN/A 274 # WideIO has 4 banks in all configurations 275 banks_per_rank = 4 276 277 # WIO-200 278 tRCD = '18ns' 279 tCL = '18ns' 280 tRP = '18ns' 281 tRAS = '42ns' 282 283 # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz. 284 # Note this is a BL4 SDR device. 285 tBURST = '20ns' 286 287 # WIO 8 Gb 288 tRFC = '210ns' 289 290 # WIO 8 Gb, <=85C, half for >85C 291 tREFI = '3.9us' 292 293 # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns 294 tWTR = '15ns' 295 296 # Activate to activate irrespective of density and speed grade 297 tRRD = '10.0ns' 298 299 # Two instead of four activation window 300 tXAW = '50ns' 301 activation_limit = 2 302 303# A single LPDDR3 x32 interface (one command/address bus), with 304# default timings based on a LPDDR3-1600 4 Gbit part in a 1x32 305# configuration 306class LPDDR3_1600_x32(SimpleDRAM): 307 # 1x32 configuration, 1 device with a 32-bit interface 308 device_bus_width = 32 309 310 # LPDDR3 is a BL8 device 311 burst_length = 8 312 313 # Each device has a page (row buffer) size of 1KB 314 # (this depends on the memory density) 315 device_rowbuffer_size = '1kB' 316 317 # 1x32 configuration, so 1 device 318 devices_per_rank = 1 319 320 # Use a single rank 321 ranks_per_channel = 1 322 323 # LPDDR3 has 8 banks in all configurations 324 banks_per_rank = 8 325 326 # Fixed at 15 ns 327 tRCD = '15ns' 328 329 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time 330 tCL = '15ns' 331 332 tRAS = '42ns' 333 334 # Pre-charge one bank 15 ns (all banks 18 ns) 335 tRP = '15ns' 336 337 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz. 338 # Note this is a BL8 DDR device. 339 # Requests larger than 32 bytes are broken down into multiple requests 340 # in the SimpleDRAM controller 341 tBURST = '5ns' 342 343 # LPDDR3, 4 Gb 344 tRFC = '130ns' 345 tREFI = '3.9us' 346 347 # Irrespective of speed grade, tWTR is 7.5 ns 348 tWTR = '7.5ns' 349 350 # Activate to activate irrespective of density and speed grade 351 tRRD = '10.0ns' 352 353 # Irrespective of size, tFAW is 50 ns 354 tXAW = '50ns' 355 activation_limit = 4 356