DRAMCtrl.py revision 9971
1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2013 Amin Farmahini-Farahani 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Andreas Hansson 40# Ani Udipi 41 42from m5.params import * 43from AbstractMemory import * 44 45# Enum for memory scheduling algorithms, currently First-Come 46# First-Served and a First-Row Hit then First-Come First-Served 47class MemSched(Enum): vals = ['fcfs', 'frfcfs'] 48 49# Enum for the address mapping. With Ra, Co, Ba and Ch denoting rank, 50# column, bank and channel, respectively, and going from MSB to LSB. 51# Available are RaBaChCo and RaBaCoCh, that are suitable for an 52# open-page policy, optimising for sequential accesses hitting in the 53# open row. For a closed-page policy, CoRaBaCh maximises parallelism. 54class AddrMap(Enum): vals = ['RaBaChCo', 'RaBaCoCh', 'CoRaBaCh'] 55 56# Enum for the page policy, either open or close. 57class PageManage(Enum): vals = ['open', 'close'] 58 59# SimpleDRAM is a single-channel single-ported DRAM controller model 60# that aims to model the most important system-level performance 61# effects of a DRAM without getting into too much detail of the DRAM 62# itself. 63class SimpleDRAM(AbstractMemory): 64 type = 'SimpleDRAM' 65 cxx_header = "mem/simple_dram.hh" 66 67 # single-ported on the system interface side, instantiate with a 68 # bus in front of the controller for multiple ports 69 port = SlavePort("Slave port") 70 71 # the basic configuration of the controller architecture 72 write_buffer_size = Param.Unsigned(32, "Number of read queue entries") 73 read_buffer_size = Param.Unsigned(32, "Number of write queue entries") 74 75 # threshold in percent for when to trigger writes and start 76 # emptying the write buffer as it starts to get full 77 write_thresh_perc = Param.Percent(70, "Threshold to trigger writes") 78 79 # scheduler, address map and page policy 80 mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy") 81 addr_mapping = Param.AddrMap('RaBaChCo', "Address mapping policy") 82 page_policy = Param.PageManage('open', "Page closure management policy") 83 84 # pipeline latency of the controller and PHY, split into a 85 # frontend part and a backend part, with reads and writes serviced 86 # by the queues only seeing the frontend contribution, and reads 87 # serviced by the memory seeing the sum of the two 88 static_frontend_latency = Param.Latency("10ns", "Static frontend latency") 89 static_backend_latency = Param.Latency("10ns", "Static backend latency") 90 91 # the physical organisation of the DRAM 92 device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\ 93 "device/chip") 94 burst_length = Param.Unsigned("Burst lenght (BL) in beats") 95 device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\ 96 "device/chip") 97 devices_per_rank = Param.Unsigned("Number of devices/chips per rank") 98 ranks_per_channel = Param.Unsigned("Number of ranks per channel") 99 banks_per_rank = Param.Unsigned("Number of banks per rank") 100 # only used for the address mapping as the controller by 101 # construction is a single channel and multiple controllers have 102 # to be instantiated for a multi-channel configuration 103 channels = Param.Unsigned(1, "Number of channels") 104 105 # timing behaviour and constraints - all in nanoseconds 106 107 # the amount of time in nanoseconds from issuing an activate command 108 # to the data being available in the row buffer for a read/write 109 tRCD = Param.Latency("RAS to CAS delay") 110 111 # the time from issuing a read/write command to seeing the actual data 112 tCL = Param.Latency("CAS latency") 113 114 # minimum time between a precharge and subsequent activate 115 tRP = Param.Latency("Row precharge time") 116 117 # minimum time between an activate and a precharge to the same row 118 tRAS = Param.Latency("ACT to PRE delay") 119 120 # time to complete a burst transfer, typically the burst length 121 # divided by two due to the DDR bus, but by making it a parameter 122 # it is easier to also evaluate SDR memories like WideIO. 123 # This parameter has to account for burst length. 124 # Read/Write requests with data size larger than one full burst are broken 125 # down into multiple requests in the SimpleDRAM controller 126 tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)") 127 128 # time taken to complete one refresh cycle (N rows in all banks) 129 tRFC = Param.Latency("Refresh cycle time") 130 131 # refresh command interval, how often a "ref" command needs 132 # to be sent. It is 7.8 us for a 64ms refresh requirement 133 tREFI = Param.Latency("Refresh command interval") 134 135 # write-to-read turn around penalty, assumed same as read-to-write 136 tWTR = Param.Latency("Write to read switching time") 137 138 # minimum row activate to row activate delay time 139 tRRD = Param.Latency("ACT to ACT delay") 140 141 # time window in which a maximum number of activates are allowed 142 # to take place, set to 0 to disable 143 tXAW = Param.Latency("X activation window") 144 activation_limit = Param.Unsigned("Max number of activates in window") 145 146 # Currently rolled into other params 147 ###################################################################### 148 149 # tRC - assumed to be tRAS + tRP 150 151# A single DDR3 x64 interface (one command and address bus), with 152# default timings based on DDR3-1600 4 Gbit parts in an 8x8 153# configuration, which would amount to 4 Gbyte of memory. 154class DDR3_1600_x64(SimpleDRAM): 155 # 8x8 configuration, 8 devices each with an 8-bit interface 156 device_bus_width = 8 157 158 # DDR3 is a BL8 device 159 burst_length = 8 160 161 # Each device has a page (row buffer) size of 1KB 162 # (this depends on the memory density) 163 device_rowbuffer_size = '1kB' 164 165 # 8x8 configuration, so 8 devices 166 devices_per_rank = 8 167 168 # Use two ranks 169 ranks_per_channel = 2 170 171 # DDR3 has 8 banks in all configurations 172 banks_per_rank = 8 173 174 # DDR3-1600 11-11-11-28 175 tRCD = '13.75ns' 176 tCL = '13.75ns' 177 tRP = '13.75ns' 178 tRAS = '35ns' 179 180 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz. 181 # Note this is a BL8 DDR device. 182 tBURST = '5ns' 183 184 # DDR3, 4 Gbit has a tRFC of 240 CK and tCK = 1.25 ns 185 tRFC = '300ns' 186 187 # DDR3, <=85C, half for >85C 188 tREFI = '7.8us' 189 190 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns 191 tWTR = '7.5ns' 192 193 # Assume 5 CK for activate to activate for different banks 194 tRRD = '6.25ns' 195 196 # With a 2kbyte page size, DDR3-1600 lands around 40 ns 197 tXAW = '40ns' 198 activation_limit = 4 199 200 201# A single LPDDR2-S4 x32 interface (one command/address bus), with 202# default timings based on a LPDDR2-1066 4 Gbit part in a 1x32 203# configuration. 204class LPDDR2_S4_1066_x32(SimpleDRAM): 205 # 1x32 configuration, 1 device with a 32-bit interface 206 device_bus_width = 32 207 208 # LPDDR2_S4 is a BL4 and BL8 device 209 burst_length = 8 210 211 # Each device has a page (row buffer) size of 1KB 212 # (this depends on the memory density) 213 device_rowbuffer_size = '1kB' 214 215 # 1x32 configuration, so 1 device 216 devices_per_rank = 1 217 218 # Use a single rank 219 ranks_per_channel = 1 220 221 # LPDDR2-S4 has 8 banks in all configurations 222 banks_per_rank = 8 223 224 # Fixed at 15 ns 225 tRCD = '15ns' 226 227 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time 228 tCL = '15ns' 229 230 # Pre-charge one bank 15 ns (all banks 18 ns) 231 tRP = '15ns' 232 233 tRAS = '42ns' 234 235 # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz. 236 # Note this is a BL8 DDR device. 237 # Requests larger than 32 bytes are broken down into multiple requests 238 # in the SimpleDRAM controller 239 tBURST = '7.5ns' 240 241 # LPDDR2-S4, 4 Gbit 242 tRFC = '130ns' 243 tREFI = '3.9us' 244 245 # Irrespective of speed grade, tWTR is 7.5 ns 246 tWTR = '7.5ns' 247 248 # Activate to activate irrespective of density and speed grade 249 tRRD = '10.0ns' 250 251 # Irrespective of density, tFAW is 50 ns 252 tXAW = '50ns' 253 activation_limit = 4 254 255# A single WideIO x128 interface (one command and address bus), with 256# default timings based on an estimated WIO-200 8 Gbit part. 257class WideIO_200_x128(SimpleDRAM): 258 # 1x128 configuration, 1 device with a 128-bit interface 259 device_bus_width = 128 260 261 # This is a BL4 device 262 burst_length = 4 263 264 # Each device has a page (row buffer) size of 4KB 265 # (this depends on the memory density) 266 device_rowbuffer_size = '4kB' 267 268 # 1x128 configuration, so 1 device 269 devices_per_rank = 1 270 271 # Use one rank for a one-high die stack 272 ranks_per_channel = 1 273 274 # WideIO has 4 banks in all configurations 275 banks_per_rank = 4 276 277 # WIO-200 278 tRCD = '18ns' 279 tCL = '18ns' 280 tRP = '18ns' 281 tRAS = '42ns' 282 283 # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz. 284 # Note this is a BL4 SDR device. 285 tBURST = '20ns' 286 287 # WIO 8 Gb 288 tRFC = '210ns' 289 290 # WIO 8 Gb, <=85C, half for >85C 291 tREFI = '3.9us' 292 293 # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns 294 tWTR = '15ns' 295 296 # Activate to activate irrespective of density and speed grade 297 tRRD = '10.0ns' 298 299 # Two instead of four activation window 300 tXAW = '50ns' 301 activation_limit = 2 302 303# A single LPDDR3 x32 interface (one command/address bus), with 304# default timings based on a LPDDR3-1600 4 Gbit part in a 1x32 305# configuration 306class LPDDR3_1600_x32(SimpleDRAM): 307 # 1x32 configuration, 1 device with a 32-bit interface 308 device_bus_width = 32 309 310 # LPDDR3 is a BL8 device 311 burst_length = 8 312 313 # Each device has a page (row buffer) size of 1KB 314 # (this depends on the memory density) 315 device_rowbuffer_size = '1kB' 316 317 # 1x32 configuration, so 1 device 318 devices_per_rank = 1 319 320 # Use a single rank 321 ranks_per_channel = 1 322 323 # LPDDR3 has 8 banks in all configurations 324 banks_per_rank = 8 325 326 # Fixed at 15 ns 327 tRCD = '15ns' 328 329 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time 330 tCL = '15ns' 331 332 tRAS = '42ns' 333 334 # Pre-charge one bank 15 ns (all banks 18 ns) 335 tRP = '15ns' 336 337 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz. 338 # Note this is a BL8 DDR device. 339 # Requests larger than 32 bytes are broken down into multiple requests 340 # in the SimpleDRAM controller 341 tBURST = '5ns' 342 343 # LPDDR3, 4 Gb 344 tRFC = '130ns' 345 tREFI = '3.9us' 346 347 # Irrespective of speed grade, tWTR is 7.5 ns 348 tWTR = '7.5ns' 349 350 # Activate to activate irrespective of density and speed grade 351 tRRD = '10.0ns' 352 353 # Irrespective of size, tFAW is 50 ns 354 tXAW = '50ns' 355 activation_limit = 4 356