DRAMCtrl.py revision 9243
15647Sgblack@eecs.umich.edu# Copyright (c) 2012 ARM Limited 29544Sandreas.hansson@arm.com# All rights reserved. 38922Swilliam.wang@arm.com# 48922Swilliam.wang@arm.com# The license below extends only to copyright in the software and shall 58922Swilliam.wang@arm.com# not be construed as granting a license to any other intellectual 68922Swilliam.wang@arm.com# property including but not limited to intellectual property relating 78922Swilliam.wang@arm.com# to a hardware implementation of the functionality of the software 88922Swilliam.wang@arm.com# licensed hereunder. You may use the software subject to the license 98922Swilliam.wang@arm.com# terms below provided that you ensure that this notice is replicated 108922Swilliam.wang@arm.com# unmodified and in its entirety in all distributions of the software, 118922Swilliam.wang@arm.com# modified or unmodified, in source code or in binary form. 128922Swilliam.wang@arm.com# 138922Swilliam.wang@arm.com# Redistribution and use in source and binary forms, with or without 145647Sgblack@eecs.umich.edu# modification, are permitted provided that the following conditions are 155647Sgblack@eecs.umich.edu# met: redistributions of source code must retain the above copyright 165647Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 177087Snate@binkert.org# redistributions in binary form must reproduce the above copyright 187087Snate@binkert.org# notice, this list of conditions and the following disclaimer in the 197087Snate@binkert.org# documentation and/or other materials provided with the distribution; 207087Snate@binkert.org# neither the name of the copyright holders nor the names of its 217087Snate@binkert.org# contributors may be used to endorse or promote products derived from 227087Snate@binkert.org# this software without specific prior written permission. 237087Snate@binkert.org# 247087Snate@binkert.org# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 255647Sgblack@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 267087Snate@binkert.org# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 277087Snate@binkert.org# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 287087Snate@binkert.org# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 297087Snate@binkert.org# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 307087Snate@binkert.org# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 317087Snate@binkert.org# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 327087Snate@binkert.org# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 337087Snate@binkert.org# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 345647Sgblack@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 357087Snate@binkert.org# 365647Sgblack@eecs.umich.edu# Authors: Andreas Hansson 375647Sgblack@eecs.umich.edu# Ani Udipi 385647Sgblack@eecs.umich.edu 395647Sgblack@eecs.umich.edufrom m5.params import * 405647Sgblack@eecs.umich.edufrom AbstractMemory import * 415647Sgblack@eecs.umich.edu 425647Sgblack@eecs.umich.edu# Enum for memory scheduling algorithms, currently First-Come 435647Sgblack@eecs.umich.edu# First-Served and a First-Row Hit then First-Come First-Served 445647Sgblack@eecs.umich.educlass MemSched(Enum): vals = ['fcfs', 'frfcfs'] 455647Sgblack@eecs.umich.edu 465647Sgblack@eecs.umich.edu# Enum for the address mapping, currently corresponding to either 475647Sgblack@eecs.umich.edu# optimising for sequential accesses hitting in the open row, or 485647Sgblack@eecs.umich.edu# striping across banks. 495647Sgblack@eecs.umich.educlass AddrMap(Enum): vals = ['openmap', 'closemap'] 505647Sgblack@eecs.umich.edu 515647Sgblack@eecs.umich.edu# Enum for the page policy, either open or close. 5211793Sbrandon.potter@amd.comclass PageManage(Enum): vals = ['open', 'close'] 5311793Sbrandon.potter@amd.com 5410474Sandreas.hansson@arm.com# SimpleDRAM is a single-channel single-ported DRAM controller model 5510474Sandreas.hansson@arm.com# that aims to model the most important system-level performance 5611793Sbrandon.potter@amd.com# effects of a DRAM without getting into too much detail of the DRAM 578229Snate@binkert.org# itself. 585647Sgblack@eecs.umich.educlass SimpleDRAM(AbstractMemory): 598232Snate@binkert.org type = 'SimpleDRAM' 606137Sgblack@eecs.umich.edu 616137Sgblack@eecs.umich.edu # single-ported on the system interface side, instantiate with a 626137Sgblack@eecs.umich.edu # bus in front of the controller for multiple ports 635654Sgblack@eecs.umich.edu port = SlavePort("Slave port") 6411793Sbrandon.potter@amd.com 656046Sgblack@eecs.umich.edu # the physical organisation of the DRAM 665647Sgblack@eecs.umich.edu lines_per_rowbuffer = Param.Unsigned(64, "Row buffer size in cache lines") 675648Sgblack@eecs.umich.edu ranks_per_channel = Param.Unsigned(2, "Number of ranks per channel") 685648Sgblack@eecs.umich.edu banks_per_rank = Param.Unsigned(8, "Number of banks per rank") 695647Sgblack@eecs.umich.edu 705647Sgblack@eecs.umich.edu # the basic configuration of the controller architecture 715647Sgblack@eecs.umich.edu write_buffer_size = Param.Unsigned(32, "Number of read queue entries") 725647Sgblack@eecs.umich.edu read_buffer_size = Param.Unsigned(32, "Number of write queue entries") 735647Sgblack@eecs.umich.edu 745647Sgblack@eecs.umich.edu # threshold in percent for when to trigger writes and start 755647Sgblack@eecs.umich.edu # emptying the write buffer as it starts to get full 765647Sgblack@eecs.umich.edu write_thresh_perc = Param.Percent(70, "Threshold to trigger writes") 775647Sgblack@eecs.umich.edu 785648Sgblack@eecs.umich.edu # scheduler, address map and page policy 795647Sgblack@eecs.umich.edu mem_sched_policy = Param.MemSched('fcfs', "Memory scheduling policy") 805648Sgblack@eecs.umich.edu addr_mapping = Param.AddrMap('openmap', "Address mapping policy") 815648Sgblack@eecs.umich.edu page_policy = Param.PageManage('open', "Page closure management policy") 825648Sgblack@eecs.umich.edu 835648Sgblack@eecs.umich.edu # timing behaviour and constraints - all in nanoseconds 845648Sgblack@eecs.umich.edu 855648Sgblack@eecs.umich.edu # the amount of time in nanoseconds from issuing an activate command 865648Sgblack@eecs.umich.edu # to the data being available in the row buffer for a read/write 875648Sgblack@eecs.umich.edu tRCD = Param.Latency("14ns", "RAS to CAS delay") 885648Sgblack@eecs.umich.edu 895648Sgblack@eecs.umich.edu # the time from issuing a read/write command to seeing the actual data 905648Sgblack@eecs.umich.edu tCL = Param.Latency("14ns", "CAS latency") 915648Sgblack@eecs.umich.edu 925648Sgblack@eecs.umich.edu # minimum time between a precharge and subsequent activate 935648Sgblack@eecs.umich.edu tRP = Param.Latency("14ns", "Row precharge time") 945648Sgblack@eecs.umich.edu 955648Sgblack@eecs.umich.edu # time to complete a burst transfer, typically the burst length 965648Sgblack@eecs.umich.edu # divided by two due to the DDR bus, but by making it a parameter 975648Sgblack@eecs.umich.edu # it is easier to also evaluate SDR memories like WideIO. 985648Sgblack@eecs.umich.edu # This parameter has to account for bus width and burst length. 995648Sgblack@eecs.umich.edu # Adjustment also necessary if cache line size is greater than 1005648Sgblack@eecs.umich.edu # data size read/written by one full burst. 1015648Sgblack@eecs.umich.edu tBURST = Param.Latency("4ns", 1025648Sgblack@eecs.umich.edu "Burst duration (for DDR burst length / 2 cycles)") 1035648Sgblack@eecs.umich.edu 1045648Sgblack@eecs.umich.edu # time taken to complete one refresh cycle (N rows in all banks) 1055648Sgblack@eecs.umich.edu tRFC = Param.Latency("300ns", "Refresh cycle time") 1065648Sgblack@eecs.umich.edu 1075648Sgblack@eecs.umich.edu # refresh command interval, how often a "ref" command needs 1085648Sgblack@eecs.umich.edu # to be sent. It is 7.8 us for a 64ms refresh requirement 1095648Sgblack@eecs.umich.edu tREFI = Param.Latency("7.8us", "Refresh command interval") 1105648Sgblack@eecs.umich.edu 1115648Sgblack@eecs.umich.edu # write-to-read turn around penalty, assumed same as read-to-write 1125648Sgblack@eecs.umich.edu tWTR = Param.Latency("1ns", "Write to read switching time") 1135648Sgblack@eecs.umich.edu 1145648Sgblack@eecs.umich.edu # Currently unimplemented, unused, deduced or rolled into other params 1155648Sgblack@eecs.umich.edu ###################################################################### 1165648Sgblack@eecs.umich.edu 1175648Sgblack@eecs.umich.edu # the minimum amount of time between a row being activated, and 1185648Sgblack@eecs.umich.edu # precharged (de-activated) 1195648Sgblack@eecs.umich.edu # tRAS - assumed to be 3 * tRP 1205648Sgblack@eecs.umich.edu 1215648Sgblack@eecs.umich.edu # tRC - assumed to be 4 * tRP 1225648Sgblack@eecs.umich.edu 12311479Sbaz21@cam.ac.uk # burst length for an access derived from peerBlockSize 1245648Sgblack@eecs.umich.edu 1255648Sgblack@eecs.umich.edu # @todo: Implement tFAW in the model 1265648Sgblack@eecs.umich.edu # minimum time window in which a maximum of four activates are 1275648Sgblack@eecs.umich.edu # allowed to take place 1285648Sgblack@eecs.umich.edu # tFAW = Param.Latency("30ns", "Four activation window") 1295648Sgblack@eecs.umich.edu 1305648Sgblack@eecs.umich.edu 1315648Sgblack@eecs.umich.edu