DRAMCtrl.py revision 9243
1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Redistribution and use in source and binary forms, with or without 14# modification, are permitted provided that the following conditions are 15# met: redistributions of source code must retain the above copyright 16# notice, this list of conditions and the following disclaimer; 17# redistributions in binary form must reproduce the above copyright 18# notice, this list of conditions and the following disclaimer in the 19# documentation and/or other materials provided with the distribution; 20# neither the name of the copyright holders nor the names of its 21# contributors may be used to endorse or promote products derived from 22# this software without specific prior written permission. 23# 24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Andreas Hansson 37# Ani Udipi 38 39from m5.params import * 40from AbstractMemory import * 41 42# Enum for memory scheduling algorithms, currently First-Come 43# First-Served and a First-Row Hit then First-Come First-Served 44class MemSched(Enum): vals = ['fcfs', 'frfcfs'] 45 46# Enum for the address mapping, currently corresponding to either 47# optimising for sequential accesses hitting in the open row, or 48# striping across banks. 49class AddrMap(Enum): vals = ['openmap', 'closemap'] 50 51# Enum for the page policy, either open or close. 52class PageManage(Enum): vals = ['open', 'close'] 53 54# SimpleDRAM is a single-channel single-ported DRAM controller model 55# that aims to model the most important system-level performance 56# effects of a DRAM without getting into too much detail of the DRAM 57# itself. 58class SimpleDRAM(AbstractMemory): 59 type = 'SimpleDRAM' 60 61 # single-ported on the system interface side, instantiate with a 62 # bus in front of the controller for multiple ports 63 port = SlavePort("Slave port") 64 65 # the physical organisation of the DRAM 66 lines_per_rowbuffer = Param.Unsigned(64, "Row buffer size in cache lines") 67 ranks_per_channel = Param.Unsigned(2, "Number of ranks per channel") 68 banks_per_rank = Param.Unsigned(8, "Number of banks per rank") 69 70 # the basic configuration of the controller architecture 71 write_buffer_size = Param.Unsigned(32, "Number of read queue entries") 72 read_buffer_size = Param.Unsigned(32, "Number of write queue entries") 73 74 # threshold in percent for when to trigger writes and start 75 # emptying the write buffer as it starts to get full 76 write_thresh_perc = Param.Percent(70, "Threshold to trigger writes") 77 78 # scheduler, address map and page policy 79 mem_sched_policy = Param.MemSched('fcfs', "Memory scheduling policy") 80 addr_mapping = Param.AddrMap('openmap', "Address mapping policy") 81 page_policy = Param.PageManage('open', "Page closure management policy") 82 83 # timing behaviour and constraints - all in nanoseconds 84 85 # the amount of time in nanoseconds from issuing an activate command 86 # to the data being available in the row buffer for a read/write 87 tRCD = Param.Latency("14ns", "RAS to CAS delay") 88 89 # the time from issuing a read/write command to seeing the actual data 90 tCL = Param.Latency("14ns", "CAS latency") 91 92 # minimum time between a precharge and subsequent activate 93 tRP = Param.Latency("14ns", "Row precharge time") 94 95 # time to complete a burst transfer, typically the burst length 96 # divided by two due to the DDR bus, but by making it a parameter 97 # it is easier to also evaluate SDR memories like WideIO. 98 # This parameter has to account for bus width and burst length. 99 # Adjustment also necessary if cache line size is greater than 100 # data size read/written by one full burst. 101 tBURST = Param.Latency("4ns", 102 "Burst duration (for DDR burst length / 2 cycles)") 103 104 # time taken to complete one refresh cycle (N rows in all banks) 105 tRFC = Param.Latency("300ns", "Refresh cycle time") 106 107 # refresh command interval, how often a "ref" command needs 108 # to be sent. It is 7.8 us for a 64ms refresh requirement 109 tREFI = Param.Latency("7.8us", "Refresh command interval") 110 111 # write-to-read turn around penalty, assumed same as read-to-write 112 tWTR = Param.Latency("1ns", "Write to read switching time") 113 114 # Currently unimplemented, unused, deduced or rolled into other params 115 ###################################################################### 116 117 # the minimum amount of time between a row being activated, and 118 # precharged (de-activated) 119 # tRAS - assumed to be 3 * tRP 120 121 # tRC - assumed to be 4 * tRP 122 123 # burst length for an access derived from peerBlockSize 124 125 # @todo: Implement tFAW in the model 126 # minimum time window in which a maximum of four activates are 127 # allowed to take place 128 # tFAW = Param.Latency("30ns", "Four activation window") 129 130 131