DRAMCtrl.py revision 10145
12497SN/A# Copyright (c) 2012-2013 ARM Limited 211605Snikos.nikoleris@arm.com# All rights reserved. 38711SN/A# 48711SN/A# The license below extends only to copyright in the software and shall 58711SN/A# not be construed as granting a license to any other intellectual 68711SN/A# property including but not limited to intellectual property relating 78711SN/A# to a hardware implementation of the functionality of the software 88711SN/A# licensed hereunder. You may use the software subject to the license 98711SN/A# terms below provided that you ensure that this notice is replicated 108711SN/A# unmodified and in its entirety in all distributions of the software, 118711SN/A# modified or unmodified, in source code or in binary form. 128711SN/A# 138711SN/A# Copyright (c) 2013 Amin Farmahini-Farahani 142497SN/A# All rights reserved. 152497SN/A# 162497SN/A# Redistribution and use in source and binary forms, with or without 172497SN/A# modification, are permitted provided that the following conditions are 182497SN/A# met: redistributions of source code must retain the above copyright 192497SN/A# notice, this list of conditions and the following disclaimer; 202497SN/A# redistributions in binary form must reproduce the above copyright 212497SN/A# notice, this list of conditions and the following disclaimer in the 222497SN/A# documentation and/or other materials provided with the distribution; 232497SN/A# neither the name of the copyright holders nor the names of its 242497SN/A# contributors may be used to endorse or promote products derived from 252497SN/A# this software without specific prior written permission. 262497SN/A# 272497SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 282497SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 292497SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 302497SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 312497SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 322497SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 332497SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 342497SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 352497SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 362497SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 372497SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 382497SN/A# 392665SN/A# Authors: Andreas Hansson 402665SN/A# Ani Udipi 418715SN/A 428922SN/Afrom m5.params import * 432497SN/Afrom AbstractMemory import * 442497SN/A 452497SN/A# Enum for memory scheduling algorithms, currently First-Come 462982SN/A# First-Served and a First-Row Hit then First-Come First-Served 4710405Sandreas.hansson@arm.comclass MemSched(Enum): vals = ['fcfs', 'frfcfs'] 482497SN/A 492497SN/A# Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting 502846SN/A# channel, rank, bank, row and column, respectively, and going from 512548SN/A# MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are 5210405Sandreas.hansson@arm.com# suitable for an open-page policy, optimising for sequential accesses 5310405Sandreas.hansson@arm.com# hitting in the open row. For a closed-page policy, RoCoRaBaCh 5410405Sandreas.hansson@arm.com# maximises parallelism. 559524SN/Aclass AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh'] 562497SN/A 5710405Sandreas.hansson@arm.com# Enum for the page policy, either open, open_adaptive, close, or 5810719SMarco.Balboni@ARM.com# close_adaptive. 5911334Sandreas.hansson@arm.comclass PageManage(Enum): vals = ['open', 'open_adaptive', 'close', 6011334Sandreas.hansson@arm.com 'close_adaptive'] 617523SN/A 628851SN/A# SimpleDRAM is a single-channel single-ported DRAM controller model 638948SN/A# that aims to model the most important system-level performance 648948SN/A# effects of a DRAM without getting into too much detail of the DRAM 658851SN/A# itself. 669095SN/Aclass SimpleDRAM(AbstractMemory): 6710405Sandreas.hansson@arm.com type = 'SimpleDRAM' 688922SN/A cxx_header = "mem/simple_dram.hh" 699715SN/A 709715SN/A # single-ported on the system interface side, instantiate with a 7110713Sandreas.hansson@arm.com # bus in front of the controller for multiple ports 7210713Sandreas.hansson@arm.com port = SlavePort("Slave port") 738851SN/A 748851SN/A # the basic configuration of the controller architecture 758948SN/A write_buffer_size = Param.Unsigned(64, "Number of write queue entries") 768948SN/A read_buffer_size = Param.Unsigned(32, "Number of read queue entries") 778915SN/A 789031SN/A # threshold in percent for when to forcefully trigger writes and 799095SN/A # start emptying the write buffer 8010405Sandreas.hansson@arm.com write_high_thresh_perc = Param.Percent(85, "Threshold to force writes") 819036SN/A 828922SN/A # threshold in percentage for when to start writes if the read 839715SN/A # queue is empty 849715SN/A write_low_thresh_perc = Param.Percent(50, "Threshold to start writes") 8510713Sandreas.hansson@arm.com 8610713Sandreas.hansson@arm.com # minimum write bursts to schedule before switching back to reads 8710713Sandreas.hansson@arm.com min_writes_per_switch = Param.Unsigned(16, "Minimum write bursts before " 888915SN/A "switching to reads") 898915SN/A 908948SN/A # scheduler, address map and page policy 918851SN/A mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy") 929095SN/A addr_mapping = Param.AddrMap('RoRaBaChCo', "Address mapping policy") 9310888Sandreas.hansson@arm.com page_policy = Param.PageManage('open_adaptive', "Page management policy") 948922SN/A 959715SN/A # enforce a limit on the number of accesses per row 969715SN/A max_accesses_per_row = Param.Unsigned(16, "Max accesses per row before " 979716SN/A "closing"); 988851SN/A 998851SN/A # pipeline latency of the controller and PHY, split into a 1007523SN/A # frontend part and a backend part, with reads and writes serviced 1017523SN/A # by the queues only seeing the frontend contribution, and reads 1027523SN/A # serviced by the memory seeing the sum of the two 10310405Sandreas.hansson@arm.com static_frontend_latency = Param.Latency("10ns", "Static frontend latency") 1049715SN/A static_backend_latency = Param.Latency("10ns", "Static backend latency") 10510405Sandreas.hansson@arm.com 10610405Sandreas.hansson@arm.com # the physical organisation of the DRAM 10710405Sandreas.hansson@arm.com device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\ 10810405Sandreas.hansson@arm.com "device/chip") 10910405Sandreas.hansson@arm.com burst_length = Param.Unsigned("Burst lenght (BL) in beats") 11010405Sandreas.hansson@arm.com device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\ 11110405Sandreas.hansson@arm.com "device/chip") 11210405Sandreas.hansson@arm.com devices_per_rank = Param.Unsigned("Number of devices/chips per rank") 1139715SN/A ranks_per_channel = Param.Unsigned("Number of ranks per channel") 1149715SN/A banks_per_rank = Param.Unsigned("Number of banks per rank") 1152568SN/A # only used for the address mapping as the controller by 11610405Sandreas.hansson@arm.com # construction is a single channel and multiple controllers have 1172568SN/A # to be instantiated for a multi-channel configuration 11810405Sandreas.hansson@arm.com channels = Param.Unsigned(1, "Number of channels") 1199278SN/A 1208948SN/A # timing behaviour and constraints - all in nanoseconds 1218948SN/A 12210405Sandreas.hansson@arm.com # the amount of time in nanoseconds from issuing an activate command 1239088SN/A # to the data being available in the row buffer for a read/write 12410405Sandreas.hansson@arm.com tRCD = Param.Latency("RAS to CAS delay") 12510405Sandreas.hansson@arm.com 12610405Sandreas.hansson@arm.com # the time from issuing a read/write command to seeing the actual data 12710405Sandreas.hansson@arm.com tCL = Param.Latency("CAS latency") 1288711SN/A 1298711SN/A # minimum time between a precharge and subsequent activate 1302568SN/A tRP = Param.Latency("Row precharge time") 1319036SN/A 13210405Sandreas.hansson@arm.com # minimum time between an activate and a precharge to the same row 13311133Sandreas.hansson@arm.com tRAS = Param.Latency("ACT to PRE delay") 13411133Sandreas.hansson@arm.com 13511133Sandreas.hansson@arm.com # time to complete a burst transfer, typically the burst length 13611133Sandreas.hansson@arm.com # divided by two due to the DDR bus, but by making it a parameter 13711133Sandreas.hansson@arm.com # it is easier to also evaluate SDR memories like WideIO. 1383244SN/A # This parameter has to account for burst length. 1393244SN/A # Read/Write requests with data size larger than one full burst are broken 1408948SN/A # down into multiple requests in the SimpleDRAM controller 14110405Sandreas.hansson@arm.com tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)") 1423244SN/A 1438975SN/A # time taken to complete one refresh cycle (N rows in all banks) 1449032SN/A tRFC = Param.Latency("Refresh cycle time") 1453244SN/A 1469091SN/A # refresh command interval, how often a "ref" command needs 1479091SN/A # to be sent. It is 7.8 us for a 64ms refresh requirement 14811284Sandreas.hansson@arm.com tREFI = Param.Latency("Refresh command interval") 14910656Sandreas.hansson@arm.com 15011284Sandreas.hansson@arm.com # write-to-read turn around penalty, assumed same as read-to-write 15111284Sandreas.hansson@arm.com tWTR = Param.Latency("Write to read switching time") 1529091SN/A 1539612SN/A # minimum row activate to row activate delay time 1549712SN/A tRRD = Param.Latency("ACT to ACT delay") 1559612SN/A 15610405Sandreas.hansson@arm.com # time window in which a maximum number of activates are allowed 1579033SN/A # to take place, set to 0 to disable 1589715SN/A tXAW = Param.Latency("X activation window") 15910405Sandreas.hansson@arm.com activation_limit = Param.Unsigned("Max number of activates in window") 1608949SN/A 1613244SN/A # Currently rolled into other params 1623244SN/A ###################################################################### 1633244SN/A 16410405Sandreas.hansson@arm.com # tRC - assumed to be tRAS + tRP 1659091SN/A 1669091SN/A# A single DDR3 x64 interface (one command and address bus), with 1675197SN/A# default timings based on DDR3-1600 4 Gbit parts in an 8x8 1689712SN/A# configuration, which would amount to 4 Gbyte of memory. 1699712SN/Aclass DDR3_1600_x64(SimpleDRAM): 1709712SN/A # 8x8 configuration, 8 devices each with an 8-bit interface 1719712SN/A device_bus_width = 8 1729712SN/A 17310719SMarco.Balboni@ARM.com # DDR3 is a BL8 device 17410719SMarco.Balboni@ARM.com burst_length = 8 17510719SMarco.Balboni@ARM.com 17610719SMarco.Balboni@ARM.com # Each device has a page (row buffer) size of 1KB 17710719SMarco.Balboni@ARM.com # (this depends on the memory density) 17810719SMarco.Balboni@ARM.com device_rowbuffer_size = '1kB' 17910719SMarco.Balboni@ARM.com 18010719SMarco.Balboni@ARM.com # 8x8 configuration, so 8 devices 18110719SMarco.Balboni@ARM.com devices_per_rank = 8 18210719SMarco.Balboni@ARM.com 18310719SMarco.Balboni@ARM.com # Use two ranks 1844912SN/A ranks_per_channel = 2 18510821Sandreas.hansson@arm.com 18611127Sandreas.hansson@arm.com # DDR3 has 8 banks in all configurations 18711127Sandreas.hansson@arm.com banks_per_rank = 8 1888979SN/A 1898979SN/A # DDR3-1600 11-11-11-28 19010402SN/A tRCD = '13.75ns' 19110402SN/A tCL = '13.75ns' 19210402SN/A tRP = '13.75ns' 19311126Sandreas.hansson@arm.com tRAS = '35ns' 19411126Sandreas.hansson@arm.com 19511126Sandreas.hansson@arm.com # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz. 19610719SMarco.Balboni@ARM.com # Note this is a BL8 DDR device. 19710405Sandreas.hansson@arm.com tBURST = '5ns' 19810402SN/A 19910402SN/A # DDR3, 4 Gbit has a tRFC of 240 CK and tCK = 1.25 ns 20010402SN/A tRFC = '300ns' 20111196Sali.jafri@arm.com 20211199Sandreas.hansson@arm.com # DDR3, <=85C, half for >85C 20311196Sali.jafri@arm.com tREFI = '7.8us' 20411196Sali.jafri@arm.com 20511196Sali.jafri@arm.com # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns 20611196Sali.jafri@arm.com tWTR = '7.5ns' 20711196Sali.jafri@arm.com 20811196Sali.jafri@arm.com # Assume 5 CK for activate to activate for different banks 20911196Sali.jafri@arm.com tRRD = '6.25ns' 21011196Sali.jafri@arm.com 21111196Sali.jafri@arm.com # With a 2kbyte page size, DDR3-1600 lands around 40 ns 21211196Sali.jafri@arm.com tXAW = '40ns' 21310402SN/A activation_limit = 4 21410402SN/A 21510402SN/A 21611127Sandreas.hansson@arm.com# A single DDR3 x64 interface (one command and address bus), with 21711127Sandreas.hansson@arm.com# default timings based on DDR3-1333 4 Gbit parts in an 8x8 21811127Sandreas.hansson@arm.com# configuration, which would amount to 4 GByte of memory. This 21911127Sandreas.hansson@arm.com# configuration is primarily for comparing with DRAMSim2, and all the 2208979SN/A# parameters except ranks_per_channel are based on the DRAMSim2 config 2218948SN/A# file DDR3_micron_32M_8B_x8_sg15.ini. Note that ranks_per_channel has 22211334Sandreas.hansson@arm.com# to be manually set, depending on size of the memory to be 22311334Sandreas.hansson@arm.com# simulated. By default DRAMSim2 has 2048MB of memory with a single 22410883Sali.jafri@arm.com# rank. Therefore for 4 GByte memory, set ranks_per_channel = 2 22511284Sandreas.hansson@arm.comclass DDR3_1333_x64_DRAMSim2(SimpleDRAM): 22611284Sandreas.hansson@arm.com # 8x8 configuration, 8 devices each with an 8-bit interface 22711284Sandreas.hansson@arm.com device_bus_width = 8 22811284Sandreas.hansson@arm.com 22911334Sandreas.hansson@arm.com # DDR3 is a BL8 device 2308915SN/A burst_length = 8 23111334Sandreas.hansson@arm.com 23211334Sandreas.hansson@arm.com # Each device has a page (row buffer) size of 1KB 23311334Sandreas.hansson@arm.com # (this depends on the memory density) 23411334Sandreas.hansson@arm.com device_rowbuffer_size = '1kB' 23511544Snikos.nikoleris@arm.com 23611544Snikos.nikoleris@arm.com # 8x8 configuration, so 8 devices 23711544Snikos.nikoleris@arm.com devices_per_rank = 8 23811334Sandreas.hansson@arm.com 23911334Sandreas.hansson@arm.com # Use two ranks 24011334Sandreas.hansson@arm.com ranks_per_channel = 2 24111334Sandreas.hansson@arm.com 24211334Sandreas.hansson@arm.com # DDR3 has 8 banks in all configurations 24311334Sandreas.hansson@arm.com banks_per_rank = 8 24411334Sandreas.hansson@arm.com 24511334Sandreas.hansson@arm.com tRCD = '15ns' 24611334Sandreas.hansson@arm.com tCL = '15ns' 24711334Sandreas.hansson@arm.com tRP = '15ns' 24811334Sandreas.hansson@arm.com tRAS = '36ns' 24911334Sandreas.hansson@arm.com 25011334Sandreas.hansson@arm.com # 8 beats across an x64 interface translates to 4 clocks @ 666.66 MHz. 25111334Sandreas.hansson@arm.com # Note this is a BL8 DDR device. 25211334Sandreas.hansson@arm.com tBURST = '6ns' 25311334Sandreas.hansson@arm.com 25411334Sandreas.hansson@arm.com tRFC = '160ns' 25511334Sandreas.hansson@arm.com 25611334Sandreas.hansson@arm.com # DDR3, <=85C, half for >85C 25711334Sandreas.hansson@arm.com tREFI = '7.8us' 25811334Sandreas.hansson@arm.com 25911334Sandreas.hansson@arm.com # Greater of 4 CK or 7.5 ns, 4 CK @ 666.66 MHz = 6 ns 26011334Sandreas.hansson@arm.com tWTR = '7.5ns' 26111334Sandreas.hansson@arm.com 26211334Sandreas.hansson@arm.com tRRD = '6.0ns' 26311334Sandreas.hansson@arm.com 26411334Sandreas.hansson@arm.com tXAW = '30ns' 26511334Sandreas.hansson@arm.com activation_limit = 4 2668948SN/A 26710821Sandreas.hansson@arm.com 26810402SN/A# A single LPDDR2-S4 x32 interface (one command/address bus), with 26911605Snikos.nikoleris@arm.com# default timings based on a LPDDR2-1066 4 Gbit part in a 1x32 27010402SN/A# configuration. 27110402SN/Aclass LPDDR2_S4_1066_x32(SimpleDRAM): 27210656Sandreas.hansson@arm.com # 1x32 configuration, 1 device with a 32-bit interface 27310656Sandreas.hansson@arm.com device_bus_width = 32 27411284Sandreas.hansson@arm.com 27510656Sandreas.hansson@arm.com # LPDDR2_S4 is a BL4 and BL8 device 27610656Sandreas.hansson@arm.com burst_length = 8 27710719SMarco.Balboni@ARM.com 27810719SMarco.Balboni@ARM.com # Each device has a page (row buffer) size of 1KB 27910656Sandreas.hansson@arm.com # (this depends on the memory density) 28010656Sandreas.hansson@arm.com device_rowbuffer_size = '1kB' 28110656Sandreas.hansson@arm.com 28210656Sandreas.hansson@arm.com # 1x32 configuration, so 1 device 28310656Sandreas.hansson@arm.com devices_per_rank = 1 28410656Sandreas.hansson@arm.com 28510719SMarco.Balboni@ARM.com # Use a single rank 2869091SN/A ranks_per_channel = 1 28710656Sandreas.hansson@arm.com 28810656Sandreas.hansson@arm.com # LPDDR2-S4 has 8 banks in all configurations 28910656Sandreas.hansson@arm.com banks_per_rank = 8 29010656Sandreas.hansson@arm.com 29110656Sandreas.hansson@arm.com # Fixed at 15 ns 29210656Sandreas.hansson@arm.com tRCD = '15ns' 29310656Sandreas.hansson@arm.com 29410656Sandreas.hansson@arm.com # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time 29510656Sandreas.hansson@arm.com tCL = '15ns' 2968948SN/A 29710656Sandreas.hansson@arm.com # Pre-charge one bank 15 ns (all banks 18 ns) 29810656Sandreas.hansson@arm.com tRP = '15ns' 29910656Sandreas.hansson@arm.com 30010656Sandreas.hansson@arm.com tRAS = '42ns' 3018948SN/A 30210656Sandreas.hansson@arm.com # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz. 30310656Sandreas.hansson@arm.com # Note this is a BL8 DDR device. 30410656Sandreas.hansson@arm.com # Requests larger than 32 bytes are broken down into multiple requests 30510656Sandreas.hansson@arm.com # in the SimpleDRAM controller 3069549SN/A tBURST = '7.5ns' 30710656Sandreas.hansson@arm.com 30810656Sandreas.hansson@arm.com # LPDDR2-S4, 4 Gbit 30910656Sandreas.hansson@arm.com tRFC = '130ns' 3108948SN/A tREFI = '3.9us' 31110405Sandreas.hansson@arm.com 3129715SN/A # Irrespective of speed grade, tWTR is 7.5 ns 3139091SN/A tWTR = '7.5ns' 3148975SN/A 31510656Sandreas.hansson@arm.com # Activate to activate irrespective of density and speed grade 3169712SN/A tRRD = '10.0ns' 31710405Sandreas.hansson@arm.com 3189712SN/A # Irrespective of density, tFAW is 50 ns 31910656Sandreas.hansson@arm.com tXAW = '50ns' 32011564Sdavid.guillen@arm.com activation_limit = 4 32110656Sandreas.hansson@arm.com 32211564Sdavid.guillen@arm.com# A single WideIO x128 interface (one command and address bus), with 32311564Sdavid.guillen@arm.com# default timings based on an estimated WIO-200 8 Gbit part. 3249712SN/Aclass WideIO_200_x128(SimpleDRAM): 3259712SN/A # 1x128 configuration, 1 device with a 128-bit interface 32611334Sandreas.hansson@arm.com device_bus_width = 128 32711334Sandreas.hansson@arm.com 32811334Sandreas.hansson@arm.com # This is a BL4 device 32911334Sandreas.hansson@arm.com burst_length = 4 33011334Sandreas.hansson@arm.com 33111334Sandreas.hansson@arm.com # Each device has a page (row buffer) size of 4KB 33211334Sandreas.hansson@arm.com # (this depends on the memory density) 33311334Sandreas.hansson@arm.com device_rowbuffer_size = '4kB' 33411334Sandreas.hansson@arm.com 33511334Sandreas.hansson@arm.com # 1x128 configuration, so 1 device 33611334Sandreas.hansson@arm.com devices_per_rank = 1 33711334Sandreas.hansson@arm.com 33811334Sandreas.hansson@arm.com # Use one rank for a one-high die stack 33911334Sandreas.hansson@arm.com ranks_per_channel = 1 34011334Sandreas.hansson@arm.com 34111334Sandreas.hansson@arm.com # WideIO has 4 banks in all configurations 34211334Sandreas.hansson@arm.com banks_per_rank = 4 34311334Sandreas.hansson@arm.com 34411334Sandreas.hansson@arm.com # WIO-200 34511334Sandreas.hansson@arm.com tRCD = '18ns' 34611334Sandreas.hansson@arm.com tCL = '18ns' 3479091SN/A tRP = '18ns' 3488975SN/A tRAS = '42ns' 3498975SN/A 3508975SN/A # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz. 35110405Sandreas.hansson@arm.com # Note this is a BL4 SDR device. 3528975SN/A tBURST = '20ns' 3538975SN/A 3549032SN/A # WIO 8 Gb 3558975SN/A tRFC = '210ns' 35610656Sandreas.hansson@arm.com 35710656Sandreas.hansson@arm.com # WIO 8 Gb, <=85C, half for >85C 35810656Sandreas.hansson@arm.com tREFI = '3.9us' 35910656Sandreas.hansson@arm.com 36010572Sandreas.hansson@arm.com # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns 36110572Sandreas.hansson@arm.com tWTR = '15ns' 3629713SN/A 36310405Sandreas.hansson@arm.com # Activate to activate irrespective of density and speed grade 36410405Sandreas.hansson@arm.com tRRD = '10.0ns' 3659715SN/A 36610405Sandreas.hansson@arm.com # Two instead of four activation window 3678975SN/A tXAW = '50ns' 3688975SN/A activation_limit = 2 3698975SN/A 3708975SN/A# A single LPDDR3 x32 interface (one command/address bus), with 37110405Sandreas.hansson@arm.com# default timings based on a LPDDR3-1600 4 Gbit part in a 1x32 3728975SN/A# configuration 3738975SN/Aclass LPDDR3_1600_x32(SimpleDRAM): 3749712SN/A # 1x32 configuration, 1 device with a 32-bit interface 3759712SN/A device_bus_width = 32 3769712SN/A 3779712SN/A # LPDDR3 is a BL8 device 3789712SN/A burst_length = 8 37910719SMarco.Balboni@ARM.com 38010719SMarco.Balboni@ARM.com # Each device has a page (row buffer) size of 4KB 38110719SMarco.Balboni@ARM.com device_rowbuffer_size = '4kB' 38210719SMarco.Balboni@ARM.com 38310719SMarco.Balboni@ARM.com # 1x32 configuration, so 1 device 38410719SMarco.Balboni@ARM.com devices_per_rank = 1 38510719SMarco.Balboni@ARM.com 38610719SMarco.Balboni@ARM.com # Use a single rank 3878975SN/A ranks_per_channel = 1 38810821Sandreas.hansson@arm.com 38910402SN/A # LPDDR3 has 8 banks in all configurations 39010402SN/A banks_per_rank = 8 39110402SN/A 39210402SN/A # Fixed at 15 ns 39310888Sandreas.hansson@arm.com tRCD = '15ns' 39410888Sandreas.hansson@arm.com 39510888Sandreas.hansson@arm.com # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time 39610888Sandreas.hansson@arm.com tCL = '15ns' 39710888Sandreas.hansson@arm.com 3988975SN/A tRAS = '42ns' 39910656Sandreas.hansson@arm.com 40010656Sandreas.hansson@arm.com # Pre-charge one bank 15 ns (all banks 18 ns) 40110656Sandreas.hansson@arm.com tRP = '15ns' 4029715SN/A 4038975SN/A # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz. 4049712SN/A # Note this is a BL8 DDR device. 4059712SN/A # Requests larger than 32 bytes are broken down into multiple requests 40610405Sandreas.hansson@arm.com # in the SimpleDRAM controller 4079712SN/A tBURST = '5ns' 4089712SN/A 4098975SN/A # LPDDR3, 4 Gb 4108975SN/A tRFC = '130ns' 4118975SN/A tREFI = '3.9us' 4128975SN/A 41310405Sandreas.hansson@arm.com # Irrespective of speed grade, tWTR is 7.5 ns 4148975SN/A tWTR = '7.5ns' 41510405Sandreas.hansson@arm.com 4169032SN/A # Activate to activate irrespective of density and speed grade 4178975SN/A tRRD = '10.0ns' 4188975SN/A 4199712SN/A # Irrespective of size, tFAW is 50 ns 42011564Sdavid.guillen@arm.com tXAW = '50ns' 4219712SN/A activation_limit = 4 42210405Sandreas.hansson@arm.com