DRAMCtrl.py revision 10145
1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2013 Amin Farmahini-Farahani 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Andreas Hansson 40# Ani Udipi 41 42from m5.params import * 43from AbstractMemory import * 44 45# Enum for memory scheduling algorithms, currently First-Come 46# First-Served and a First-Row Hit then First-Come First-Served 47class MemSched(Enum): vals = ['fcfs', 'frfcfs'] 48 49# Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting 50# channel, rank, bank, row and column, respectively, and going from 51# MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are 52# suitable for an open-page policy, optimising for sequential accesses 53# hitting in the open row. For a closed-page policy, RoCoRaBaCh 54# maximises parallelism. 55class AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh'] 56 57# Enum for the page policy, either open, open_adaptive, close, or 58# close_adaptive. 59class PageManage(Enum): vals = ['open', 'open_adaptive', 'close', 60 'close_adaptive'] 61 62# SimpleDRAM is a single-channel single-ported DRAM controller model 63# that aims to model the most important system-level performance 64# effects of a DRAM without getting into too much detail of the DRAM 65# itself. 66class SimpleDRAM(AbstractMemory): 67 type = 'SimpleDRAM' 68 cxx_header = "mem/simple_dram.hh" 69 70 # single-ported on the system interface side, instantiate with a 71 # bus in front of the controller for multiple ports 72 port = SlavePort("Slave port") 73 74 # the basic configuration of the controller architecture 75 write_buffer_size = Param.Unsigned(64, "Number of write queue entries") 76 read_buffer_size = Param.Unsigned(32, "Number of read queue entries") 77 78 # threshold in percent for when to forcefully trigger writes and 79 # start emptying the write buffer 80 write_high_thresh_perc = Param.Percent(85, "Threshold to force writes") 81 82 # threshold in percentage for when to start writes if the read 83 # queue is empty 84 write_low_thresh_perc = Param.Percent(50, "Threshold to start writes") 85 86 # minimum write bursts to schedule before switching back to reads 87 min_writes_per_switch = Param.Unsigned(16, "Minimum write bursts before " 88 "switching to reads") 89 90 # scheduler, address map and page policy 91 mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy") 92 addr_mapping = Param.AddrMap('RoRaBaChCo', "Address mapping policy") 93 page_policy = Param.PageManage('open_adaptive', "Page management policy") 94 95 # enforce a limit on the number of accesses per row 96 max_accesses_per_row = Param.Unsigned(16, "Max accesses per row before " 97 "closing"); 98 99 # pipeline latency of the controller and PHY, split into a 100 # frontend part and a backend part, with reads and writes serviced 101 # by the queues only seeing the frontend contribution, and reads 102 # serviced by the memory seeing the sum of the two 103 static_frontend_latency = Param.Latency("10ns", "Static frontend latency") 104 static_backend_latency = Param.Latency("10ns", "Static backend latency") 105 106 # the physical organisation of the DRAM 107 device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\ 108 "device/chip") 109 burst_length = Param.Unsigned("Burst lenght (BL) in beats") 110 device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\ 111 "device/chip") 112 devices_per_rank = Param.Unsigned("Number of devices/chips per rank") 113 ranks_per_channel = Param.Unsigned("Number of ranks per channel") 114 banks_per_rank = Param.Unsigned("Number of banks per rank") 115 # only used for the address mapping as the controller by 116 # construction is a single channel and multiple controllers have 117 # to be instantiated for a multi-channel configuration 118 channels = Param.Unsigned(1, "Number of channels") 119 120 # timing behaviour and constraints - all in nanoseconds 121 122 # the amount of time in nanoseconds from issuing an activate command 123 # to the data being available in the row buffer for a read/write 124 tRCD = Param.Latency("RAS to CAS delay") 125 126 # the time from issuing a read/write command to seeing the actual data 127 tCL = Param.Latency("CAS latency") 128 129 # minimum time between a precharge and subsequent activate 130 tRP = Param.Latency("Row precharge time") 131 132 # minimum time between an activate and a precharge to the same row 133 tRAS = Param.Latency("ACT to PRE delay") 134 135 # time to complete a burst transfer, typically the burst length 136 # divided by two due to the DDR bus, but by making it a parameter 137 # it is easier to also evaluate SDR memories like WideIO. 138 # This parameter has to account for burst length. 139 # Read/Write requests with data size larger than one full burst are broken 140 # down into multiple requests in the SimpleDRAM controller 141 tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)") 142 143 # time taken to complete one refresh cycle (N rows in all banks) 144 tRFC = Param.Latency("Refresh cycle time") 145 146 # refresh command interval, how often a "ref" command needs 147 # to be sent. It is 7.8 us for a 64ms refresh requirement 148 tREFI = Param.Latency("Refresh command interval") 149 150 # write-to-read turn around penalty, assumed same as read-to-write 151 tWTR = Param.Latency("Write to read switching time") 152 153 # minimum row activate to row activate delay time 154 tRRD = Param.Latency("ACT to ACT delay") 155 156 # time window in which a maximum number of activates are allowed 157 # to take place, set to 0 to disable 158 tXAW = Param.Latency("X activation window") 159 activation_limit = Param.Unsigned("Max number of activates in window") 160 161 # Currently rolled into other params 162 ###################################################################### 163 164 # tRC - assumed to be tRAS + tRP 165 166# A single DDR3 x64 interface (one command and address bus), with 167# default timings based on DDR3-1600 4 Gbit parts in an 8x8 168# configuration, which would amount to 4 Gbyte of memory. 169class DDR3_1600_x64(SimpleDRAM): 170 # 8x8 configuration, 8 devices each with an 8-bit interface 171 device_bus_width = 8 172 173 # DDR3 is a BL8 device 174 burst_length = 8 175 176 # Each device has a page (row buffer) size of 1KB 177 # (this depends on the memory density) 178 device_rowbuffer_size = '1kB' 179 180 # 8x8 configuration, so 8 devices 181 devices_per_rank = 8 182 183 # Use two ranks 184 ranks_per_channel = 2 185 186 # DDR3 has 8 banks in all configurations 187 banks_per_rank = 8 188 189 # DDR3-1600 11-11-11-28 190 tRCD = '13.75ns' 191 tCL = '13.75ns' 192 tRP = '13.75ns' 193 tRAS = '35ns' 194 195 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz. 196 # Note this is a BL8 DDR device. 197 tBURST = '5ns' 198 199 # DDR3, 4 Gbit has a tRFC of 240 CK and tCK = 1.25 ns 200 tRFC = '300ns' 201 202 # DDR3, <=85C, half for >85C 203 tREFI = '7.8us' 204 205 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns 206 tWTR = '7.5ns' 207 208 # Assume 5 CK for activate to activate for different banks 209 tRRD = '6.25ns' 210 211 # With a 2kbyte page size, DDR3-1600 lands around 40 ns 212 tXAW = '40ns' 213 activation_limit = 4 214 215 216# A single DDR3 x64 interface (one command and address bus), with 217# default timings based on DDR3-1333 4 Gbit parts in an 8x8 218# configuration, which would amount to 4 GByte of memory. This 219# configuration is primarily for comparing with DRAMSim2, and all the 220# parameters except ranks_per_channel are based on the DRAMSim2 config 221# file DDR3_micron_32M_8B_x8_sg15.ini. Note that ranks_per_channel has 222# to be manually set, depending on size of the memory to be 223# simulated. By default DRAMSim2 has 2048MB of memory with a single 224# rank. Therefore for 4 GByte memory, set ranks_per_channel = 2 225class DDR3_1333_x64_DRAMSim2(SimpleDRAM): 226 # 8x8 configuration, 8 devices each with an 8-bit interface 227 device_bus_width = 8 228 229 # DDR3 is a BL8 device 230 burst_length = 8 231 232 # Each device has a page (row buffer) size of 1KB 233 # (this depends on the memory density) 234 device_rowbuffer_size = '1kB' 235 236 # 8x8 configuration, so 8 devices 237 devices_per_rank = 8 238 239 # Use two ranks 240 ranks_per_channel = 2 241 242 # DDR3 has 8 banks in all configurations 243 banks_per_rank = 8 244 245 tRCD = '15ns' 246 tCL = '15ns' 247 tRP = '15ns' 248 tRAS = '36ns' 249 250 # 8 beats across an x64 interface translates to 4 clocks @ 666.66 MHz. 251 # Note this is a BL8 DDR device. 252 tBURST = '6ns' 253 254 tRFC = '160ns' 255 256 # DDR3, <=85C, half for >85C 257 tREFI = '7.8us' 258 259 # Greater of 4 CK or 7.5 ns, 4 CK @ 666.66 MHz = 6 ns 260 tWTR = '7.5ns' 261 262 tRRD = '6.0ns' 263 264 tXAW = '30ns' 265 activation_limit = 4 266 267 268# A single LPDDR2-S4 x32 interface (one command/address bus), with 269# default timings based on a LPDDR2-1066 4 Gbit part in a 1x32 270# configuration. 271class LPDDR2_S4_1066_x32(SimpleDRAM): 272 # 1x32 configuration, 1 device with a 32-bit interface 273 device_bus_width = 32 274 275 # LPDDR2_S4 is a BL4 and BL8 device 276 burst_length = 8 277 278 # Each device has a page (row buffer) size of 1KB 279 # (this depends on the memory density) 280 device_rowbuffer_size = '1kB' 281 282 # 1x32 configuration, so 1 device 283 devices_per_rank = 1 284 285 # Use a single rank 286 ranks_per_channel = 1 287 288 # LPDDR2-S4 has 8 banks in all configurations 289 banks_per_rank = 8 290 291 # Fixed at 15 ns 292 tRCD = '15ns' 293 294 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time 295 tCL = '15ns' 296 297 # Pre-charge one bank 15 ns (all banks 18 ns) 298 tRP = '15ns' 299 300 tRAS = '42ns' 301 302 # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz. 303 # Note this is a BL8 DDR device. 304 # Requests larger than 32 bytes are broken down into multiple requests 305 # in the SimpleDRAM controller 306 tBURST = '7.5ns' 307 308 # LPDDR2-S4, 4 Gbit 309 tRFC = '130ns' 310 tREFI = '3.9us' 311 312 # Irrespective of speed grade, tWTR is 7.5 ns 313 tWTR = '7.5ns' 314 315 # Activate to activate irrespective of density and speed grade 316 tRRD = '10.0ns' 317 318 # Irrespective of density, tFAW is 50 ns 319 tXAW = '50ns' 320 activation_limit = 4 321 322# A single WideIO x128 interface (one command and address bus), with 323# default timings based on an estimated WIO-200 8 Gbit part. 324class WideIO_200_x128(SimpleDRAM): 325 # 1x128 configuration, 1 device with a 128-bit interface 326 device_bus_width = 128 327 328 # This is a BL4 device 329 burst_length = 4 330 331 # Each device has a page (row buffer) size of 4KB 332 # (this depends on the memory density) 333 device_rowbuffer_size = '4kB' 334 335 # 1x128 configuration, so 1 device 336 devices_per_rank = 1 337 338 # Use one rank for a one-high die stack 339 ranks_per_channel = 1 340 341 # WideIO has 4 banks in all configurations 342 banks_per_rank = 4 343 344 # WIO-200 345 tRCD = '18ns' 346 tCL = '18ns' 347 tRP = '18ns' 348 tRAS = '42ns' 349 350 # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz. 351 # Note this is a BL4 SDR device. 352 tBURST = '20ns' 353 354 # WIO 8 Gb 355 tRFC = '210ns' 356 357 # WIO 8 Gb, <=85C, half for >85C 358 tREFI = '3.9us' 359 360 # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns 361 tWTR = '15ns' 362 363 # Activate to activate irrespective of density and speed grade 364 tRRD = '10.0ns' 365 366 # Two instead of four activation window 367 tXAW = '50ns' 368 activation_limit = 2 369 370# A single LPDDR3 x32 interface (one command/address bus), with 371# default timings based on a LPDDR3-1600 4 Gbit part in a 1x32 372# configuration 373class LPDDR3_1600_x32(SimpleDRAM): 374 # 1x32 configuration, 1 device with a 32-bit interface 375 device_bus_width = 32 376 377 # LPDDR3 is a BL8 device 378 burst_length = 8 379 380 # Each device has a page (row buffer) size of 4KB 381 device_rowbuffer_size = '4kB' 382 383 # 1x32 configuration, so 1 device 384 devices_per_rank = 1 385 386 # Use a single rank 387 ranks_per_channel = 1 388 389 # LPDDR3 has 8 banks in all configurations 390 banks_per_rank = 8 391 392 # Fixed at 15 ns 393 tRCD = '15ns' 394 395 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time 396 tCL = '15ns' 397 398 tRAS = '42ns' 399 400 # Pre-charge one bank 15 ns (all banks 18 ns) 401 tRP = '15ns' 402 403 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz. 404 # Note this is a BL8 DDR device. 405 # Requests larger than 32 bytes are broken down into multiple requests 406 # in the SimpleDRAM controller 407 tBURST = '5ns' 408 409 # LPDDR3, 4 Gb 410 tRFC = '130ns' 411 tREFI = '3.9us' 412 413 # Irrespective of speed grade, tWTR is 7.5 ns 414 tWTR = '7.5ns' 415 416 # Activate to activate irrespective of density and speed grade 417 tRRD = '10.0ns' 418 419 # Irrespective of size, tFAW is 50 ns 420 tXAW = '50ns' 421 activation_limit = 4 422