DRAMCtrl.py revision 10140
111986Sandreas.sandberg@arm.com# Copyright (c) 2012-2013 ARM Limited
211986Sandreas.sandberg@arm.com# All rights reserved.
311986Sandreas.sandberg@arm.com#
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511986Sandreas.sandberg@arm.com# not be construed as granting a license to any other intellectual
611986Sandreas.sandberg@arm.com# property including but not limited to intellectual property relating
711986Sandreas.sandberg@arm.com# to a hardware implementation of the functionality of the software
811986Sandreas.sandberg@arm.com# licensed hereunder.  You may use the software subject to the license
911986Sandreas.sandberg@arm.com# terms below provided that you ensure that this notice is replicated
1011986Sandreas.sandberg@arm.com# unmodified and in its entirety in all distributions of the software,
1111986Sandreas.sandberg@arm.com# modified or unmodified, in source code or in binary form.
1211986Sandreas.sandberg@arm.com#
1311986Sandreas.sandberg@arm.com# Copyright (c) 2013 Amin Farmahini-Farahani
1411986Sandreas.sandberg@arm.com# All rights reserved.
1511986Sandreas.sandberg@arm.com#
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1711986Sandreas.sandberg@arm.com# modification, are permitted provided that the following conditions are
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2011986Sandreas.sandberg@arm.com# redistributions in binary form must reproduce the above copyright
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2511986Sandreas.sandberg@arm.com# this software without specific prior written permission.
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3711986Sandreas.sandberg@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3811986Sandreas.sandberg@arm.com#
3911986Sandreas.sandberg@arm.com# Authors: Andreas Hansson
4011986Sandreas.sandberg@arm.com#          Ani Udipi
4111986Sandreas.sandberg@arm.com
4211986Sandreas.sandberg@arm.comfrom m5.params import *
4311986Sandreas.sandberg@arm.comfrom AbstractMemory import *
4411986Sandreas.sandberg@arm.com
4511986Sandreas.sandberg@arm.com# Enum for memory scheduling algorithms, currently First-Come
4611986Sandreas.sandberg@arm.com# First-Served and a First-Row Hit then First-Come First-Served
4711986Sandreas.sandberg@arm.comclass MemSched(Enum): vals = ['fcfs', 'frfcfs']
4811986Sandreas.sandberg@arm.com
4911986Sandreas.sandberg@arm.com# Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting
5011986Sandreas.sandberg@arm.com# channel, rank, bank, row and column, respectively, and going from
5111986Sandreas.sandberg@arm.com# MSB to LSB.  Available are RoRaBaChCo and RoRaBaCoCh, that are
5211986Sandreas.sandberg@arm.com# suitable for an open-page policy, optimising for sequential accesses
5311986Sandreas.sandberg@arm.com# hitting in the open row. For a closed-page policy, RoCoRaBaCh
5411986Sandreas.sandberg@arm.com# maximises parallelism.
5511986Sandreas.sandberg@arm.comclass AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh']
5611986Sandreas.sandberg@arm.com
5711986Sandreas.sandberg@arm.com# Enum for the page policy, either open, open_adaptive or close.
5811986Sandreas.sandberg@arm.comclass PageManage(Enum): vals = ['open', 'open_adaptive', 'close']
5911986Sandreas.sandberg@arm.com
6011986Sandreas.sandberg@arm.com# SimpleDRAM is a single-channel single-ported DRAM controller model
6111986Sandreas.sandberg@arm.com# that aims to model the most important system-level performance
6211986Sandreas.sandberg@arm.com# effects of a DRAM without getting into too much detail of the DRAM
6311986Sandreas.sandberg@arm.com# itself.
6411986Sandreas.sandberg@arm.comclass SimpleDRAM(AbstractMemory):
6511986Sandreas.sandberg@arm.com    type = 'SimpleDRAM'
6611986Sandreas.sandberg@arm.com    cxx_header = "mem/simple_dram.hh"
6711986Sandreas.sandberg@arm.com
6811986Sandreas.sandberg@arm.com    # single-ported on the system interface side, instantiate with a
6911986Sandreas.sandberg@arm.com    # bus in front of the controller for multiple ports
7011986Sandreas.sandberg@arm.com    port = SlavePort("Slave port")
7111986Sandreas.sandberg@arm.com
7211986Sandreas.sandberg@arm.com    # the basic configuration of the controller architecture
7311986Sandreas.sandberg@arm.com    write_buffer_size = Param.Unsigned(32, "Number of write queue entries")
7411986Sandreas.sandberg@arm.com    read_buffer_size = Param.Unsigned(32, "Number of read queue entries")
7511986Sandreas.sandberg@arm.com
7611986Sandreas.sandberg@arm.com    # threshold in percent for when to forcefully trigger writes and
7711986Sandreas.sandberg@arm.com    # start emptying the write buffer
7811986Sandreas.sandberg@arm.com    write_high_thresh_perc = Param.Percent(85, "Threshold to force writes")
7911986Sandreas.sandberg@arm.com
8011986Sandreas.sandberg@arm.com    # threshold in percentage for when to start writes if the read
8111986Sandreas.sandberg@arm.com    # queue is empty
8211986Sandreas.sandberg@arm.com    write_low_thresh_perc = Param.Percent(50, "Threshold to start writes")
8311986Sandreas.sandberg@arm.com
8411986Sandreas.sandberg@arm.com    # minimum write bursts to schedule before switching back to reads
8511986Sandreas.sandberg@arm.com    min_writes_per_switch = Param.Unsigned(16, "Minimum write bursts before "
8611986Sandreas.sandberg@arm.com                                           "switching to reads")
8711986Sandreas.sandberg@arm.com
8811986Sandreas.sandberg@arm.com    # scheduler, address map and page policy
8911986Sandreas.sandberg@arm.com    mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy")
9011986Sandreas.sandberg@arm.com    addr_mapping = Param.AddrMap('RoRaBaChCo', "Address mapping policy")
9111986Sandreas.sandberg@arm.com    page_policy = Param.PageManage('open', "Page closure management policy")
9211986Sandreas.sandberg@arm.com
9311986Sandreas.sandberg@arm.com    # pipeline latency of the controller and PHY, split into a
9411986Sandreas.sandberg@arm.com    # frontend part and a backend part, with reads and writes serviced
9511986Sandreas.sandberg@arm.com    # by the queues only seeing the frontend contribution, and reads
9611986Sandreas.sandberg@arm.com    # serviced by the memory seeing the sum of the two
9711986Sandreas.sandberg@arm.com    static_frontend_latency = Param.Latency("10ns", "Static frontend latency")
9811986Sandreas.sandberg@arm.com    static_backend_latency = Param.Latency("10ns", "Static backend latency")
9911986Sandreas.sandberg@arm.com
10011986Sandreas.sandberg@arm.com    # the physical organisation of the DRAM
10111986Sandreas.sandberg@arm.com    device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\
10211986Sandreas.sandberg@arm.com                                      "device/chip")
10311986Sandreas.sandberg@arm.com    burst_length = Param.Unsigned("Burst lenght (BL) in beats")
10411986Sandreas.sandberg@arm.com    device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\
10511986Sandreas.sandberg@arm.com                                           "device/chip")
10611986Sandreas.sandberg@arm.com    devices_per_rank = Param.Unsigned("Number of devices/chips per rank")
10711986Sandreas.sandberg@arm.com    ranks_per_channel = Param.Unsigned("Number of ranks per channel")
10811986Sandreas.sandberg@arm.com    banks_per_rank = Param.Unsigned("Number of banks per rank")
10911986Sandreas.sandberg@arm.com    # only used for the address mapping as the controller by
11011986Sandreas.sandberg@arm.com    # construction is a single channel and multiple controllers have
11111986Sandreas.sandberg@arm.com    # to be instantiated for a multi-channel configuration
11211986Sandreas.sandberg@arm.com    channels = Param.Unsigned(1, "Number of channels")
11311986Sandreas.sandberg@arm.com
11411986Sandreas.sandberg@arm.com    # timing behaviour and constraints - all in nanoseconds
11511986Sandreas.sandberg@arm.com
11611986Sandreas.sandberg@arm.com    # the amount of time in nanoseconds from issuing an activate command
11711986Sandreas.sandberg@arm.com    # to the data being available in the row buffer for a read/write
11811986Sandreas.sandberg@arm.com    tRCD = Param.Latency("RAS to CAS delay")
11911986Sandreas.sandberg@arm.com
12011986Sandreas.sandberg@arm.com    # the time from issuing a read/write command to seeing the actual data
12111986Sandreas.sandberg@arm.com    tCL = Param.Latency("CAS latency")
12211986Sandreas.sandberg@arm.com
12311986Sandreas.sandberg@arm.com    # minimum time between a precharge and subsequent activate
12411986Sandreas.sandberg@arm.com    tRP = Param.Latency("Row precharge time")
12511986Sandreas.sandberg@arm.com
12611986Sandreas.sandberg@arm.com    # minimum time between an activate and a precharge to the same row
12711986Sandreas.sandberg@arm.com    tRAS = Param.Latency("ACT to PRE delay")
12811986Sandreas.sandberg@arm.com
12911986Sandreas.sandberg@arm.com    # time to complete a burst transfer, typically the burst length
13011986Sandreas.sandberg@arm.com    # divided by two due to the DDR bus, but by making it a parameter
13111986Sandreas.sandberg@arm.com    # it is easier to also evaluate SDR memories like WideIO.
13211986Sandreas.sandberg@arm.com    # This parameter has to account for burst length.
13311986Sandreas.sandberg@arm.com    # Read/Write requests with data size larger than one full burst are broken
13411986Sandreas.sandberg@arm.com    # down into multiple requests in the SimpleDRAM controller
13511986Sandreas.sandberg@arm.com    tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)")
13611986Sandreas.sandberg@arm.com
13711986Sandreas.sandberg@arm.com    # time taken to complete one refresh cycle (N rows in all banks)
13811986Sandreas.sandberg@arm.com    tRFC = Param.Latency("Refresh cycle time")
13911986Sandreas.sandberg@arm.com
14011986Sandreas.sandberg@arm.com    # refresh command interval, how often a "ref" command needs
14111986Sandreas.sandberg@arm.com    # to be sent. It is 7.8 us for a 64ms refresh requirement
14211986Sandreas.sandberg@arm.com    tREFI = Param.Latency("Refresh command interval")
14311986Sandreas.sandberg@arm.com
14411986Sandreas.sandberg@arm.com    # write-to-read turn around penalty, assumed same as read-to-write
14511986Sandreas.sandberg@arm.com    tWTR = Param.Latency("Write to read switching time")
14611986Sandreas.sandberg@arm.com
14711986Sandreas.sandberg@arm.com    # minimum row activate to row activate delay time
14811986Sandreas.sandberg@arm.com    tRRD = Param.Latency("ACT to ACT delay")
14911986Sandreas.sandberg@arm.com
15011986Sandreas.sandberg@arm.com    # time window in which a maximum number of activates are allowed
15111986Sandreas.sandberg@arm.com    # to take place, set to 0 to disable
15211986Sandreas.sandberg@arm.com    tXAW = Param.Latency("X activation window")
15311986Sandreas.sandberg@arm.com    activation_limit = Param.Unsigned("Max number of activates in window")
15411986Sandreas.sandberg@arm.com
15511986Sandreas.sandberg@arm.com    # Currently rolled into other params
15611986Sandreas.sandberg@arm.com    ######################################################################
15711986Sandreas.sandberg@arm.com
15811986Sandreas.sandberg@arm.com    # tRC  - assumed to be tRAS + tRP
15911986Sandreas.sandberg@arm.com
16011986Sandreas.sandberg@arm.com# A single DDR3 x64 interface (one command and address bus), with
16111986Sandreas.sandberg@arm.com# default timings based on DDR3-1600 4 Gbit parts in an 8x8
16211986Sandreas.sandberg@arm.com# configuration, which would amount to 4 Gbyte of memory.
16311986Sandreas.sandberg@arm.comclass DDR3_1600_x64(SimpleDRAM):
16411986Sandreas.sandberg@arm.com    # 8x8 configuration, 8 devices each with an 8-bit interface
16511986Sandreas.sandberg@arm.com    device_bus_width = 8
16611986Sandreas.sandberg@arm.com
16711986Sandreas.sandberg@arm.com    # DDR3 is a BL8 device
16811986Sandreas.sandberg@arm.com    burst_length = 8
16911986Sandreas.sandberg@arm.com
17011986Sandreas.sandberg@arm.com    # Each device has a page (row buffer) size of 1KB
17111986Sandreas.sandberg@arm.com    # (this depends on the memory density)
17211986Sandreas.sandberg@arm.com    device_rowbuffer_size = '1kB'
17311986Sandreas.sandberg@arm.com
17411986Sandreas.sandberg@arm.com    # 8x8 configuration, so 8 devices
17511986Sandreas.sandberg@arm.com    devices_per_rank = 8
17611986Sandreas.sandberg@arm.com
17711986Sandreas.sandberg@arm.com    # Use two ranks
17811986Sandreas.sandberg@arm.com    ranks_per_channel = 2
17911986Sandreas.sandberg@arm.com
18011986Sandreas.sandberg@arm.com    # DDR3 has 8 banks in all configurations
18111986Sandreas.sandberg@arm.com    banks_per_rank = 8
18211986Sandreas.sandberg@arm.com
18311986Sandreas.sandberg@arm.com    # DDR3-1600 11-11-11-28
18411986Sandreas.sandberg@arm.com    tRCD = '13.75ns'
18511986Sandreas.sandberg@arm.com    tCL = '13.75ns'
18611986Sandreas.sandberg@arm.com    tRP = '13.75ns'
18711986Sandreas.sandberg@arm.com    tRAS = '35ns'
18811986Sandreas.sandberg@arm.com
18911986Sandreas.sandberg@arm.com    # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz.
19011986Sandreas.sandberg@arm.com    # Note this is a BL8 DDR device.
19111986Sandreas.sandberg@arm.com    tBURST = '5ns'
19211986Sandreas.sandberg@arm.com
19311986Sandreas.sandberg@arm.com    # DDR3, 4 Gbit has a tRFC of 240 CK and tCK = 1.25 ns
19411986Sandreas.sandberg@arm.com    tRFC = '300ns'
19511986Sandreas.sandberg@arm.com
19611986Sandreas.sandberg@arm.com    # DDR3, <=85C, half for >85C
19711986Sandreas.sandberg@arm.com    tREFI = '7.8us'
19811986Sandreas.sandberg@arm.com
19911986Sandreas.sandberg@arm.com    # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
20011986Sandreas.sandberg@arm.com    tWTR = '7.5ns'
20111986Sandreas.sandberg@arm.com
20211986Sandreas.sandberg@arm.com    # Assume 5 CK for activate to activate for different banks
20311986Sandreas.sandberg@arm.com    tRRD = '6.25ns'
20411986Sandreas.sandberg@arm.com
20511986Sandreas.sandberg@arm.com    # With a 2kbyte page size, DDR3-1600 lands around 40 ns
20611986Sandreas.sandberg@arm.com    tXAW = '40ns'
20711986Sandreas.sandberg@arm.com    activation_limit = 4
20811986Sandreas.sandberg@arm.com
20911986Sandreas.sandberg@arm.com
21011986Sandreas.sandberg@arm.com# A single DDR3 x64 interface (one command and address bus), with
21111986Sandreas.sandberg@arm.com# default timings based on DDR3-1333 4 Gbit parts in an 8x8
21211986Sandreas.sandberg@arm.com# configuration, which would amount to 4 GByte of memory.  This
21311986Sandreas.sandberg@arm.com# configuration is primarily for comparing with DRAMSim2, and all the
21411986Sandreas.sandberg@arm.com# parameters except ranks_per_channel are based on the DRAMSim2 config
21511986Sandreas.sandberg@arm.com# file DDR3_micron_32M_8B_x8_sg15.ini. Note that ranks_per_channel has
21611986Sandreas.sandberg@arm.com# to be manually set, depending on size of the memory to be
21711986Sandreas.sandberg@arm.com# simulated. By default DRAMSim2 has 2048MB of memory with a single
21811986Sandreas.sandberg@arm.com# rank. Therefore for 4 GByte memory, set ranks_per_channel = 2
21911986Sandreas.sandberg@arm.comclass DDR3_1333_x64_DRAMSim2(SimpleDRAM):
22011986Sandreas.sandberg@arm.com    # 8x8 configuration, 8 devices each with an 8-bit interface
22111986Sandreas.sandberg@arm.com    device_bus_width = 8
22211986Sandreas.sandberg@arm.com
22311986Sandreas.sandberg@arm.com    # DDR3 is a BL8 device
22411986Sandreas.sandberg@arm.com    burst_length = 8
22511986Sandreas.sandberg@arm.com
22611986Sandreas.sandberg@arm.com    # Each device has a page (row buffer) size of 1KB
22711986Sandreas.sandberg@arm.com    # (this depends on the memory density)
22811986Sandreas.sandberg@arm.com    device_rowbuffer_size = '1kB'
22911986Sandreas.sandberg@arm.com
23011986Sandreas.sandberg@arm.com    # 8x8 configuration, so 8 devices
23111986Sandreas.sandberg@arm.com    devices_per_rank = 8
23211986Sandreas.sandberg@arm.com
23311986Sandreas.sandberg@arm.com    # Use two ranks
23411986Sandreas.sandberg@arm.com    ranks_per_channel = 2
23511986Sandreas.sandberg@arm.com
23611986Sandreas.sandberg@arm.com    # DDR3 has 8 banks in all configurations
23711986Sandreas.sandberg@arm.com    banks_per_rank = 8
23811986Sandreas.sandberg@arm.com
23911986Sandreas.sandberg@arm.com    tRCD = '15ns'
24011986Sandreas.sandberg@arm.com    tCL = '15ns'
24111986Sandreas.sandberg@arm.com    tRP = '15ns'
24211986Sandreas.sandberg@arm.com    tRAS = '36ns'
24311986Sandreas.sandberg@arm.com
24411986Sandreas.sandberg@arm.com    # 8 beats across an x64 interface translates to 4 clocks @ 666.66 MHz.
24511986Sandreas.sandberg@arm.com    # Note this is a BL8 DDR device.
24611986Sandreas.sandberg@arm.com    tBURST = '6ns'
24711986Sandreas.sandberg@arm.com
24811986Sandreas.sandberg@arm.com    tRFC = '160ns'
24911986Sandreas.sandberg@arm.com
25011986Sandreas.sandberg@arm.com    # DDR3, <=85C, half for >85C
25111986Sandreas.sandberg@arm.com    tREFI = '7.8us'
25211986Sandreas.sandberg@arm.com
25311986Sandreas.sandberg@arm.com    # Greater of 4 CK or 7.5 ns, 4 CK @ 666.66 MHz = 6 ns
254    tWTR = '7.5ns'
255
256    tRRD = '6.0ns'
257
258    tXAW = '30ns'
259    activation_limit = 4
260
261
262# A single LPDDR2-S4 x32 interface (one command/address bus), with
263# default timings based on a LPDDR2-1066 4 Gbit part in a 1x32
264# configuration.
265class LPDDR2_S4_1066_x32(SimpleDRAM):
266    # 1x32 configuration, 1 device with a 32-bit interface
267    device_bus_width = 32
268
269    # LPDDR2_S4 is a BL4 and BL8 device
270    burst_length = 8
271
272    # Each device has a page (row buffer) size of 1KB
273    # (this depends on the memory density)
274    device_rowbuffer_size = '1kB'
275
276    # 1x32 configuration, so 1 device
277    devices_per_rank = 1
278
279    # Use a single rank
280    ranks_per_channel = 1
281
282    # LPDDR2-S4 has 8 banks in all configurations
283    banks_per_rank = 8
284
285    # Fixed at 15 ns
286    tRCD = '15ns'
287
288    # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time
289    tCL = '15ns'
290
291    # Pre-charge one bank 15 ns (all banks 18 ns)
292    tRP = '15ns'
293
294    tRAS = '42ns'
295
296    # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz.
297    # Note this is a BL8 DDR device.
298    # Requests larger than 32 bytes are broken down into multiple requests
299    # in the SimpleDRAM controller
300    tBURST = '7.5ns'
301
302    # LPDDR2-S4, 4 Gbit
303    tRFC = '130ns'
304    tREFI = '3.9us'
305
306    # Irrespective of speed grade, tWTR is 7.5 ns
307    tWTR = '7.5ns'
308
309    # Activate to activate irrespective of density and speed grade
310    tRRD = '10.0ns'
311
312    # Irrespective of density, tFAW is 50 ns
313    tXAW = '50ns'
314    activation_limit = 4
315
316# A single WideIO x128 interface (one command and address bus), with
317# default timings based on an estimated WIO-200 8 Gbit part.
318class WideIO_200_x128(SimpleDRAM):
319    # 1x128 configuration, 1 device with a 128-bit interface
320    device_bus_width = 128
321
322    # This is a BL4 device
323    burst_length = 4
324
325    # Each device has a page (row buffer) size of 4KB
326    # (this depends on the memory density)
327    device_rowbuffer_size = '4kB'
328
329    # 1x128 configuration, so 1 device
330    devices_per_rank = 1
331
332    # Use one rank for a one-high die stack
333    ranks_per_channel = 1
334
335    # WideIO has 4 banks in all configurations
336    banks_per_rank = 4
337
338    # WIO-200
339    tRCD = '18ns'
340    tCL = '18ns'
341    tRP = '18ns'
342    tRAS = '42ns'
343
344    # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz.
345    # Note this is a BL4 SDR device.
346    tBURST = '20ns'
347
348    # WIO 8 Gb
349    tRFC = '210ns'
350
351    # WIO 8 Gb, <=85C, half for >85C
352    tREFI = '3.9us'
353
354    # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns
355    tWTR = '15ns'
356
357    # Activate to activate irrespective of density and speed grade
358    tRRD = '10.0ns'
359
360    # Two instead of four activation window
361    tXAW = '50ns'
362    activation_limit = 2
363
364# A single LPDDR3 x32 interface (one command/address bus), with
365# default timings based on a LPDDR3-1600 4 Gbit part in a 1x32
366# configuration
367class LPDDR3_1600_x32(SimpleDRAM):
368    # 1x32 configuration, 1 device with a 32-bit interface
369    device_bus_width = 32
370
371    # LPDDR3 is a BL8 device
372    burst_length = 8
373
374    # Each device has a page (row buffer) size of 4KB
375    device_rowbuffer_size = '4kB'
376
377    # 1x32 configuration, so 1 device
378    devices_per_rank = 1
379
380    # Use a single rank
381    ranks_per_channel = 1
382
383    # LPDDR3 has 8 banks in all configurations
384    banks_per_rank = 8
385
386    # Fixed at 15 ns
387    tRCD = '15ns'
388
389    # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time
390    tCL = '15ns'
391
392    tRAS = '42ns'
393
394    # Pre-charge one bank 15 ns (all banks 18 ns)
395    tRP = '15ns'
396
397    # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz.
398    # Note this is a BL8 DDR device.
399    # Requests larger than 32 bytes are broken down into multiple requests
400    # in the SimpleDRAM controller
401    tBURST = '5ns'
402
403    # LPDDR3, 4 Gb
404    tRFC = '130ns'
405    tREFI = '3.9us'
406
407    # Irrespective of speed grade, tWTR is 7.5 ns
408    tWTR = '7.5ns'
409
410    # Activate to activate irrespective of density and speed grade
411    tRRD = '10.0ns'
412
413    # Irrespective of size, tFAW is 50 ns
414    tXAW = '50ns'
415    activation_limit = 4
416