DRAMCtrl.py revision 10140
1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2013 Amin Farmahini-Farahani 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Andreas Hansson 40# Ani Udipi 41 42from m5.params import * 43from AbstractMemory import * 44 45# Enum for memory scheduling algorithms, currently First-Come 46# First-Served and a First-Row Hit then First-Come First-Served 47class MemSched(Enum): vals = ['fcfs', 'frfcfs'] 48 49# Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting 50# channel, rank, bank, row and column, respectively, and going from 51# MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are 52# suitable for an open-page policy, optimising for sequential accesses 53# hitting in the open row. For a closed-page policy, RoCoRaBaCh 54# maximises parallelism. 55class AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh'] 56 57# Enum for the page policy, either open, open_adaptive or close. 58class PageManage(Enum): vals = ['open', 'open_adaptive', 'close'] 59 60# SimpleDRAM is a single-channel single-ported DRAM controller model 61# that aims to model the most important system-level performance 62# effects of a DRAM without getting into too much detail of the DRAM 63# itself. 64class SimpleDRAM(AbstractMemory): 65 type = 'SimpleDRAM' 66 cxx_header = "mem/simple_dram.hh" 67 68 # single-ported on the system interface side, instantiate with a 69 # bus in front of the controller for multiple ports 70 port = SlavePort("Slave port") 71 72 # the basic configuration of the controller architecture 73 write_buffer_size = Param.Unsigned(32, "Number of write queue entries") 74 read_buffer_size = Param.Unsigned(32, "Number of read queue entries") 75 76 # threshold in percent for when to forcefully trigger writes and 77 # start emptying the write buffer 78 write_high_thresh_perc = Param.Percent(85, "Threshold to force writes") 79 80 # threshold in percentage for when to start writes if the read 81 # queue is empty 82 write_low_thresh_perc = Param.Percent(50, "Threshold to start writes") 83 84 # minimum write bursts to schedule before switching back to reads 85 min_writes_per_switch = Param.Unsigned(16, "Minimum write bursts before " 86 "switching to reads") 87 88 # scheduler, address map and page policy 89 mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy") 90 addr_mapping = Param.AddrMap('RoRaBaChCo', "Address mapping policy") 91 page_policy = Param.PageManage('open', "Page closure management policy") 92 93 # pipeline latency of the controller and PHY, split into a 94 # frontend part and a backend part, with reads and writes serviced 95 # by the queues only seeing the frontend contribution, and reads 96 # serviced by the memory seeing the sum of the two 97 static_frontend_latency = Param.Latency("10ns", "Static frontend latency") 98 static_backend_latency = Param.Latency("10ns", "Static backend latency") 99 100 # the physical organisation of the DRAM 101 device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\ 102 "device/chip") 103 burst_length = Param.Unsigned("Burst lenght (BL) in beats") 104 device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\ 105 "device/chip") 106 devices_per_rank = Param.Unsigned("Number of devices/chips per rank") 107 ranks_per_channel = Param.Unsigned("Number of ranks per channel") 108 banks_per_rank = Param.Unsigned("Number of banks per rank") 109 # only used for the address mapping as the controller by 110 # construction is a single channel and multiple controllers have 111 # to be instantiated for a multi-channel configuration 112 channels = Param.Unsigned(1, "Number of channels") 113 114 # timing behaviour and constraints - all in nanoseconds 115 116 # the amount of time in nanoseconds from issuing an activate command 117 # to the data being available in the row buffer for a read/write 118 tRCD = Param.Latency("RAS to CAS delay") 119 120 # the time from issuing a read/write command to seeing the actual data 121 tCL = Param.Latency("CAS latency") 122 123 # minimum time between a precharge and subsequent activate 124 tRP = Param.Latency("Row precharge time") 125 126 # minimum time between an activate and a precharge to the same row 127 tRAS = Param.Latency("ACT to PRE delay") 128 129 # time to complete a burst transfer, typically the burst length 130 # divided by two due to the DDR bus, but by making it a parameter 131 # it is easier to also evaluate SDR memories like WideIO. 132 # This parameter has to account for burst length. 133 # Read/Write requests with data size larger than one full burst are broken 134 # down into multiple requests in the SimpleDRAM controller 135 tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)") 136 137 # time taken to complete one refresh cycle (N rows in all banks) 138 tRFC = Param.Latency("Refresh cycle time") 139 140 # refresh command interval, how often a "ref" command needs 141 # to be sent. It is 7.8 us for a 64ms refresh requirement 142 tREFI = Param.Latency("Refresh command interval") 143 144 # write-to-read turn around penalty, assumed same as read-to-write 145 tWTR = Param.Latency("Write to read switching time") 146 147 # minimum row activate to row activate delay time 148 tRRD = Param.Latency("ACT to ACT delay") 149 150 # time window in which a maximum number of activates are allowed 151 # to take place, set to 0 to disable 152 tXAW = Param.Latency("X activation window") 153 activation_limit = Param.Unsigned("Max number of activates in window") 154 155 # Currently rolled into other params 156 ###################################################################### 157 158 # tRC - assumed to be tRAS + tRP 159 160# A single DDR3 x64 interface (one command and address bus), with 161# default timings based on DDR3-1600 4 Gbit parts in an 8x8 162# configuration, which would amount to 4 Gbyte of memory. 163class DDR3_1600_x64(SimpleDRAM): 164 # 8x8 configuration, 8 devices each with an 8-bit interface 165 device_bus_width = 8 166 167 # DDR3 is a BL8 device 168 burst_length = 8 169 170 # Each device has a page (row buffer) size of 1KB 171 # (this depends on the memory density) 172 device_rowbuffer_size = '1kB' 173 174 # 8x8 configuration, so 8 devices 175 devices_per_rank = 8 176 177 # Use two ranks 178 ranks_per_channel = 2 179 180 # DDR3 has 8 banks in all configurations 181 banks_per_rank = 8 182 183 # DDR3-1600 11-11-11-28 184 tRCD = '13.75ns' 185 tCL = '13.75ns' 186 tRP = '13.75ns' 187 tRAS = '35ns' 188 189 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz. 190 # Note this is a BL8 DDR device. 191 tBURST = '5ns' 192 193 # DDR3, 4 Gbit has a tRFC of 240 CK and tCK = 1.25 ns 194 tRFC = '300ns' 195 196 # DDR3, <=85C, half for >85C 197 tREFI = '7.8us' 198 199 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns 200 tWTR = '7.5ns' 201 202 # Assume 5 CK for activate to activate for different banks 203 tRRD = '6.25ns' 204 205 # With a 2kbyte page size, DDR3-1600 lands around 40 ns 206 tXAW = '40ns' 207 activation_limit = 4 208 209 210# A single DDR3 x64 interface (one command and address bus), with 211# default timings based on DDR3-1333 4 Gbit parts in an 8x8 212# configuration, which would amount to 4 GByte of memory. This 213# configuration is primarily for comparing with DRAMSim2, and all the 214# parameters except ranks_per_channel are based on the DRAMSim2 config 215# file DDR3_micron_32M_8B_x8_sg15.ini. Note that ranks_per_channel has 216# to be manually set, depending on size of the memory to be 217# simulated. By default DRAMSim2 has 2048MB of memory with a single 218# rank. Therefore for 4 GByte memory, set ranks_per_channel = 2 219class DDR3_1333_x64_DRAMSim2(SimpleDRAM): 220 # 8x8 configuration, 8 devices each with an 8-bit interface 221 device_bus_width = 8 222 223 # DDR3 is a BL8 device 224 burst_length = 8 225 226 # Each device has a page (row buffer) size of 1KB 227 # (this depends on the memory density) 228 device_rowbuffer_size = '1kB' 229 230 # 8x8 configuration, so 8 devices 231 devices_per_rank = 8 232 233 # Use two ranks 234 ranks_per_channel = 2 235 236 # DDR3 has 8 banks in all configurations 237 banks_per_rank = 8 238 239 tRCD = '15ns' 240 tCL = '15ns' 241 tRP = '15ns' 242 tRAS = '36ns' 243 244 # 8 beats across an x64 interface translates to 4 clocks @ 666.66 MHz. 245 # Note this is a BL8 DDR device. 246 tBURST = '6ns' 247 248 tRFC = '160ns' 249 250 # DDR3, <=85C, half for >85C 251 tREFI = '7.8us' 252 253 # Greater of 4 CK or 7.5 ns, 4 CK @ 666.66 MHz = 6 ns 254 tWTR = '7.5ns' 255 256 tRRD = '6.0ns' 257 258 tXAW = '30ns' 259 activation_limit = 4 260 261 262# A single LPDDR2-S4 x32 interface (one command/address bus), with 263# default timings based on a LPDDR2-1066 4 Gbit part in a 1x32 264# configuration. 265class LPDDR2_S4_1066_x32(SimpleDRAM): 266 # 1x32 configuration, 1 device with a 32-bit interface 267 device_bus_width = 32 268 269 # LPDDR2_S4 is a BL4 and BL8 device 270 burst_length = 8 271 272 # Each device has a page (row buffer) size of 1KB 273 # (this depends on the memory density) 274 device_rowbuffer_size = '1kB' 275 276 # 1x32 configuration, so 1 device 277 devices_per_rank = 1 278 279 # Use a single rank 280 ranks_per_channel = 1 281 282 # LPDDR2-S4 has 8 banks in all configurations 283 banks_per_rank = 8 284 285 # Fixed at 15 ns 286 tRCD = '15ns' 287 288 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time 289 tCL = '15ns' 290 291 # Pre-charge one bank 15 ns (all banks 18 ns) 292 tRP = '15ns' 293 294 tRAS = '42ns' 295 296 # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz. 297 # Note this is a BL8 DDR device. 298 # Requests larger than 32 bytes are broken down into multiple requests 299 # in the SimpleDRAM controller 300 tBURST = '7.5ns' 301 302 # LPDDR2-S4, 4 Gbit 303 tRFC = '130ns' 304 tREFI = '3.9us' 305 306 # Irrespective of speed grade, tWTR is 7.5 ns 307 tWTR = '7.5ns' 308 309 # Activate to activate irrespective of density and speed grade 310 tRRD = '10.0ns' 311 312 # Irrespective of density, tFAW is 50 ns 313 tXAW = '50ns' 314 activation_limit = 4 315 316# A single WideIO x128 interface (one command and address bus), with 317# default timings based on an estimated WIO-200 8 Gbit part. 318class WideIO_200_x128(SimpleDRAM): 319 # 1x128 configuration, 1 device with a 128-bit interface 320 device_bus_width = 128 321 322 # This is a BL4 device 323 burst_length = 4 324 325 # Each device has a page (row buffer) size of 4KB 326 # (this depends on the memory density) 327 device_rowbuffer_size = '4kB' 328 329 # 1x128 configuration, so 1 device 330 devices_per_rank = 1 331 332 # Use one rank for a one-high die stack 333 ranks_per_channel = 1 334 335 # WideIO has 4 banks in all configurations 336 banks_per_rank = 4 337 338 # WIO-200 339 tRCD = '18ns' 340 tCL = '18ns' 341 tRP = '18ns' 342 tRAS = '42ns' 343 344 # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz. 345 # Note this is a BL4 SDR device. 346 tBURST = '20ns' 347 348 # WIO 8 Gb 349 tRFC = '210ns' 350 351 # WIO 8 Gb, <=85C, half for >85C 352 tREFI = '3.9us' 353 354 # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns 355 tWTR = '15ns' 356 357 # Activate to activate irrespective of density and speed grade 358 tRRD = '10.0ns' 359 360 # Two instead of four activation window 361 tXAW = '50ns' 362 activation_limit = 2 363 364# A single LPDDR3 x32 interface (one command/address bus), with 365# default timings based on a LPDDR3-1600 4 Gbit part in a 1x32 366# configuration 367class LPDDR3_1600_x32(SimpleDRAM): 368 # 1x32 configuration, 1 device with a 32-bit interface 369 device_bus_width = 32 370 371 # LPDDR3 is a BL8 device 372 burst_length = 8 373 374 # Each device has a page (row buffer) size of 4KB 375 device_rowbuffer_size = '4kB' 376 377 # 1x32 configuration, so 1 device 378 devices_per_rank = 1 379 380 # Use a single rank 381 ranks_per_channel = 1 382 383 # LPDDR3 has 8 banks in all configurations 384 banks_per_rank = 8 385 386 # Fixed at 15 ns 387 tRCD = '15ns' 388 389 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time 390 tCL = '15ns' 391 392 tRAS = '42ns' 393 394 # Pre-charge one bank 15 ns (all banks 18 ns) 395 tRP = '15ns' 396 397 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz. 398 # Note this is a BL8 DDR device. 399 # Requests larger than 32 bytes are broken down into multiple requests 400 # in the SimpleDRAM controller 401 tBURST = '5ns' 402 403 # LPDDR3, 4 Gb 404 tRFC = '130ns' 405 tREFI = '3.9us' 406 407 # Irrespective of speed grade, tWTR is 7.5 ns 408 tWTR = '7.5ns' 409 410 # Activate to activate irrespective of density and speed grade 411 tRRD = '10.0ns' 412 413 # Irrespective of size, tFAW is 50 ns 414 tXAW = '50ns' 415 activation_limit = 4 416