i82094aa.cc revision 8746
15643Sgblack@eecs.umich.edu/* 25643Sgblack@eecs.umich.edu * Copyright (c) 2008 The Regents of The University of Michigan 35643Sgblack@eecs.umich.edu * All rights reserved. 45643Sgblack@eecs.umich.edu * 55643Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 65643Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 75643Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 85643Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 95643Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 105643Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 115643Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 125643Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 135643Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 145643Sgblack@eecs.umich.edu * this software without specific prior written permission. 155643Sgblack@eecs.umich.edu * 165643Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175643Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185643Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195643Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205643Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215643Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225643Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235643Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245643Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255643Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265643Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275643Sgblack@eecs.umich.edu * 285643Sgblack@eecs.umich.edu * Authors: Gabe Black 295643Sgblack@eecs.umich.edu */ 305643Sgblack@eecs.umich.edu 318739Sgblack@eecs.umich.edu#include "config/full_system.hh" 328739Sgblack@eecs.umich.edu 336138Sgblack@eecs.umich.edu#include "arch/x86/interrupts.hh" 345651Sgblack@eecs.umich.edu#include "arch/x86/intmessage.hh" 358746Sgblack@eecs.umich.edu#include "cpu/base.hh" 368232Snate@binkert.org#include "debug/I82094AA.hh" 375643Sgblack@eecs.umich.edu#include "dev/x86/i82094aa.hh" 385657Sgblack@eecs.umich.edu#include "dev/x86/i8259.hh" 395643Sgblack@eecs.umich.edu#include "mem/packet.hh" 405643Sgblack@eecs.umich.edu#include "mem/packet_access.hh" 415643Sgblack@eecs.umich.edu#include "sim/system.hh" 425643Sgblack@eecs.umich.edu 436803Sgblack@eecs.umich.eduX86ISA::I82094AA::I82094AA(Params *p) : PioDevice(p), 446803Sgblack@eecs.umich.edu IntDev(this, p->int_latency), 455827Sgblack@eecs.umich.edu latency(p->pio_latency), pioAddr(p->pio_addr), 466139Sgblack@eecs.umich.edu extIntPic(p->external_int_pic), lowestPriorityOffset(0) 475643Sgblack@eecs.umich.edu{ 487913SBrad.Beckmann@amd.com // This assumes there's only one I/O APIC in the system and since the apic 497913SBrad.Beckmann@amd.com // id is stored in a 8-bit field with 0xff meaning broadcast, the id must 507913SBrad.Beckmann@amd.com // be less than 0xff 517913SBrad.Beckmann@amd.com 527913SBrad.Beckmann@amd.com assert(p->apic_id < 0xff); 536136Sgblack@eecs.umich.edu initialApicId = id = p->apic_id; 545643Sgblack@eecs.umich.edu arbId = id; 555643Sgblack@eecs.umich.edu regSel = 0; 565653Sgblack@eecs.umich.edu RedirTableEntry entry = 0; 575653Sgblack@eecs.umich.edu entry.mask = 1; 585653Sgblack@eecs.umich.edu for (int i = 0; i < TableSize; i++) { 595653Sgblack@eecs.umich.edu redirTable[i] = entry; 605827Sgblack@eecs.umich.edu pinStates[i] = false; 615653Sgblack@eecs.umich.edu } 625643Sgblack@eecs.umich.edu} 635643Sgblack@eecs.umich.edu 647913SBrad.Beckmann@amd.comvoid 657913SBrad.Beckmann@amd.comX86ISA::I82094AA::init() 667913SBrad.Beckmann@amd.com{ 677913SBrad.Beckmann@amd.com // The io apic must register its address ranges on both its pio port 687913SBrad.Beckmann@amd.com // via the piodevice init() function and its int port that it inherited 697913SBrad.Beckmann@amd.com // from IntDev. Note IntDev is not a SimObject itself. 707913SBrad.Beckmann@amd.com 717913SBrad.Beckmann@amd.com PioDevice::init(); 727913SBrad.Beckmann@amd.com IntDev::init(); 737913SBrad.Beckmann@amd.com} 747913SBrad.Beckmann@amd.com 755643Sgblack@eecs.umich.eduTick 765643Sgblack@eecs.umich.eduX86ISA::I82094AA::read(PacketPtr pkt) 775643Sgblack@eecs.umich.edu{ 785643Sgblack@eecs.umich.edu assert(pkt->getSize() == 4); 795643Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - pioAddr; 805643Sgblack@eecs.umich.edu switch(offset) { 815643Sgblack@eecs.umich.edu case 0: 825643Sgblack@eecs.umich.edu pkt->set<uint32_t>(regSel); 835643Sgblack@eecs.umich.edu break; 845643Sgblack@eecs.umich.edu case 16: 855643Sgblack@eecs.umich.edu pkt->set<uint32_t>(readReg(regSel)); 865643Sgblack@eecs.umich.edu break; 875643Sgblack@eecs.umich.edu default: 885643Sgblack@eecs.umich.edu panic("Illegal read from I/O APIC.\n"); 895643Sgblack@eecs.umich.edu } 905898Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 915643Sgblack@eecs.umich.edu return latency; 925643Sgblack@eecs.umich.edu} 935643Sgblack@eecs.umich.edu 945643Sgblack@eecs.umich.eduTick 955643Sgblack@eecs.umich.eduX86ISA::I82094AA::write(PacketPtr pkt) 965643Sgblack@eecs.umich.edu{ 975643Sgblack@eecs.umich.edu assert(pkt->getSize() == 4); 985643Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - pioAddr; 995643Sgblack@eecs.umich.edu switch(offset) { 1005643Sgblack@eecs.umich.edu case 0: 1015643Sgblack@eecs.umich.edu regSel = pkt->get<uint32_t>(); 1025643Sgblack@eecs.umich.edu break; 1035643Sgblack@eecs.umich.edu case 16: 1045643Sgblack@eecs.umich.edu writeReg(regSel, pkt->get<uint32_t>()); 1055643Sgblack@eecs.umich.edu break; 1065643Sgblack@eecs.umich.edu default: 1075643Sgblack@eecs.umich.edu panic("Illegal write to I/O APIC.\n"); 1085643Sgblack@eecs.umich.edu } 1095898Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 1105643Sgblack@eecs.umich.edu return latency; 1115643Sgblack@eecs.umich.edu} 1125643Sgblack@eecs.umich.edu 1135643Sgblack@eecs.umich.eduvoid 1145643Sgblack@eecs.umich.eduX86ISA::I82094AA::writeReg(uint8_t offset, uint32_t value) 1155643Sgblack@eecs.umich.edu{ 1165643Sgblack@eecs.umich.edu if (offset == 0x0) { 1177913SBrad.Beckmann@amd.com id = bits(value, 31, 24); 1185643Sgblack@eecs.umich.edu } else if (offset == 0x1) { 1195643Sgblack@eecs.umich.edu // The IOAPICVER register is read only. 1205643Sgblack@eecs.umich.edu } else if (offset == 0x2) { 1217913SBrad.Beckmann@amd.com arbId = bits(value, 31, 24); 1225643Sgblack@eecs.umich.edu } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) { 1235643Sgblack@eecs.umich.edu int index = (offset - 0x10) / 2; 1245643Sgblack@eecs.umich.edu if (offset % 2) { 1255643Sgblack@eecs.umich.edu redirTable[index].topDW = value; 1265643Sgblack@eecs.umich.edu redirTable[index].topReserved = 0; 1275643Sgblack@eecs.umich.edu } else { 1285643Sgblack@eecs.umich.edu redirTable[index].bottomDW = value; 1295643Sgblack@eecs.umich.edu redirTable[index].bottomReserved = 0; 1305643Sgblack@eecs.umich.edu } 1315643Sgblack@eecs.umich.edu } else { 1325643Sgblack@eecs.umich.edu warn("Access to undefined I/O APIC register %#x.\n", offset); 1335643Sgblack@eecs.umich.edu } 1345643Sgblack@eecs.umich.edu DPRINTF(I82094AA, 1355643Sgblack@eecs.umich.edu "Wrote %#x to I/O APIC register %#x .\n", value, offset); 1365643Sgblack@eecs.umich.edu} 1375643Sgblack@eecs.umich.edu 1385643Sgblack@eecs.umich.eduuint32_t 1395643Sgblack@eecs.umich.eduX86ISA::I82094AA::readReg(uint8_t offset) 1405643Sgblack@eecs.umich.edu{ 1415643Sgblack@eecs.umich.edu uint32_t result = 0; 1425643Sgblack@eecs.umich.edu if (offset == 0x0) { 1435643Sgblack@eecs.umich.edu result = id << 24; 1445643Sgblack@eecs.umich.edu } else if (offset == 0x1) { 1455643Sgblack@eecs.umich.edu result = ((TableSize - 1) << 16) | APICVersion; 1465643Sgblack@eecs.umich.edu } else if (offset == 0x2) { 1475643Sgblack@eecs.umich.edu result = arbId << 24; 1485643Sgblack@eecs.umich.edu } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) { 1495643Sgblack@eecs.umich.edu int index = (offset - 0x10) / 2; 1505643Sgblack@eecs.umich.edu if (offset % 2) { 1515643Sgblack@eecs.umich.edu result = redirTable[index].topDW; 1525643Sgblack@eecs.umich.edu } else { 1535643Sgblack@eecs.umich.edu result = redirTable[index].bottomDW; 1545643Sgblack@eecs.umich.edu } 1555643Sgblack@eecs.umich.edu } else { 1565643Sgblack@eecs.umich.edu warn("Access to undefined I/O APIC register %#x.\n", offset); 1575643Sgblack@eecs.umich.edu } 1585643Sgblack@eecs.umich.edu DPRINTF(I82094AA, 1595643Sgblack@eecs.umich.edu "Read %#x from I/O APIC register %#x.\n", result, offset); 1605643Sgblack@eecs.umich.edu return result; 1615643Sgblack@eecs.umich.edu} 1625643Sgblack@eecs.umich.edu 1635643Sgblack@eecs.umich.eduvoid 1645643Sgblack@eecs.umich.eduX86ISA::I82094AA::signalInterrupt(int line) 1655643Sgblack@eecs.umich.edu{ 1665643Sgblack@eecs.umich.edu DPRINTF(I82094AA, "Received interrupt %d.\n", line); 1675643Sgblack@eecs.umich.edu assert(line < TableSize); 1685643Sgblack@eecs.umich.edu RedirTableEntry entry = redirTable[line]; 1695643Sgblack@eecs.umich.edu if (entry.mask) { 1705643Sgblack@eecs.umich.edu DPRINTF(I82094AA, "Entry was masked.\n"); 1715643Sgblack@eecs.umich.edu return; 1725643Sgblack@eecs.umich.edu } else { 1736712Snate@binkert.org TriggerIntMessage message = 0; 1745651Sgblack@eecs.umich.edu message.destination = entry.dest; 1755657Sgblack@eecs.umich.edu if (entry.deliveryMode == DeliveryMode::ExtInt) { 1765657Sgblack@eecs.umich.edu assert(extIntPic); 1775657Sgblack@eecs.umich.edu message.vector = extIntPic->getVector(); 1785657Sgblack@eecs.umich.edu } else { 1795657Sgblack@eecs.umich.edu message.vector = entry.vector; 1805657Sgblack@eecs.umich.edu } 1815651Sgblack@eecs.umich.edu message.deliveryMode = entry.deliveryMode; 1825651Sgblack@eecs.umich.edu message.destMode = entry.destMode; 1835654Sgblack@eecs.umich.edu message.level = entry.polarity; 1845654Sgblack@eecs.umich.edu message.trigger = entry.trigger; 1856138Sgblack@eecs.umich.edu ApicList apics; 1866138Sgblack@eecs.umich.edu int numContexts = sys->numContexts(); 1876138Sgblack@eecs.umich.edu if (message.destMode == 0) { 1886138Sgblack@eecs.umich.edu if (message.deliveryMode == DeliveryMode::LowestPriority) { 1896138Sgblack@eecs.umich.edu panic("Lowest priority delivery mode from the " 1906138Sgblack@eecs.umich.edu "IO APIC aren't supported in physical " 1916138Sgblack@eecs.umich.edu "destination mode.\n"); 1926138Sgblack@eecs.umich.edu } 1936138Sgblack@eecs.umich.edu if (message.destination == 0xFF) { 1946138Sgblack@eecs.umich.edu for (int i = 0; i < numContexts; i++) { 1956138Sgblack@eecs.umich.edu apics.push_back(i); 1966138Sgblack@eecs.umich.edu } 1976138Sgblack@eecs.umich.edu } else { 1986138Sgblack@eecs.umich.edu apics.push_back(message.destination); 1996138Sgblack@eecs.umich.edu } 2006138Sgblack@eecs.umich.edu } else { 2016138Sgblack@eecs.umich.edu for (int i = 0; i < numContexts; i++) { 2028746Sgblack@eecs.umich.edu Interrupts *localApic = sys->getThreadContext(i)-> 2038746Sgblack@eecs.umich.edu getCpuPtr()->getInterruptController(); 2046138Sgblack@eecs.umich.edu if ((localApic->readReg(APIC_LOGICAL_DESTINATION) >> 24) & 2056138Sgblack@eecs.umich.edu message.destination) { 2068746Sgblack@eecs.umich.edu apics.push_back(localApic->getInitialApicId()); 2076138Sgblack@eecs.umich.edu } 2086138Sgblack@eecs.umich.edu } 2096139Sgblack@eecs.umich.edu if (message.deliveryMode == DeliveryMode::LowestPriority && 2106139Sgblack@eecs.umich.edu apics.size()) { 2116139Sgblack@eecs.umich.edu // The manual seems to suggest that the chipset just does 2126139Sgblack@eecs.umich.edu // something reasonable for these instead of actually using 2136139Sgblack@eecs.umich.edu // state from the local APIC. We'll just rotate an offset 2146139Sgblack@eecs.umich.edu // through the set of APICs selected above. 2156139Sgblack@eecs.umich.edu uint64_t modOffset = lowestPriorityOffset % apics.size(); 2166139Sgblack@eecs.umich.edu lowestPriorityOffset++; 2176139Sgblack@eecs.umich.edu ApicList::iterator apicIt = apics.begin(); 2186139Sgblack@eecs.umich.edu while (modOffset--) { 2196139Sgblack@eecs.umich.edu apicIt++; 2206139Sgblack@eecs.umich.edu assert(apicIt != apics.end()); 2216139Sgblack@eecs.umich.edu } 2226139Sgblack@eecs.umich.edu int selected = *apicIt; 2236139Sgblack@eecs.umich.edu apics.clear(); 2246139Sgblack@eecs.umich.edu apics.push_back(selected); 2256138Sgblack@eecs.umich.edu } 2266138Sgblack@eecs.umich.edu } 2276138Sgblack@eecs.umich.edu intPort->sendMessage(apics, message, 2286138Sgblack@eecs.umich.edu sys->getMemoryMode() == Enums::timing); 2295643Sgblack@eecs.umich.edu } 2305643Sgblack@eecs.umich.edu} 2315643Sgblack@eecs.umich.edu 2325827Sgblack@eecs.umich.eduvoid 2335827Sgblack@eecs.umich.eduX86ISA::I82094AA::raiseInterruptPin(int number) 2345827Sgblack@eecs.umich.edu{ 2355827Sgblack@eecs.umich.edu assert(number < TableSize); 2365827Sgblack@eecs.umich.edu if (!pinStates[number]) 2375827Sgblack@eecs.umich.edu signalInterrupt(number); 2385827Sgblack@eecs.umich.edu pinStates[number] = true; 2395827Sgblack@eecs.umich.edu} 2405827Sgblack@eecs.umich.edu 2415827Sgblack@eecs.umich.eduvoid 2425827Sgblack@eecs.umich.eduX86ISA::I82094AA::lowerInterruptPin(int number) 2435827Sgblack@eecs.umich.edu{ 2445827Sgblack@eecs.umich.edu assert(number < TableSize); 2455827Sgblack@eecs.umich.edu pinStates[number] = false; 2465827Sgblack@eecs.umich.edu} 2475827Sgblack@eecs.umich.edu 2486137Sgblack@eecs.umich.eduvoid 2497903Shestness@cs.utexas.eduX86ISA::I82094AA::serialize(std::ostream &os) 2507903Shestness@cs.utexas.edu{ 2517903Shestness@cs.utexas.edu uint64_t* redirTableArray = (uint64_t*)redirTable; 2527903Shestness@cs.utexas.edu SERIALIZE_SCALAR(regSel); 2537903Shestness@cs.utexas.edu SERIALIZE_SCALAR(initialApicId); 2547903Shestness@cs.utexas.edu SERIALIZE_SCALAR(id); 2557903Shestness@cs.utexas.edu SERIALIZE_SCALAR(arbId); 2567903Shestness@cs.utexas.edu SERIALIZE_SCALAR(lowestPriorityOffset); 2577903Shestness@cs.utexas.edu SERIALIZE_ARRAY(redirTableArray, TableSize); 2587903Shestness@cs.utexas.edu SERIALIZE_ARRAY(pinStates, TableSize); 2597903Shestness@cs.utexas.edu} 2607903Shestness@cs.utexas.edu 2617903Shestness@cs.utexas.eduvoid 2627903Shestness@cs.utexas.eduX86ISA::I82094AA::unserialize(Checkpoint *cp, const std::string §ion) 2637903Shestness@cs.utexas.edu{ 2647903Shestness@cs.utexas.edu uint64_t redirTableArray[TableSize]; 2657903Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(regSel); 2667903Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(initialApicId); 2677903Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(id); 2687903Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(arbId); 2697903Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(lowestPriorityOffset); 2707903Shestness@cs.utexas.edu UNSERIALIZE_ARRAY(redirTableArray, TableSize); 2717903Shestness@cs.utexas.edu UNSERIALIZE_ARRAY(pinStates, TableSize); 2727903Shestness@cs.utexas.edu for (int i = 0; i < TableSize; i++) { 2737903Shestness@cs.utexas.edu redirTable[i] = (RedirTableEntry)redirTableArray[i]; 2747903Shestness@cs.utexas.edu } 2757903Shestness@cs.utexas.edu} 2767903Shestness@cs.utexas.edu 2775643Sgblack@eecs.umich.eduX86ISA::I82094AA * 2785643Sgblack@eecs.umich.eduI82094AAParams::create() 2795643Sgblack@eecs.umich.edu{ 2805643Sgblack@eecs.umich.edu return new X86ISA::I82094AA(this); 2815643Sgblack@eecs.umich.edu} 282