i82094aa.cc revision 8746 
1/*
2 * Copyright (c) 2008 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#include "config/full_system.hh"
32
33#include "arch/x86/interrupts.hh"
34#include "arch/x86/intmessage.hh"
35#include "cpu/base.hh"
36#include "debug/I82094AA.hh"
37#include "dev/x86/i82094aa.hh"
38#include "dev/x86/i8259.hh"
39#include "mem/packet.hh"
40#include "mem/packet_access.hh"
41#include "sim/system.hh"
42
43X86ISA::I82094AA::I82094AA(Params *p) : PioDevice(p),
44    IntDev(this, p->int_latency),
45    latency(p->pio_latency), pioAddr(p->pio_addr),
46    extIntPic(p->external_int_pic), lowestPriorityOffset(0)
47{
48    // This assumes there's only one I/O APIC in the system and since the apic
49    // id is stored in a 8-bit field with 0xff meaning broadcast, the id must
50    // be less than 0xff
51
52    assert(p->apic_id < 0xff);
53    initialApicId = id = p->apic_id;
54    arbId = id;
55    regSel = 0;
56    RedirTableEntry entry = 0;
57    entry.mask = 1;
58    for (int i = 0; i < TableSize; i++) {
59        redirTable[i] = entry;
60        pinStates[i] = false;
61    }
62}
63
64void
65X86ISA::I82094AA::init()
66{
67    // The io apic must register its address ranges on both its pio port
68    // via the piodevice init() function and its int port that it inherited
69    // from IntDev.  Note IntDev is not a SimObject itself.
70
71    PioDevice::init();
72    IntDev::init();
73}
74
75Tick
76X86ISA::I82094AA::read(PacketPtr pkt)
77{
78    assert(pkt->getSize() == 4);
79    Addr offset = pkt->getAddr() - pioAddr;
80    switch(offset) {
81      case 0:
82        pkt->set<uint32_t>(regSel);
83        break;
84      case 16:
85        pkt->set<uint32_t>(readReg(regSel));
86        break;
87      default:
88        panic("Illegal read from I/O APIC.\n");
89    }
90    pkt->makeAtomicResponse();
91    return latency;
92}
93
94Tick
95X86ISA::I82094AA::write(PacketPtr pkt)
96{
97    assert(pkt->getSize() == 4);
98    Addr offset = pkt->getAddr() - pioAddr;
99    switch(offset) {
100      case 0:
101        regSel = pkt->get<uint32_t>();
102        break;
103      case 16:
104        writeReg(regSel, pkt->get<uint32_t>());
105        break;
106      default:
107        panic("Illegal write to I/O APIC.\n");
108    }
109    pkt->makeAtomicResponse();
110    return latency;
111}
112
113void
114X86ISA::I82094AA::writeReg(uint8_t offset, uint32_t value)
115{
116    if (offset == 0x0) {
117        id = bits(value, 31, 24);
118    } else if (offset == 0x1) {
119        // The IOAPICVER register is read only.
120    } else if (offset == 0x2) {
121        arbId = bits(value, 31, 24);
122    } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) {
123        int index = (offset - 0x10) / 2;
124        if (offset % 2) {
125            redirTable[index].topDW = value;
126            redirTable[index].topReserved = 0;
127        } else {
128            redirTable[index].bottomDW = value;
129            redirTable[index].bottomReserved = 0;
130        }
131    } else {
132        warn("Access to undefined I/O APIC register %#x.\n", offset);
133    }
134    DPRINTF(I82094AA,
135            "Wrote %#x to I/O APIC register %#x .\n", value, offset);
136}
137
138uint32_t
139X86ISA::I82094AA::readReg(uint8_t offset)
140{
141    uint32_t result = 0;
142    if (offset == 0x0) {
143        result = id << 24;
144    } else if (offset == 0x1) {
145        result = ((TableSize - 1) << 16) | APICVersion;
146    } else if (offset == 0x2) {
147        result = arbId << 24;
148    } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) {
149        int index = (offset - 0x10) / 2;
150        if (offset % 2) {
151            result = redirTable[index].topDW;
152        } else {
153            result = redirTable[index].bottomDW;
154        }
155    } else {
156        warn("Access to undefined I/O APIC register %#x.\n", offset);
157    }
158    DPRINTF(I82094AA,
159            "Read %#x from I/O APIC register %#x.\n", result, offset);
160    return result;
161}
162
163void
164X86ISA::I82094AA::signalInterrupt(int line)
165{
166    DPRINTF(I82094AA, "Received interrupt %d.\n", line);
167    assert(line < TableSize);
168    RedirTableEntry entry = redirTable[line];
169    if (entry.mask) {
170        DPRINTF(I82094AA, "Entry was masked.\n");
171        return;
172    } else {
173        TriggerIntMessage message = 0;
174        message.destination = entry.dest;
175        if (entry.deliveryMode == DeliveryMode::ExtInt) {
176            assert(extIntPic);
177            message.vector = extIntPic->getVector();
178        } else {
179            message.vector = entry.vector;
180        }
181        message.deliveryMode = entry.deliveryMode;
182        message.destMode = entry.destMode;
183        message.level = entry.polarity;
184        message.trigger = entry.trigger;
185        ApicList apics;
186        int numContexts = sys->numContexts();
187        if (message.destMode == 0) {
188            if (message.deliveryMode == DeliveryMode::LowestPriority) {
189                panic("Lowest priority delivery mode from the "
190                        "IO APIC aren't supported in physical "
191                        "destination mode.\n");
192            }
193            if (message.destination == 0xFF) {
194                for (int i = 0; i < numContexts; i++) {
195                    apics.push_back(i);
196                }
197            } else {
198                apics.push_back(message.destination);
199            }
200        } else {
201            for (int i = 0; i < numContexts; i++) {
202                Interrupts *localApic = sys->getThreadContext(i)->
203                    getCpuPtr()->getInterruptController();
204                if ((localApic->readReg(APIC_LOGICAL_DESTINATION) >> 24) &
205                        message.destination) {
206                    apics.push_back(localApic->getInitialApicId());
207                }
208            }
209            if (message.deliveryMode == DeliveryMode::LowestPriority &&
210                    apics.size()) {
211                // The manual seems to suggest that the chipset just does
212                // something reasonable for these instead of actually using
213                // state from the local APIC. We'll just rotate an offset
214                // through the set of APICs selected above.
215                uint64_t modOffset = lowestPriorityOffset % apics.size();
216                lowestPriorityOffset++;
217                ApicList::iterator apicIt = apics.begin();
218                while (modOffset--) {
219                    apicIt++;
220                    assert(apicIt != apics.end());
221                }
222                int selected = *apicIt;
223                apics.clear();
224                apics.push_back(selected);
225            }
226        }
227        intPort->sendMessage(apics, message,
228                sys->getMemoryMode() == Enums::timing);
229    }
230}
231
232void
233X86ISA::I82094AA::raiseInterruptPin(int number)
234{
235    assert(number < TableSize);
236    if (!pinStates[number])
237        signalInterrupt(number);
238    pinStates[number] = true;
239}
240
241void
242X86ISA::I82094AA::lowerInterruptPin(int number)
243{
244    assert(number < TableSize);
245    pinStates[number] = false;
246}
247
248void
249X86ISA::I82094AA::serialize(std::ostream &os)
250{
251    uint64_t* redirTableArray = (uint64_t*)redirTable;
252    SERIALIZE_SCALAR(regSel);
253    SERIALIZE_SCALAR(initialApicId);
254    SERIALIZE_SCALAR(id);
255    SERIALIZE_SCALAR(arbId);
256    SERIALIZE_SCALAR(lowestPriorityOffset);
257    SERIALIZE_ARRAY(redirTableArray, TableSize);
258    SERIALIZE_ARRAY(pinStates, TableSize);
259}
260
261void
262X86ISA::I82094AA::unserialize(Checkpoint *cp, const std::string &section)
263{
264    uint64_t redirTableArray[TableSize];
265    UNSERIALIZE_SCALAR(regSel);
266    UNSERIALIZE_SCALAR(initialApicId);
267    UNSERIALIZE_SCALAR(id);
268    UNSERIALIZE_SCALAR(arbId);
269    UNSERIALIZE_SCALAR(lowestPriorityOffset);
270    UNSERIALIZE_ARRAY(redirTableArray, TableSize);
271    UNSERIALIZE_ARRAY(pinStates, TableSize);
272    for (int i = 0; i < TableSize; i++) {
273        redirTable[i] = (RedirTableEntry)redirTableArray[i];
274    }
275}
276
277X86ISA::I82094AA *
278I82094AAParams::create()
279{
280    return new X86ISA::I82094AA(this);
281}
282