hdlcd.hh revision 11090
19646SChris.Emmons@arm.com/* 210839Sandreas.sandberg@arm.com * Copyright (c) 2010-2013, 2015 ARM Limited 39646SChris.Emmons@arm.com * All rights reserved 49646SChris.Emmons@arm.com * 59646SChris.Emmons@arm.com * The license below extends only to copyright in the software and shall 69646SChris.Emmons@arm.com * not be construed as granting a license to any other intellectual 79646SChris.Emmons@arm.com * property including but not limited to intellectual property relating 89646SChris.Emmons@arm.com * to a hardware implementation of the functionality of the software 99646SChris.Emmons@arm.com * licensed hereunder. You may use the software subject to the license 109646SChris.Emmons@arm.com * terms below provided that you ensure that this notice is replicated 119646SChris.Emmons@arm.com * unmodified and in its entirety in all distributions of the software, 129646SChris.Emmons@arm.com * modified or unmodified, in source code or in binary form. 139646SChris.Emmons@arm.com * 149646SChris.Emmons@arm.com * Redistribution and use in source and binary forms, with or without 159646SChris.Emmons@arm.com * modification, are permitted provided that the following conditions are 169646SChris.Emmons@arm.com * met: redistributions of source code must retain the above copyright 179646SChris.Emmons@arm.com * notice, this list of conditions and the following disclaimer; 189646SChris.Emmons@arm.com * redistributions in binary form must reproduce the above copyright 199646SChris.Emmons@arm.com * notice, this list of conditions and the following disclaimer in the 209646SChris.Emmons@arm.com * documentation and/or other materials provided with the distribution; 219646SChris.Emmons@arm.com * neither the name of the copyright holders nor the names of its 229646SChris.Emmons@arm.com * contributors may be used to endorse or promote products derived from 239646SChris.Emmons@arm.com * this software without specific prior written permission. 249646SChris.Emmons@arm.com * 259646SChris.Emmons@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 269646SChris.Emmons@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 279646SChris.Emmons@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 289646SChris.Emmons@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 299646SChris.Emmons@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 309646SChris.Emmons@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 319646SChris.Emmons@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 329646SChris.Emmons@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 339646SChris.Emmons@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 349646SChris.Emmons@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 359646SChris.Emmons@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 369646SChris.Emmons@arm.com * 379646SChris.Emmons@arm.com * Authors: Chris Emmons 3811090Sandreas.sandberg@arm.com * Andreas Sandberg 399646SChris.Emmons@arm.com */ 409646SChris.Emmons@arm.com 419646SChris.Emmons@arm.com 429646SChris.Emmons@arm.com/** @file 439646SChris.Emmons@arm.com * Implementiation of the ARM HDLcd controller. 449646SChris.Emmons@arm.com * 459646SChris.Emmons@arm.com * This implementation aims to have sufficient detail such that underrun 469646SChris.Emmons@arm.com * conditions are reasonable / behave similar to reality. There are two 479646SChris.Emmons@arm.com * 'engines' going at once. First, the DMA engine running at LCD clock 489646SChris.Emmons@arm.com * frequency is responsible for filling the controller's internal buffer. 499646SChris.Emmons@arm.com * The second engine runs at the pixel clock frequency and reads the pixels 509646SChris.Emmons@arm.com * out of the internal buffer. The pixel rendering engine uses front / back 519646SChris.Emmons@arm.com * porch and sync delays between lines and frames. 529646SChris.Emmons@arm.com * 539646SChris.Emmons@arm.com * If the pixel rendering engine does not have a pixel to display, it will 549646SChris.Emmons@arm.com * cause an underrun event. The HDLcd controller, per spec, will stop 559646SChris.Emmons@arm.com * issuing DMA requests for the rest of the frame and resume normal behavior 569646SChris.Emmons@arm.com * on the subsequent frame. What pixels are rendered upon an underrun 579646SChris.Emmons@arm.com * condition is different than the real hardware; while the user will see 589646SChris.Emmons@arm.com * artifacts (previous frame mixed with current frame), it is not the same 599646SChris.Emmons@arm.com * behavior as real hardware which repeats the last pixel value for the rest 609646SChris.Emmons@arm.com * of the current frame. This compromise was made to save on memory and 619646SChris.Emmons@arm.com * complexity and assumes that it is not important to accurately model the 629646SChris.Emmons@arm.com * content of an underrun frame. 639646SChris.Emmons@arm.com * 649646SChris.Emmons@arm.com * KNOWN ISSUES 6511090Sandreas.sandberg@arm.com * <ul> 6611090Sandreas.sandberg@arm.com * <li>The HDLcd is implemented here as an AmbaDmaDevice, but it 6711090Sandreas.sandberg@arm.com * doesn't have an AMBA ID as far as I know. That is the only 6811090Sandreas.sandberg@arm.com * bit of the AmbaDmaDevice interface that is irrelevant to it, 6911090Sandreas.sandberg@arm.com * so a fake AMBA ID is used for now. I didn't think inserting 7011090Sandreas.sandberg@arm.com * an extra layer of hierachy between AmbaDmaDevice and 7111090Sandreas.sandberg@arm.com * DmaDevice would be helpful to anyone else, but that may be 7211090Sandreas.sandberg@arm.com * the right answer. 7311090Sandreas.sandberg@arm.com * </ul> 749646SChris.Emmons@arm.com */ 759646SChris.Emmons@arm.com 769646SChris.Emmons@arm.com#ifndef __DEV_ARM_HDLCD_HH__ 779646SChris.Emmons@arm.com#define __DEV_ARM_HDLCD_HH__ 789646SChris.Emmons@arm.com 799646SChris.Emmons@arm.com#include <fstream> 8010839Sandreas.sandberg@arm.com#include <memory> 819646SChris.Emmons@arm.com 8210839Sandreas.sandberg@arm.com#include "base/bitmap.hh" 8310839Sandreas.sandberg@arm.com#include "base/framebuffer.hh" 849646SChris.Emmons@arm.com#include "dev/arm/amba_device.hh" 8511090Sandreas.sandberg@arm.com#include "dev/pixelpump.hh" 869646SChris.Emmons@arm.com#include "sim/serialize.hh" 879646SChris.Emmons@arm.com 889646SChris.Emmons@arm.comclass VncInput; 8911090Sandreas.sandberg@arm.comstruct HDLcdParams; 9011090Sandreas.sandberg@arm.comclass HDLcdPixelPump; 919646SChris.Emmons@arm.com 929646SChris.Emmons@arm.comclass HDLcd: public AmbaDmaDevice 939646SChris.Emmons@arm.com{ 9411090Sandreas.sandberg@arm.com public: 9511090Sandreas.sandberg@arm.com HDLcd(const HDLcdParams *p); 9611090Sandreas.sandberg@arm.com ~HDLcd(); 979646SChris.Emmons@arm.com 9811090Sandreas.sandberg@arm.com void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; 9911090Sandreas.sandberg@arm.com void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; 10011090Sandreas.sandberg@arm.com 10111090Sandreas.sandberg@arm.com void drainResume() M5_ATTR_OVERRIDE; 10211090Sandreas.sandberg@arm.com 10311090Sandreas.sandberg@arm.com public: // IO device interface 10411090Sandreas.sandberg@arm.com Tick read(PacketPtr pkt) M5_ATTR_OVERRIDE; 10511090Sandreas.sandberg@arm.com Tick write(PacketPtr pkt) M5_ATTR_OVERRIDE; 10611090Sandreas.sandberg@arm.com 10711090Sandreas.sandberg@arm.com AddrRangeList getAddrRanges() const M5_ATTR_OVERRIDE { return addrRanges; } 10811090Sandreas.sandberg@arm.com 10911090Sandreas.sandberg@arm.com protected: // Parameters 11011090Sandreas.sandberg@arm.com VncInput *vnc; 11111090Sandreas.sandberg@arm.com const bool workaroundSwapRB; 11211090Sandreas.sandberg@arm.com const bool workaroundDmaLineCount; 11311090Sandreas.sandberg@arm.com const AddrRangeList addrRanges; 11411090Sandreas.sandberg@arm.com const bool enableCapture; 11511090Sandreas.sandberg@arm.com const Addr pixelBufferSize; 11611090Sandreas.sandberg@arm.com 11711090Sandreas.sandberg@arm.com protected: // Register handling 1189646SChris.Emmons@arm.com /** ARM HDLcd register offsets */ 1199646SChris.Emmons@arm.com enum RegisterOffset { 1209646SChris.Emmons@arm.com Version = 0x0000, 1219646SChris.Emmons@arm.com Int_RawStat = 0x0010, 1229646SChris.Emmons@arm.com Int_Clear = 0x0014, 1239646SChris.Emmons@arm.com Int_Mask = 0x0018, 1249646SChris.Emmons@arm.com Int_Status = 0x001C, 1259646SChris.Emmons@arm.com Fb_Base = 0x0100, 1269646SChris.Emmons@arm.com Fb_Line_Length = 0x0104, 1279646SChris.Emmons@arm.com Fb_Line_Count = 0x0108, 1289646SChris.Emmons@arm.com Fb_Line_Pitch = 0x010C, 1299646SChris.Emmons@arm.com Bus_Options = 0x0110, 1309646SChris.Emmons@arm.com V_Sync = 0x0200, 1319646SChris.Emmons@arm.com V_Back_Porch = 0x0204, 1329646SChris.Emmons@arm.com V_Data = 0x0208, 1339646SChris.Emmons@arm.com V_Front_Porch = 0x020C, 1349646SChris.Emmons@arm.com H_Sync = 0x0210, 1359646SChris.Emmons@arm.com H_Back_Porch = 0x0214, 1369646SChris.Emmons@arm.com H_Data = 0x0218, 1379646SChris.Emmons@arm.com H_Front_Porch = 0x021C, 1389646SChris.Emmons@arm.com Polarities = 0x0220, 1399646SChris.Emmons@arm.com Command = 0x0230, 1409646SChris.Emmons@arm.com Pixel_Format = 0x0240, 1419646SChris.Emmons@arm.com Red_Select = 0x0244, 1429646SChris.Emmons@arm.com Green_Select = 0x0248, 14311090Sandreas.sandberg@arm.com Blue_Select = 0x024C, 14411090Sandreas.sandberg@arm.com }; 1459646SChris.Emmons@arm.com 1469646SChris.Emmons@arm.com /** Reset value for Bus_Options register */ 14711090Sandreas.sandberg@arm.com static constexpr size_t BUS_OPTIONS_RESETV = 0x408; 1489646SChris.Emmons@arm.com 1499646SChris.Emmons@arm.com /** Reset value for Version register */ 15011090Sandreas.sandberg@arm.com static constexpr size_t VERSION_RESETV = 0x1CDC0000; 1519646SChris.Emmons@arm.com 15211090Sandreas.sandberg@arm.com /** AXI port width in bytes */ 15311090Sandreas.sandberg@arm.com static constexpr size_t AXI_PORT_WIDTH = 8; 1549646SChris.Emmons@arm.com 1559646SChris.Emmons@arm.com /** max number of beats delivered in one dma burst */ 15611090Sandreas.sandberg@arm.com static constexpr size_t MAX_BURST_LEN = 16; 1579646SChris.Emmons@arm.com 15811090Sandreas.sandberg@arm.com /** Maximum number of bytes per pixel */ 15911090Sandreas.sandberg@arm.com static constexpr size_t MAX_PIXEL_SIZE = 4; 16010839Sandreas.sandberg@arm.com 1619646SChris.Emmons@arm.com /** 1629646SChris.Emmons@arm.com * @name RegisterFieldLayouts 1639646SChris.Emmons@arm.com * Bit layout declarations for multi-field registers. 1649646SChris.Emmons@arm.com */ 1659646SChris.Emmons@arm.com /**@{*/ 1669646SChris.Emmons@arm.com BitUnion32(VersionReg) 1679646SChris.Emmons@arm.com Bitfield<7,0> version_minor; 1689646SChris.Emmons@arm.com Bitfield<15,8> version_major; 1699646SChris.Emmons@arm.com Bitfield<31,16> product_id; 1709646SChris.Emmons@arm.com EndBitUnion(VersionReg) 1719646SChris.Emmons@arm.com 17211090Sandreas.sandberg@arm.com static constexpr uint32_t INT_DMA_END = (1UL << 0); 17311090Sandreas.sandberg@arm.com static constexpr uint32_t INT_BUS_ERROR = (1UL << 1); 17411090Sandreas.sandberg@arm.com static constexpr uint32_t INT_VSYNC = (1UL << 2); 17511090Sandreas.sandberg@arm.com static constexpr uint32_t INT_UNDERRUN = (1UL << 3); 1769646SChris.Emmons@arm.com 1779646SChris.Emmons@arm.com BitUnion32(FbLineCountReg) 1789646SChris.Emmons@arm.com Bitfield<11,0> fb_line_count; 1799646SChris.Emmons@arm.com Bitfield<31,12> reserved_31_12; 1809646SChris.Emmons@arm.com EndBitUnion(FbLineCountReg) 1819646SChris.Emmons@arm.com 1829646SChris.Emmons@arm.com BitUnion32(BusOptsReg) 1839646SChris.Emmons@arm.com Bitfield<4,0> burst_len; 1849646SChris.Emmons@arm.com Bitfield<7,5> reserved_7_5; 1859646SChris.Emmons@arm.com Bitfield<11,8> max_outstanding; 1869646SChris.Emmons@arm.com Bitfield<31,12> reserved_31_12; 1879646SChris.Emmons@arm.com EndBitUnion(BusOptsReg) 1889646SChris.Emmons@arm.com 1899646SChris.Emmons@arm.com BitUnion32(TimingReg) 1909646SChris.Emmons@arm.com Bitfield<11,0> val; 1919646SChris.Emmons@arm.com Bitfield<31,12> reserved_31_12; 1929646SChris.Emmons@arm.com EndBitUnion(TimingReg) 1939646SChris.Emmons@arm.com 1949646SChris.Emmons@arm.com BitUnion32(PolaritiesReg) 1959646SChris.Emmons@arm.com Bitfield<0> vsync_polarity; 1969646SChris.Emmons@arm.com Bitfield<1> hsync_polarity; 1979646SChris.Emmons@arm.com Bitfield<2> dataen_polarity; 1989646SChris.Emmons@arm.com Bitfield<3> data_polarity; 1999646SChris.Emmons@arm.com Bitfield<4> pxlclk_polarity; 2009646SChris.Emmons@arm.com Bitfield<31,5> reserved_31_5; 2019646SChris.Emmons@arm.com EndBitUnion(PolaritiesReg) 2029646SChris.Emmons@arm.com 2039646SChris.Emmons@arm.com BitUnion32(CommandReg) 2049646SChris.Emmons@arm.com Bitfield<0> enable; 2059646SChris.Emmons@arm.com Bitfield<31,1> reserved_31_1; 2069646SChris.Emmons@arm.com EndBitUnion(CommandReg) 2079646SChris.Emmons@arm.com 2089646SChris.Emmons@arm.com BitUnion32(PixelFormatReg) 2099646SChris.Emmons@arm.com Bitfield<2,0> reserved_2_0; 2109646SChris.Emmons@arm.com Bitfield<4,3> bytes_per_pixel; 2119646SChris.Emmons@arm.com Bitfield<30,5> reserved_30_5; 2129646SChris.Emmons@arm.com Bitfield<31> big_endian; 2139646SChris.Emmons@arm.com EndBitUnion(PixelFormatReg) 2149646SChris.Emmons@arm.com 2159646SChris.Emmons@arm.com BitUnion32(ColorSelectReg) 2169646SChris.Emmons@arm.com Bitfield<4,0> offset; 2179646SChris.Emmons@arm.com Bitfield<7,5> reserved_7_5; 2189646SChris.Emmons@arm.com Bitfield<11,8> size; 2199646SChris.Emmons@arm.com Bitfield<15,12> reserved_15_12; 2209646SChris.Emmons@arm.com Bitfield<23,16> default_color; 2219646SChris.Emmons@arm.com Bitfield<31,24> reserved_31_24; 2229646SChris.Emmons@arm.com EndBitUnion(ColorSelectReg) 2239646SChris.Emmons@arm.com /**@}*/ 2249646SChris.Emmons@arm.com 2259646SChris.Emmons@arm.com /** 2269646SChris.Emmons@arm.com * @name HDLCDRegisters 2279646SChris.Emmons@arm.com * HDLCD register contents. 2289646SChris.Emmons@arm.com */ 2299646SChris.Emmons@arm.com /**@{*/ 23011090Sandreas.sandberg@arm.com const VersionReg version; /**< Version register */ 23111090Sandreas.sandberg@arm.com uint32_t int_rawstat; /**< Interrupt raw status register */ 23211090Sandreas.sandberg@arm.com uint32_t int_mask; /**< Interrupt mask register */ 2339646SChris.Emmons@arm.com uint32_t fb_base; /**< Frame buffer base address register */ 2349646SChris.Emmons@arm.com uint32_t fb_line_length; /**< Frame buffer Line length register */ 2359646SChris.Emmons@arm.com FbLineCountReg fb_line_count; /**< Frame buffer Line count register */ 23611090Sandreas.sandberg@arm.com int32_t fb_line_pitch; /**< Frame buffer Line pitch register */ 2379646SChris.Emmons@arm.com BusOptsReg bus_options; /**< Bus options register */ 2389646SChris.Emmons@arm.com TimingReg v_sync; /**< Vertical sync width register */ 2399646SChris.Emmons@arm.com TimingReg v_back_porch; /**< Vertical back porch width register */ 2409646SChris.Emmons@arm.com TimingReg v_data; /**< Vertical data width register */ 2419646SChris.Emmons@arm.com TimingReg v_front_porch; /**< Vertical front porch width register */ 2429646SChris.Emmons@arm.com TimingReg h_sync; /**< Horizontal sync width register */ 2439646SChris.Emmons@arm.com TimingReg h_back_porch; /**< Horizontal back porch width register */ 2449646SChris.Emmons@arm.com TimingReg h_data; /**< Horizontal data width register */ 2459646SChris.Emmons@arm.com TimingReg h_front_porch; /**< Horizontal front porch width reg */ 2469646SChris.Emmons@arm.com PolaritiesReg polarities; /**< Polarities register */ 2479646SChris.Emmons@arm.com CommandReg command; /**< Command register */ 2489646SChris.Emmons@arm.com PixelFormatReg pixel_format; /**< Pixel format register */ 2499646SChris.Emmons@arm.com ColorSelectReg red_select; /**< Red color select register */ 2509646SChris.Emmons@arm.com ColorSelectReg green_select; /**< Green color select register */ 2519646SChris.Emmons@arm.com ColorSelectReg blue_select; /**< Blue color select register */ 2529646SChris.Emmons@arm.com /** @} */ 2539646SChris.Emmons@arm.com 25411090Sandreas.sandberg@arm.com uint32_t readReg(Addr offset); 25511090Sandreas.sandberg@arm.com void writeReg(Addr offset, uint32_t value); 2569646SChris.Emmons@arm.com 25711090Sandreas.sandberg@arm.com PixelConverter pixelConverter() const; 25811090Sandreas.sandberg@arm.com DisplayTimings displayTimings() const; 25910839Sandreas.sandberg@arm.com 26011090Sandreas.sandberg@arm.com void createDmaEngine(); 26111090Sandreas.sandberg@arm.com 26211090Sandreas.sandberg@arm.com void cmdEnable(); 26311090Sandreas.sandberg@arm.com void cmdDisable(); 26411090Sandreas.sandberg@arm.com 26511090Sandreas.sandberg@arm.com bool enabled() const { return command.enable; } 26611090Sandreas.sandberg@arm.com 26711090Sandreas.sandberg@arm.com public: // Pixel pump callbacks 26811090Sandreas.sandberg@arm.com bool pxlNext(Pixel &p); 26911090Sandreas.sandberg@arm.com void pxlVSyncBegin(); 27011090Sandreas.sandberg@arm.com void pxlVSyncEnd(); 27111090Sandreas.sandberg@arm.com void pxlUnderrun(); 27211090Sandreas.sandberg@arm.com void pxlFrameDone(); 27311090Sandreas.sandberg@arm.com 27411090Sandreas.sandberg@arm.com protected: // Interrupt handling 27511090Sandreas.sandberg@arm.com /** 27611090Sandreas.sandberg@arm.com * Assign new interrupt values and update interrupt signals 27711090Sandreas.sandberg@arm.com * 27811090Sandreas.sandberg@arm.com * A new interrupt is scheduled signalled if the set of unmasked 27911090Sandreas.sandberg@arm.com * interrupts goes empty to non-empty. Conversely, if the set of 28011090Sandreas.sandberg@arm.com * unmasked interrupts goes from non-empty to empty, the interrupt 28111090Sandreas.sandberg@arm.com * signal is cleared. 28211090Sandreas.sandberg@arm.com * 28311090Sandreas.sandberg@arm.com * @param ints New <i>raw</i> interrupt status 28411090Sandreas.sandberg@arm.com * @param mask New interrupt mask 28511090Sandreas.sandberg@arm.com */ 28611090Sandreas.sandberg@arm.com void setInterrupts(uint32_t ints, uint32_t mask); 28711090Sandreas.sandberg@arm.com 28811090Sandreas.sandberg@arm.com /** 28911090Sandreas.sandberg@arm.com * Convenience function to update the interrupt mask 29011090Sandreas.sandberg@arm.com * 29111090Sandreas.sandberg@arm.com * @see setInterrupts 29211090Sandreas.sandberg@arm.com * @param mask New interrupt mask 29311090Sandreas.sandberg@arm.com */ 29411090Sandreas.sandberg@arm.com void intMask(uint32_t mask) { setInterrupts(int_rawstat, mask); } 29511090Sandreas.sandberg@arm.com 29611090Sandreas.sandberg@arm.com /** 29711090Sandreas.sandberg@arm.com * Convenience function to raise a new interrupt 29811090Sandreas.sandberg@arm.com * 29911090Sandreas.sandberg@arm.com * @see setInterrupts 30011090Sandreas.sandberg@arm.com * @param ints Set of interrupts to raise 30111090Sandreas.sandberg@arm.com */ 30211090Sandreas.sandberg@arm.com void intRaise(uint32_t ints) { 30311090Sandreas.sandberg@arm.com setInterrupts(int_rawstat | ints, int_mask); 30411090Sandreas.sandberg@arm.com } 30511090Sandreas.sandberg@arm.com 30611090Sandreas.sandberg@arm.com /** 30711090Sandreas.sandberg@arm.com * Convenience function to clear interrupts 30811090Sandreas.sandberg@arm.com * 30911090Sandreas.sandberg@arm.com * @see setInterrupts 31011090Sandreas.sandberg@arm.com * @param ints Set of interrupts to clear 31111090Sandreas.sandberg@arm.com */ 31211090Sandreas.sandberg@arm.com void intClear(uint32_t ints) { 31311090Sandreas.sandberg@arm.com setInterrupts(int_rawstat & ~ints, int_mask); 31411090Sandreas.sandberg@arm.com } 31511090Sandreas.sandberg@arm.com 31611090Sandreas.sandberg@arm.com /** Masked interrupt status register */ 31711090Sandreas.sandberg@arm.com const uint32_t intStatus() const { return int_rawstat & int_mask; } 31811090Sandreas.sandberg@arm.com 31911090Sandreas.sandberg@arm.com protected: // Pixel output 32011090Sandreas.sandberg@arm.com class PixelPump : public BasePixelPump 32111090Sandreas.sandberg@arm.com { 32211090Sandreas.sandberg@arm.com public: 32311090Sandreas.sandberg@arm.com PixelPump(HDLcd &p, ClockDomain &pxl_clk, unsigned pixel_chunk) 32411090Sandreas.sandberg@arm.com : BasePixelPump(p, pxl_clk, pixel_chunk), parent(p) {} 32511090Sandreas.sandberg@arm.com 32611090Sandreas.sandberg@arm.com void dumpSettings(); 32711090Sandreas.sandberg@arm.com 32811090Sandreas.sandberg@arm.com protected: 32911090Sandreas.sandberg@arm.com bool nextPixel(Pixel &p) M5_ATTR_OVERRIDE { return parent.pxlNext(p); } 33011090Sandreas.sandberg@arm.com 33111090Sandreas.sandberg@arm.com void onVSyncBegin() M5_ATTR_OVERRIDE { return parent.pxlVSyncBegin(); } 33211090Sandreas.sandberg@arm.com void onVSyncEnd() M5_ATTR_OVERRIDE { return parent.pxlVSyncEnd(); } 33311090Sandreas.sandberg@arm.com 33411090Sandreas.sandberg@arm.com void onUnderrun(unsigned x, unsigned y) M5_ATTR_OVERRIDE { 33511090Sandreas.sandberg@arm.com parent.pxlUnderrun(); 33611090Sandreas.sandberg@arm.com } 33711090Sandreas.sandberg@arm.com 33811090Sandreas.sandberg@arm.com void onFrameDone() M5_ATTR_OVERRIDE { parent.pxlFrameDone(); } 33911090Sandreas.sandberg@arm.com 34011090Sandreas.sandberg@arm.com protected: 34111090Sandreas.sandberg@arm.com HDLcd &parent; 34211090Sandreas.sandberg@arm.com }; 3439646SChris.Emmons@arm.com 3449646SChris.Emmons@arm.com /** Helper to write out bitmaps */ 34510839Sandreas.sandberg@arm.com Bitmap bmp; 3469646SChris.Emmons@arm.com 3479646SChris.Emmons@arm.com /** Picture of what the current frame buffer looks like */ 3489646SChris.Emmons@arm.com std::ostream *pic; 3499646SChris.Emmons@arm.com 35011090Sandreas.sandberg@arm.com /** Cached pixel converter, set when the converter is enabled. */ 35111090Sandreas.sandberg@arm.com PixelConverter conv; 35211090Sandreas.sandberg@arm.com 35311090Sandreas.sandberg@arm.com PixelPump pixelPump; 35411090Sandreas.sandberg@arm.com 35511090Sandreas.sandberg@arm.com protected: // DMA handling 35611090Sandreas.sandberg@arm.com class DmaEngine : public DmaReadFifo 3579646SChris.Emmons@arm.com { 35811090Sandreas.sandberg@arm.com public: 35911090Sandreas.sandberg@arm.com DmaEngine(HDLcd &_parent, size_t size, 36011090Sandreas.sandberg@arm.com unsigned request_size, unsigned max_pending, 36111090Sandreas.sandberg@arm.com size_t line_size, ssize_t line_pitch, unsigned num_lines); 3629646SChris.Emmons@arm.com 36311090Sandreas.sandberg@arm.com void startFrame(Addr fb_base); 36411090Sandreas.sandberg@arm.com void abortFrame(); 36511090Sandreas.sandberg@arm.com void dumpSettings(); 3669646SChris.Emmons@arm.com 36711090Sandreas.sandberg@arm.com void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; 36811090Sandreas.sandberg@arm.com void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; 3699646SChris.Emmons@arm.com 37011090Sandreas.sandberg@arm.com protected: 37111090Sandreas.sandberg@arm.com void onEndOfBlock() M5_ATTR_OVERRIDE; 37211090Sandreas.sandberg@arm.com void onIdle() M5_ATTR_OVERRIDE; 3739646SChris.Emmons@arm.com 37411090Sandreas.sandberg@arm.com HDLcd &parent; 37511090Sandreas.sandberg@arm.com const size_t lineSize; 37611090Sandreas.sandberg@arm.com const ssize_t linePitch; 37711090Sandreas.sandberg@arm.com const unsigned numLines; 3789646SChris.Emmons@arm.com 37911090Sandreas.sandberg@arm.com Addr nextLineAddr; 38011090Sandreas.sandberg@arm.com Addr frameEnd; 3819646SChris.Emmons@arm.com }; 3829646SChris.Emmons@arm.com 38311090Sandreas.sandberg@arm.com std::unique_ptr<DmaEngine> dmaEngine; 3849646SChris.Emmons@arm.com}; 3859646SChris.Emmons@arm.com 3869646SChris.Emmons@arm.com#endif 387