hdlcd.hh revision 11090
1/* 2 * Copyright (c) 2010-2013, 2015 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Chris Emmons 38 * Andreas Sandberg 39 */ 40 41 42/** @file 43 * Implementiation of the ARM HDLcd controller. 44 * 45 * This implementation aims to have sufficient detail such that underrun 46 * conditions are reasonable / behave similar to reality. There are two 47 * 'engines' going at once. First, the DMA engine running at LCD clock 48 * frequency is responsible for filling the controller's internal buffer. 49 * The second engine runs at the pixel clock frequency and reads the pixels 50 * out of the internal buffer. The pixel rendering engine uses front / back 51 * porch and sync delays between lines and frames. 52 * 53 * If the pixel rendering engine does not have a pixel to display, it will 54 * cause an underrun event. The HDLcd controller, per spec, will stop 55 * issuing DMA requests for the rest of the frame and resume normal behavior 56 * on the subsequent frame. What pixels are rendered upon an underrun 57 * condition is different than the real hardware; while the user will see 58 * artifacts (previous frame mixed with current frame), it is not the same 59 * behavior as real hardware which repeats the last pixel value for the rest 60 * of the current frame. This compromise was made to save on memory and 61 * complexity and assumes that it is not important to accurately model the 62 * content of an underrun frame. 63 * 64 * KNOWN ISSUES 65 * <ul> 66 * <li>The HDLcd is implemented here as an AmbaDmaDevice, but it 67 * doesn't have an AMBA ID as far as I know. That is the only 68 * bit of the AmbaDmaDevice interface that is irrelevant to it, 69 * so a fake AMBA ID is used for now. I didn't think inserting 70 * an extra layer of hierachy between AmbaDmaDevice and 71 * DmaDevice would be helpful to anyone else, but that may be 72 * the right answer. 73 * </ul> 74 */ 75 76#ifndef __DEV_ARM_HDLCD_HH__ 77#define __DEV_ARM_HDLCD_HH__ 78 79#include <fstream> 80#include <memory> 81 82#include "base/bitmap.hh" 83#include "base/framebuffer.hh" 84#include "dev/arm/amba_device.hh" 85#include "dev/pixelpump.hh" 86#include "sim/serialize.hh" 87 88class VncInput; 89struct HDLcdParams; 90class HDLcdPixelPump; 91 92class HDLcd: public AmbaDmaDevice 93{ 94 public: 95 HDLcd(const HDLcdParams *p); 96 ~HDLcd(); 97 98 void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; 99 void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; 100 101 void drainResume() M5_ATTR_OVERRIDE; 102 103 public: // IO device interface 104 Tick read(PacketPtr pkt) M5_ATTR_OVERRIDE; 105 Tick write(PacketPtr pkt) M5_ATTR_OVERRIDE; 106 107 AddrRangeList getAddrRanges() const M5_ATTR_OVERRIDE { return addrRanges; } 108 109 protected: // Parameters 110 VncInput *vnc; 111 const bool workaroundSwapRB; 112 const bool workaroundDmaLineCount; 113 const AddrRangeList addrRanges; 114 const bool enableCapture; 115 const Addr pixelBufferSize; 116 117 protected: // Register handling 118 /** ARM HDLcd register offsets */ 119 enum RegisterOffset { 120 Version = 0x0000, 121 Int_RawStat = 0x0010, 122 Int_Clear = 0x0014, 123 Int_Mask = 0x0018, 124 Int_Status = 0x001C, 125 Fb_Base = 0x0100, 126 Fb_Line_Length = 0x0104, 127 Fb_Line_Count = 0x0108, 128 Fb_Line_Pitch = 0x010C, 129 Bus_Options = 0x0110, 130 V_Sync = 0x0200, 131 V_Back_Porch = 0x0204, 132 V_Data = 0x0208, 133 V_Front_Porch = 0x020C, 134 H_Sync = 0x0210, 135 H_Back_Porch = 0x0214, 136 H_Data = 0x0218, 137 H_Front_Porch = 0x021C, 138 Polarities = 0x0220, 139 Command = 0x0230, 140 Pixel_Format = 0x0240, 141 Red_Select = 0x0244, 142 Green_Select = 0x0248, 143 Blue_Select = 0x024C, 144 }; 145 146 /** Reset value for Bus_Options register */ 147 static constexpr size_t BUS_OPTIONS_RESETV = 0x408; 148 149 /** Reset value for Version register */ 150 static constexpr size_t VERSION_RESETV = 0x1CDC0000; 151 152 /** AXI port width in bytes */ 153 static constexpr size_t AXI_PORT_WIDTH = 8; 154 155 /** max number of beats delivered in one dma burst */ 156 static constexpr size_t MAX_BURST_LEN = 16; 157 158 /** Maximum number of bytes per pixel */ 159 static constexpr size_t MAX_PIXEL_SIZE = 4; 160 161 /** 162 * @name RegisterFieldLayouts 163 * Bit layout declarations for multi-field registers. 164 */ 165 /**@{*/ 166 BitUnion32(VersionReg) 167 Bitfield<7,0> version_minor; 168 Bitfield<15,8> version_major; 169 Bitfield<31,16> product_id; 170 EndBitUnion(VersionReg) 171 172 static constexpr uint32_t INT_DMA_END = (1UL << 0); 173 static constexpr uint32_t INT_BUS_ERROR = (1UL << 1); 174 static constexpr uint32_t INT_VSYNC = (1UL << 2); 175 static constexpr uint32_t INT_UNDERRUN = (1UL << 3); 176 177 BitUnion32(FbLineCountReg) 178 Bitfield<11,0> fb_line_count; 179 Bitfield<31,12> reserved_31_12; 180 EndBitUnion(FbLineCountReg) 181 182 BitUnion32(BusOptsReg) 183 Bitfield<4,0> burst_len; 184 Bitfield<7,5> reserved_7_5; 185 Bitfield<11,8> max_outstanding; 186 Bitfield<31,12> reserved_31_12; 187 EndBitUnion(BusOptsReg) 188 189 BitUnion32(TimingReg) 190 Bitfield<11,0> val; 191 Bitfield<31,12> reserved_31_12; 192 EndBitUnion(TimingReg) 193 194 BitUnion32(PolaritiesReg) 195 Bitfield<0> vsync_polarity; 196 Bitfield<1> hsync_polarity; 197 Bitfield<2> dataen_polarity; 198 Bitfield<3> data_polarity; 199 Bitfield<4> pxlclk_polarity; 200 Bitfield<31,5> reserved_31_5; 201 EndBitUnion(PolaritiesReg) 202 203 BitUnion32(CommandReg) 204 Bitfield<0> enable; 205 Bitfield<31,1> reserved_31_1; 206 EndBitUnion(CommandReg) 207 208 BitUnion32(PixelFormatReg) 209 Bitfield<2,0> reserved_2_0; 210 Bitfield<4,3> bytes_per_pixel; 211 Bitfield<30,5> reserved_30_5; 212 Bitfield<31> big_endian; 213 EndBitUnion(PixelFormatReg) 214 215 BitUnion32(ColorSelectReg) 216 Bitfield<4,0> offset; 217 Bitfield<7,5> reserved_7_5; 218 Bitfield<11,8> size; 219 Bitfield<15,12> reserved_15_12; 220 Bitfield<23,16> default_color; 221 Bitfield<31,24> reserved_31_24; 222 EndBitUnion(ColorSelectReg) 223 /**@}*/ 224 225 /** 226 * @name HDLCDRegisters 227 * HDLCD register contents. 228 */ 229 /**@{*/ 230 const VersionReg version; /**< Version register */ 231 uint32_t int_rawstat; /**< Interrupt raw status register */ 232 uint32_t int_mask; /**< Interrupt mask register */ 233 uint32_t fb_base; /**< Frame buffer base address register */ 234 uint32_t fb_line_length; /**< Frame buffer Line length register */ 235 FbLineCountReg fb_line_count; /**< Frame buffer Line count register */ 236 int32_t fb_line_pitch; /**< Frame buffer Line pitch register */ 237 BusOptsReg bus_options; /**< Bus options register */ 238 TimingReg v_sync; /**< Vertical sync width register */ 239 TimingReg v_back_porch; /**< Vertical back porch width register */ 240 TimingReg v_data; /**< Vertical data width register */ 241 TimingReg v_front_porch; /**< Vertical front porch width register */ 242 TimingReg h_sync; /**< Horizontal sync width register */ 243 TimingReg h_back_porch; /**< Horizontal back porch width register */ 244 TimingReg h_data; /**< Horizontal data width register */ 245 TimingReg h_front_porch; /**< Horizontal front porch width reg */ 246 PolaritiesReg polarities; /**< Polarities register */ 247 CommandReg command; /**< Command register */ 248 PixelFormatReg pixel_format; /**< Pixel format register */ 249 ColorSelectReg red_select; /**< Red color select register */ 250 ColorSelectReg green_select; /**< Green color select register */ 251 ColorSelectReg blue_select; /**< Blue color select register */ 252 /** @} */ 253 254 uint32_t readReg(Addr offset); 255 void writeReg(Addr offset, uint32_t value); 256 257 PixelConverter pixelConverter() const; 258 DisplayTimings displayTimings() const; 259 260 void createDmaEngine(); 261 262 void cmdEnable(); 263 void cmdDisable(); 264 265 bool enabled() const { return command.enable; } 266 267 public: // Pixel pump callbacks 268 bool pxlNext(Pixel &p); 269 void pxlVSyncBegin(); 270 void pxlVSyncEnd(); 271 void pxlUnderrun(); 272 void pxlFrameDone(); 273 274 protected: // Interrupt handling 275 /** 276 * Assign new interrupt values and update interrupt signals 277 * 278 * A new interrupt is scheduled signalled if the set of unmasked 279 * interrupts goes empty to non-empty. Conversely, if the set of 280 * unmasked interrupts goes from non-empty to empty, the interrupt 281 * signal is cleared. 282 * 283 * @param ints New <i>raw</i> interrupt status 284 * @param mask New interrupt mask 285 */ 286 void setInterrupts(uint32_t ints, uint32_t mask); 287 288 /** 289 * Convenience function to update the interrupt mask 290 * 291 * @see setInterrupts 292 * @param mask New interrupt mask 293 */ 294 void intMask(uint32_t mask) { setInterrupts(int_rawstat, mask); } 295 296 /** 297 * Convenience function to raise a new interrupt 298 * 299 * @see setInterrupts 300 * @param ints Set of interrupts to raise 301 */ 302 void intRaise(uint32_t ints) { 303 setInterrupts(int_rawstat | ints, int_mask); 304 } 305 306 /** 307 * Convenience function to clear interrupts 308 * 309 * @see setInterrupts 310 * @param ints Set of interrupts to clear 311 */ 312 void intClear(uint32_t ints) { 313 setInterrupts(int_rawstat & ~ints, int_mask); 314 } 315 316 /** Masked interrupt status register */ 317 const uint32_t intStatus() const { return int_rawstat & int_mask; } 318 319 protected: // Pixel output 320 class PixelPump : public BasePixelPump 321 { 322 public: 323 PixelPump(HDLcd &p, ClockDomain &pxl_clk, unsigned pixel_chunk) 324 : BasePixelPump(p, pxl_clk, pixel_chunk), parent(p) {} 325 326 void dumpSettings(); 327 328 protected: 329 bool nextPixel(Pixel &p) M5_ATTR_OVERRIDE { return parent.pxlNext(p); } 330 331 void onVSyncBegin() M5_ATTR_OVERRIDE { return parent.pxlVSyncBegin(); } 332 void onVSyncEnd() M5_ATTR_OVERRIDE { return parent.pxlVSyncEnd(); } 333 334 void onUnderrun(unsigned x, unsigned y) M5_ATTR_OVERRIDE { 335 parent.pxlUnderrun(); 336 } 337 338 void onFrameDone() M5_ATTR_OVERRIDE { parent.pxlFrameDone(); } 339 340 protected: 341 HDLcd &parent; 342 }; 343 344 /** Helper to write out bitmaps */ 345 Bitmap bmp; 346 347 /** Picture of what the current frame buffer looks like */ 348 std::ostream *pic; 349 350 /** Cached pixel converter, set when the converter is enabled. */ 351 PixelConverter conv; 352 353 PixelPump pixelPump; 354 355 protected: // DMA handling 356 class DmaEngine : public DmaReadFifo 357 { 358 public: 359 DmaEngine(HDLcd &_parent, size_t size, 360 unsigned request_size, unsigned max_pending, 361 size_t line_size, ssize_t line_pitch, unsigned num_lines); 362 363 void startFrame(Addr fb_base); 364 void abortFrame(); 365 void dumpSettings(); 366 367 void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; 368 void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; 369 370 protected: 371 void onEndOfBlock() M5_ATTR_OVERRIDE; 372 void onIdle() M5_ATTR_OVERRIDE; 373 374 HDLcd &parent; 375 const size_t lineSize; 376 const ssize_t linePitch; 377 const unsigned numLines; 378 379 Addr nextLineAddr; 380 Addr frameEnd; 381 }; 382 383 std::unique_ptr<DmaEngine> dmaEngine; 384}; 385 386#endif 387