tsunami_cchip.cc revision 9808
12381SN/A/* 22381SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 32381SN/A * All rights reserved. 42381SN/A * 52381SN/A * Redistribution and use in source and binary forms, with or without 62381SN/A * modification, are permitted provided that the following conditions are 72381SN/A * met: redistributions of source code must retain the above copyright 82381SN/A * notice, this list of conditions and the following disclaimer; 92381SN/A * redistributions in binary form must reproduce the above copyright 102381SN/A * notice, this list of conditions and the following disclaimer in the 112381SN/A * documentation and/or other materials provided with the distribution; 122381SN/A * neither the name of the copyright holders nor the names of its 132381SN/A * contributors may be used to endorse or promote products derived from 142381SN/A * this software without specific prior written permission. 152381SN/A * 162381SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172381SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182381SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192381SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202381SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212381SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222381SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232381SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242381SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252381SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262381SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Ali Saidi 292665Ssaidi@eecs.umich.edu * Ron Dreslinski 302665Ssaidi@eecs.umich.edu */ 312381SN/A 322381SN/A/** @file 332381SN/A * Emulation of the Tsunami CChip CSRs 342982Sstever@eecs.umich.edu */ 352982Sstever@eecs.umich.edu 362381SN/A#include <deque> 372381SN/A#include <string> 382381SN/A#include <vector> 392381SN/A 402381SN/A#include "arch/alpha/ev5.hh" 412381SN/A#include "base/trace.hh" 422423SN/A#include "config/the_isa.hh" 432972Sgblack@eecs.umich.edu#include "cpu/intr_control.hh" 442394SN/A#include "cpu/thread_context.hh" 452394SN/A#include "debug/IPI.hh" 462394SN/A#include "debug/Tsunami.hh" 472394SN/A#include "dev/alpha/tsunami.hh" 482394SN/A#include "dev/alpha/tsunami_cchip.hh" 492812Srdreslin@umich.edu#include "dev/alpha/tsunamireg.h" 502395SN/A#include "mem/packet.hh" 512395SN/A#include "mem/packet_access.hh" 522395SN/A#include "mem/port.hh" 532395SN/A#include "params/TsunamiCChip.hh" 542395SN/A#include "sim/system.hh" 552395SN/A 562395SN/A//Should this be AlphaISA? 572395SN/Ausing namespace TheISA; 582395SN/A 592395SN/ATsunamiCChip::TsunamiCChip(const Params *p) 602395SN/A : BasicPioDevice(p, 0x10000000), tsunami(p->tsunami) 612395SN/A{ 622397SN/A drir = 0; 632397SN/A ipint = 0; 642397SN/A itint = 0; 652397SN/A 662495SN/A for (int x = 0; x < Tsunami::Max_CPUs; x++) 672495SN/A { 682814Srdreslin@umich.edu dim[x] = 0; 692814Srdreslin@umich.edu dir[x] = 0; 702395SN/A } 712381SN/A 722381SN/A //Put back pointer in tsunami 732663Sstever@eecs.umich.edu tsunami->cchip = this; 742663Sstever@eecs.umich.edu} 752663Sstever@eecs.umich.edu 762663Sstever@eecs.umich.eduTick 772663Sstever@eecs.umich.eduTsunamiCChip::read(PacketPtr pkt) 782532SN/A{ 792663Sstever@eecs.umich.edu DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize()); 802663Sstever@eecs.umich.edu 812663Sstever@eecs.umich.edu assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 822663Sstever@eecs.umich.edu 832381SN/A Addr regnum = (pkt->getAddr() - pioAddr) >> 6; 842395SN/A Addr daddr = (pkt->getAddr() - pioAddr); 852532SN/A 862395SN/A pkt->allocate(); 872384SN/A switch (pkt->getSize()) { 882663Sstever@eecs.umich.edu 892663Sstever@eecs.umich.edu case sizeof(uint64_t): 902663Sstever@eecs.umich.edu pkt->set<uint64_t>(0); 912663Sstever@eecs.umich.edu 922663Sstever@eecs.umich.edu if (daddr & TSDEV_CC_BDIMS) 932384SN/A { 942384SN/A pkt->set(dim[(daddr >> 4) & 0x3F]); 952384SN/A break; 962663Sstever@eecs.umich.edu } 972663Sstever@eecs.umich.edu 982384SN/A if (daddr & TSDEV_CC_BDIRS) 992384SN/A { 1002384SN/A pkt->set(dir[(daddr >> 4) & 0x3F]); 1012384SN/A break; 1022663Sstever@eecs.umich.edu } 1032384SN/A 1042663Sstever@eecs.umich.edu switch(regnum) { 1052384SN/A case TSDEV_CC_CSR: 1062384SN/A pkt->set(0x0); 1072381SN/A break; 1082381SN/A case TSDEV_CC_MTR: 1092663Sstever@eecs.umich.edu panic("TSDEV_CC_MTR not implemeted\n"); 1102663Sstever@eecs.umich.edu break; 1112663Sstever@eecs.umich.edu case TSDEV_CC_MISC: 1122663Sstever@eecs.umich.edu pkt->set(((ipint << 8) & 0xF) | ((itint << 4) & 0xF) | 1132663Sstever@eecs.umich.edu (pkt->req->contextId() & 0x3)); 1142663Sstever@eecs.umich.edu // currently, FS cannot handle MT so contextId and 1152663Sstever@eecs.umich.edu // cpuId are effectively the same, don't know if it will 1162663Sstever@eecs.umich.edu // matter if FS becomes MT enabled. I suspect no because 1172663Sstever@eecs.umich.edu // we are currently able to boot up to 64 procs anyway 1182663Sstever@eecs.umich.edu // which would render the CPUID of this register useless 1192532SN/A // anyway 1202532SN/A break; 1212532SN/A case TSDEV_CC_AAR0: 1222663Sstever@eecs.umich.edu case TSDEV_CC_AAR1: 1232663Sstever@eecs.umich.edu case TSDEV_CC_AAR2: 1242663Sstever@eecs.umich.edu case TSDEV_CC_AAR3: 1252663Sstever@eecs.umich.edu pkt->set(0); 1262663Sstever@eecs.umich.edu break; 1272532SN/A case TSDEV_CC_DIM0: 1282663Sstever@eecs.umich.edu pkt->set(dim[0]); 1292663Sstever@eecs.umich.edu break; 1302663Sstever@eecs.umich.edu case TSDEV_CC_DIM1: 1312663Sstever@eecs.umich.edu pkt->set(dim[1]); 1322663Sstever@eecs.umich.edu break; 1332663Sstever@eecs.umich.edu case TSDEV_CC_DIM2: 1342663Sstever@eecs.umich.edu pkt->set(dim[2]); 1352532SN/A break; 1362669Sktlim@umich.edu case TSDEV_CC_DIM3: 1372669Sktlim@umich.edu pkt->set(dim[3]); 1382669Sktlim@umich.edu break; 1392669Sktlim@umich.edu case TSDEV_CC_DIR0: 1402669Sktlim@umich.edu pkt->set(dir[0]); 1412669Sktlim@umich.edu break; 1422669Sktlim@umich.edu case TSDEV_CC_DIR1: 1432663Sstever@eecs.umich.edu pkt->set(dir[1]); 1442663Sstever@eecs.umich.edu break; 1452663Sstever@eecs.umich.edu case TSDEV_CC_DIR2: 1462663Sstever@eecs.umich.edu pkt->set(dir[2]); 1472663Sstever@eecs.umich.edu break; 1482663Sstever@eecs.umich.edu case TSDEV_CC_DIR3: 1492663Sstever@eecs.umich.edu pkt->set(dir[3]); 1502663Sstever@eecs.umich.edu break; 1512532SN/A case TSDEV_CC_DRIR: 1522663Sstever@eecs.umich.edu pkt->set(drir); 1532663Sstever@eecs.umich.edu break; 1542663Sstever@eecs.umich.edu case TSDEV_CC_PRBEN: 1552663Sstever@eecs.umich.edu panic("TSDEV_CC_PRBEN not implemented\n"); 1562663Sstever@eecs.umich.edu break; 1572663Sstever@eecs.umich.edu case TSDEV_CC_IIC0: 1582663Sstever@eecs.umich.edu case TSDEV_CC_IIC1: 1592663Sstever@eecs.umich.edu case TSDEV_CC_IIC2: 1602663Sstever@eecs.umich.edu case TSDEV_CC_IIC3: 1612663Sstever@eecs.umich.edu panic("TSDEV_CC_IICx not implemented\n"); 1622663Sstever@eecs.umich.edu break; 1632663Sstever@eecs.umich.edu case TSDEV_CC_MPR0: 1642663Sstever@eecs.umich.edu case TSDEV_CC_MPR1: 1652663Sstever@eecs.umich.edu case TSDEV_CC_MPR2: 1662532SN/A case TSDEV_CC_MPR3: 1672663Sstever@eecs.umich.edu panic("TSDEV_CC_MPRx not implemented\n"); 1682663Sstever@eecs.umich.edu break; 1692663Sstever@eecs.umich.edu case TSDEV_CC_IPIR: 1702663Sstever@eecs.umich.edu pkt->set(ipint); 1712663Sstever@eecs.umich.edu break; 1722663Sstever@eecs.umich.edu case TSDEV_CC_ITIR: 1732663Sstever@eecs.umich.edu pkt->set(itint); 1742663Sstever@eecs.umich.edu break; 1752663Sstever@eecs.umich.edu default: 1762663Sstever@eecs.umich.edu panic("default in cchip read reached, accessing 0x%x\n"); 1772663Sstever@eecs.umich.edu } // uint64_t 1782663Sstever@eecs.umich.edu 1792663Sstever@eecs.umich.edu break; 1802663Sstever@eecs.umich.edu case sizeof(uint32_t): 1812663Sstever@eecs.umich.edu case sizeof(uint16_t): 1822663Sstever@eecs.umich.edu case sizeof(uint8_t): 1832532SN/A default: 1842663Sstever@eecs.umich.edu panic("invalid access size(?) for tsunami register!\n"); 1852663Sstever@eecs.umich.edu } 1862663Sstever@eecs.umich.edu DPRINTF(Tsunami, "Tsunami CChip: read regnum=%#x size=%d data=%lld\n", 1872663Sstever@eecs.umich.edu regnum, pkt->getSize(), pkt->get<uint64_t>()); 1882663Sstever@eecs.umich.edu 1892663Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 1902663Sstever@eecs.umich.edu return pioDelay; 1912663Sstever@eecs.umich.edu} 1922663Sstever@eecs.umich.edu 1932663Sstever@eecs.umich.eduTick 1942663Sstever@eecs.umich.eduTsunamiCChip::write(PacketPtr pkt) 1952532SN/A{ 1962663Sstever@eecs.umich.edu assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 1972663Sstever@eecs.umich.edu Addr daddr = pkt->getAddr() - pioAddr; 1982663Sstever@eecs.umich.edu Addr regnum = (pkt->getAddr() - pioAddr) >> 6 ; 1992663Sstever@eecs.umich.edu 2002663Sstever@eecs.umich.edu 2012663Sstever@eecs.umich.edu assert(pkt->getSize() == sizeof(uint64_t)); 2022663Sstever@eecs.umich.edu 2032663Sstever@eecs.umich.edu DPRINTF(Tsunami, "write - addr=%#x value=%#x\n", pkt->getAddr(), pkt->get<uint64_t>()); 2042663Sstever@eecs.umich.edu 2052663Sstever@eecs.umich.edu bool supportedWrite = false; 2062663Sstever@eecs.umich.edu 2072663Sstever@eecs.umich.edu 2082663Sstever@eecs.umich.edu if (daddr & TSDEV_CC_BDIMS) 2092663Sstever@eecs.umich.edu { 2102663Sstever@eecs.umich.edu int number = (daddr >> 4) & 0x3F; 2112663Sstever@eecs.umich.edu 2122663Sstever@eecs.umich.edu uint64_t bitvector; 2132663Sstever@eecs.umich.edu uint64_t olddim; 2142663Sstever@eecs.umich.edu uint64_t olddir; 2152663Sstever@eecs.umich.edu 2162679Sktlim@umich.edu olddim = dim[number]; 2172679Sktlim@umich.edu olddir = dir[number]; 2182663Sstever@eecs.umich.edu dim[number] = pkt->get<uint64_t>(); 2192663Sstever@eecs.umich.edu dir[number] = dim[number] & drir; 2202663Sstever@eecs.umich.edu for(int x = 0; x < Tsunami::Max_CPUs; x++) 2212663Sstever@eecs.umich.edu { 2222663Sstever@eecs.umich.edu bitvector = ULL(1) << x; 2232663Sstever@eecs.umich.edu // Figure out which bits have changed 2242663Sstever@eecs.umich.edu if ((dim[number] & bitvector) != (olddim & bitvector)) 2252663Sstever@eecs.umich.edu { 2262663Sstever@eecs.umich.edu // The bit is now set and it wasn't before (set) 2272663Sstever@eecs.umich.edu if((dim[number] & bitvector) && (dir[number] & bitvector)) 2282663Sstever@eecs.umich.edu { 2292663Sstever@eecs.umich.edu tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x); 2302663Sstever@eecs.umich.edu DPRINTF(Tsunami, "dim write resulting in posting dir" 2312532SN/A " interrupt to cpu %d\n", number); 2322811Srdreslin@umich.edu } 2332811Srdreslin@umich.edu else if ((olddir & bitvector) && 2342811Srdreslin@umich.edu !(dir[number] & bitvector)) 2352814Srdreslin@umich.edu { 2362814Srdreslin@umich.edu // The bit was set and now its now clear and 2372641Sstever@eecs.umich.edu // we were interrupting on that bit before 2382384SN/A tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x); 2392381SN/A DPRINTF(Tsunami, "dim write resulting in clear" 2402381SN/A " dir interrupt to cpu %d\n", number); 241 242 } 243 244 245 } 246 } 247 } else { 248 switch(regnum) { 249 case TSDEV_CC_CSR: 250 panic("TSDEV_CC_CSR write\n"); 251 case TSDEV_CC_MTR: 252 panic("TSDEV_CC_MTR write not implemented\n"); 253 case TSDEV_CC_MISC: 254 uint64_t ipreq; 255 ipreq = (pkt->get<uint64_t>() >> 12) & 0xF; 256 //If it is bit 12-15, this is an IPI post 257 if (ipreq) { 258 reqIPI(ipreq); 259 supportedWrite = true; 260 } 261 262 //If it is bit 8-11, this is an IPI clear 263 uint64_t ipintr; 264 ipintr = (pkt->get<uint64_t>() >> 8) & 0xF; 265 if (ipintr) { 266 clearIPI(ipintr); 267 supportedWrite = true; 268 } 269 270 //If it is the 4-7th bit, clear the RTC interrupt 271 uint64_t itintr; 272 itintr = (pkt->get<uint64_t>() >> 4) & 0xF; 273 if (itintr) { 274 clearITI(itintr); 275 supportedWrite = true; 276 } 277 278 // ignore NXMs 279 if (pkt->get<uint64_t>() & 0x10000000) 280 supportedWrite = true; 281 282 if(!supportedWrite) 283 panic("TSDEV_CC_MISC write not implemented\n"); 284 285 break; 286 case TSDEV_CC_AAR0: 287 case TSDEV_CC_AAR1: 288 case TSDEV_CC_AAR2: 289 case TSDEV_CC_AAR3: 290 panic("TSDEV_CC_AARx write not implemeted\n"); 291 case TSDEV_CC_DIM0: 292 case TSDEV_CC_DIM1: 293 case TSDEV_CC_DIM2: 294 case TSDEV_CC_DIM3: 295 int number; 296 if(regnum == TSDEV_CC_DIM0) 297 number = 0; 298 else if(regnum == TSDEV_CC_DIM1) 299 number = 1; 300 else if(regnum == TSDEV_CC_DIM2) 301 number = 2; 302 else 303 number = 3; 304 305 uint64_t bitvector; 306 uint64_t olddim; 307 uint64_t olddir; 308 309 olddim = dim[number]; 310 olddir = dir[number]; 311 dim[number] = pkt->get<uint64_t>(); 312 dir[number] = dim[number] & drir; 313 for(int x = 0; x < 64; x++) 314 { 315 bitvector = ULL(1) << x; 316 // Figure out which bits have changed 317 if ((dim[number] & bitvector) != (olddim & bitvector)) 318 { 319 // The bit is now set and it wasn't before (set) 320 if((dim[number] & bitvector) && (dir[number] & bitvector)) 321 { 322 tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x); 323 DPRINTF(Tsunami, "posting dir interrupt to cpu 0\n"); 324 } 325 else if ((olddir & bitvector) && 326 !(dir[number] & bitvector)) 327 { 328 // The bit was set and now its now clear and 329 // we were interrupting on that bit before 330 tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x); 331 DPRINTF(Tsunami, "dim write resulting in clear" 332 " dir interrupt to cpu %d\n", 333 x); 334 335 } 336 337 338 } 339 } 340 break; 341 case TSDEV_CC_DIR0: 342 case TSDEV_CC_DIR1: 343 case TSDEV_CC_DIR2: 344 case TSDEV_CC_DIR3: 345 panic("TSDEV_CC_DIR write not implemented\n"); 346 case TSDEV_CC_DRIR: 347 panic("TSDEV_CC_DRIR write not implemented\n"); 348 case TSDEV_CC_PRBEN: 349 panic("TSDEV_CC_PRBEN write not implemented\n"); 350 case TSDEV_CC_IIC0: 351 case TSDEV_CC_IIC1: 352 case TSDEV_CC_IIC2: 353 case TSDEV_CC_IIC3: 354 panic("TSDEV_CC_IICx write not implemented\n"); 355 case TSDEV_CC_MPR0: 356 case TSDEV_CC_MPR1: 357 case TSDEV_CC_MPR2: 358 case TSDEV_CC_MPR3: 359 panic("TSDEV_CC_MPRx write not implemented\n"); 360 case TSDEV_CC_IPIR: 361 clearIPI(pkt->get<uint64_t>()); 362 break; 363 case TSDEV_CC_ITIR: 364 clearITI(pkt->get<uint64_t>()); 365 break; 366 case TSDEV_CC_IPIQ: 367 reqIPI(pkt->get<uint64_t>()); 368 break; 369 default: 370 panic("default in cchip read reached, accessing 0x%x\n"); 371 } // swtich(regnum) 372 } // not BIG_TSUNAMI write 373 pkt->makeAtomicResponse(); 374 return pioDelay; 375} 376 377void 378TsunamiCChip::clearIPI(uint64_t ipintr) 379{ 380 int numcpus = sys->threadContexts.size(); 381 assert(numcpus <= Tsunami::Max_CPUs); 382 383 if (ipintr) { 384 for (int cpunum=0; cpunum < numcpus; cpunum++) { 385 // Check each cpu bit 386 uint64_t cpumask = ULL(1) << cpunum; 387 if (ipintr & cpumask) { 388 // Check if there is a pending ipi 389 if (ipint & cpumask) { 390 ipint &= ~cpumask; 391 tsunami->intrctrl->clear(cpunum, TheISA::INTLEVEL_IRQ3, 0); 392 DPRINTF(IPI, "clear IPI IPI cpu=%d\n", cpunum); 393 } 394 else 395 warn("clear IPI for CPU=%d, but NO IPI\n", cpunum); 396 } 397 } 398 } 399 else 400 panic("Big IPI Clear, but not processors indicated\n"); 401} 402 403void 404TsunamiCChip::clearITI(uint64_t itintr) 405{ 406 int numcpus = sys->threadContexts.size(); 407 assert(numcpus <= Tsunami::Max_CPUs); 408 409 if (itintr) { 410 for (int i=0; i < numcpus; i++) { 411 uint64_t cpumask = ULL(1) << i; 412 if (itintr & cpumask & itint) { 413 tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ2, 0); 414 itint &= ~cpumask; 415 DPRINTF(Tsunami, "clearing rtc interrupt to cpu=%d\n", i); 416 } 417 } 418 } 419 else 420 panic("Big ITI Clear, but not processors indicated\n"); 421} 422 423void 424TsunamiCChip::reqIPI(uint64_t ipreq) 425{ 426 int numcpus = sys->threadContexts.size(); 427 assert(numcpus <= Tsunami::Max_CPUs); 428 429 if (ipreq) { 430 for (int cpunum=0; cpunum < numcpus; cpunum++) { 431 // Check each cpu bit 432 uint64_t cpumask = ULL(1) << cpunum; 433 if (ipreq & cpumask) { 434 // Check if there is already an ipi (bits 8:11) 435 if (!(ipint & cpumask)) { 436 ipint |= cpumask; 437 tsunami->intrctrl->post(cpunum, TheISA::INTLEVEL_IRQ3, 0); 438 DPRINTF(IPI, "send IPI cpu=%d\n", cpunum); 439 } 440 else 441 warn("post IPI for CPU=%d, but IPI already\n", cpunum); 442 } 443 } 444 } 445 else 446 panic("Big IPI Request, but not processors indicated\n"); 447} 448 449 450void 451TsunamiCChip::postRTC() 452{ 453 int size = sys->threadContexts.size(); 454 assert(size <= Tsunami::Max_CPUs); 455 456 for (int i = 0; i < size; i++) { 457 uint64_t cpumask = ULL(1) << i; 458 if (!(cpumask & itint)) { 459 itint |= cpumask; 460 tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ2, 0); 461 DPRINTF(Tsunami, "Posting RTC interrupt to cpu=%d\n", i); 462 } 463 } 464 465} 466 467void 468TsunamiCChip::postDRIR(uint32_t interrupt) 469{ 470 uint64_t bitvector = ULL(1) << interrupt; 471 uint64_t size = sys->threadContexts.size(); 472 assert(size <= Tsunami::Max_CPUs); 473 drir |= bitvector; 474 475 for(int i=0; i < size; i++) { 476 dir[i] = dim[i] & drir; 477 if (dim[i] & bitvector) { 478 tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ1, interrupt); 479 DPRINTF(Tsunami, "posting dir interrupt to cpu %d," 480 "interrupt %d\n",i, interrupt); 481 } 482 } 483} 484 485void 486TsunamiCChip::clearDRIR(uint32_t interrupt) 487{ 488 uint64_t bitvector = ULL(1) << interrupt; 489 uint64_t size = sys->threadContexts.size(); 490 assert(size <= Tsunami::Max_CPUs); 491 492 if (drir & bitvector) 493 { 494 drir &= ~bitvector; 495 for(int i=0; i < size; i++) { 496 if (dir[i] & bitvector) { 497 tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ1, interrupt); 498 DPRINTF(Tsunami, "clearing dir interrupt to cpu %d," 499 "interrupt %d\n",i, interrupt); 500 501 } 502 dir[i] = dim[i] & drir; 503 } 504 } 505 else 506 DPRINTF(Tsunami, "Spurrious clear? interrupt %d\n", interrupt); 507} 508 509 510void 511TsunamiCChip::serialize(std::ostream &os) 512{ 513 SERIALIZE_ARRAY(dim, Tsunami::Max_CPUs); 514 SERIALIZE_ARRAY(dir, Tsunami::Max_CPUs); 515 SERIALIZE_SCALAR(ipint); 516 SERIALIZE_SCALAR(itint); 517 SERIALIZE_SCALAR(drir); 518} 519 520void 521TsunamiCChip::unserialize(Checkpoint *cp, const std::string §ion) 522{ 523 UNSERIALIZE_ARRAY(dim, Tsunami::Max_CPUs); 524 UNSERIALIZE_ARRAY(dir, Tsunami::Max_CPUs); 525 UNSERIALIZE_SCALAR(ipint); 526 UNSERIALIZE_SCALAR(itint); 527 UNSERIALIZE_SCALAR(drir); 528} 529 530TsunamiCChip * 531TsunamiCChipParams::create() 532{ 533 return new TsunamiCChip(this); 534} 535