tsunami_cchip.cc revision 831
111723Sar4jc@virginia.edu/* $Id$ */ 211723Sar4jc@virginia.edu 311723Sar4jc@virginia.edu/* @file 411723Sar4jc@virginia.edu * Emulation of the Tsunami CChip CSRs 511723Sar4jc@virginia.edu */ 611723Sar4jc@virginia.edu 711723Sar4jc@virginia.edu#include <deque> 811723Sar4jc@virginia.edu#include <string> 911723Sar4jc@virginia.edu#include <vector> 1011723Sar4jc@virginia.edu 1111723Sar4jc@virginia.edu#include "base/trace.hh" 1211723Sar4jc@virginia.edu#include "cpu/exec_context.hh" 1311723Sar4jc@virginia.edu#include "dev/console.hh" 1411723Sar4jc@virginia.edu#include "dev/tsunami_cchip.hh" 1511723Sar4jc@virginia.edu#include "dev/tsunamireg.h" 1611723Sar4jc@virginia.edu#include "dev/tsunami.hh" 1711723Sar4jc@virginia.edu#include "cpu/intr_control.hh" 1811723Sar4jc@virginia.edu#include "mem/functional_mem/memory_control.hh" 1911723Sar4jc@virginia.edu#include "sim/builder.hh" 2011723Sar4jc@virginia.edu#include "sim/system.hh" 2111723Sar4jc@virginia.edu 2211723Sar4jc@virginia.eduusing namespace std; 2311723Sar4jc@virginia.edu 2411723Sar4jc@virginia.eduTsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a, 2511723Sar4jc@virginia.edu MemoryController *mmu) 2611723Sar4jc@virginia.edu : FunctionalMemory(name), addr(a), tsunami(t) 2711723Sar4jc@virginia.edu{ 2811723Sar4jc@virginia.edu mmu->add_child(this, Range<Addr>(addr, addr + size)); 2911723Sar4jc@virginia.edu 3011723Sar4jc@virginia.edu for(int i=0; i < Tsunami::Max_CPUs; i++) { 3111723Sar4jc@virginia.edu dim[i] = 0; 3211723Sar4jc@virginia.edu dir[i] = 0; 3311723Sar4jc@virginia.edu dirInterrupting[i] = false; 3411723Sar4jc@virginia.edu ipiInterrupting[i] = false; 3511723Sar4jc@virginia.edu RTCInterrupting[i] = false; 3611723Sar4jc@virginia.edu } 3711723Sar4jc@virginia.edu 3811723Sar4jc@virginia.edu drir = 0; 3911723Sar4jc@virginia.edu misc = 0; 4011723Sar4jc@virginia.edu 4111723Sar4jc@virginia.edu //Put back pointer in tsunami 4211723Sar4jc@virginia.edu tsunami->cchip = this; 4311723Sar4jc@virginia.edu} 4411723Sar4jc@virginia.edu 4511723Sar4jc@virginia.eduFault 4611723Sar4jc@virginia.eduTsunamiCChip::read(MemReqPtr &req, uint8_t *data) 4711723Sar4jc@virginia.edu{ 4811723Sar4jc@virginia.edu DPRINTF(Tsunami, "read va=%#x size=%d\n", 4911723Sar4jc@virginia.edu req->vaddr, req->size); 5011723Sar4jc@virginia.edu 5111723Sar4jc@virginia.edu Addr daddr = (req->paddr - (addr & PA_IMPL_MASK)) >> 6; 5211723Sar4jc@virginia.edu ExecContext *xc = req->xc; 5311723Sar4jc@virginia.edu 5411723Sar4jc@virginia.edu switch (req->size) { 5511723Sar4jc@virginia.edu 5611723Sar4jc@virginia.edu case sizeof(uint64_t): 5711723Sar4jc@virginia.edu switch(daddr) { 5811723Sar4jc@virginia.edu case TSDEV_CC_CSR: 5911723Sar4jc@virginia.edu *(uint64_t*)data = 0x0; 6011723Sar4jc@virginia.edu return No_Fault; 6111723Sar4jc@virginia.edu case TSDEV_CC_MTR: 6211723Sar4jc@virginia.edu panic("TSDEV_CC_MTR not implemeted\n"); 6311723Sar4jc@virginia.edu return No_Fault; 6411723Sar4jc@virginia.edu case TSDEV_CC_MISC: 6511723Sar4jc@virginia.edu *(uint64_t*)data = misc | (xc->cpu_id & 0x3); 6611723Sar4jc@virginia.edu return No_Fault; 6711723Sar4jc@virginia.edu case TSDEV_CC_AAR0: 6811723Sar4jc@virginia.edu case TSDEV_CC_AAR1: 6911723Sar4jc@virginia.edu case TSDEV_CC_AAR2: 7011723Sar4jc@virginia.edu case TSDEV_CC_AAR3: 7111723Sar4jc@virginia.edu panic("TSDEV_CC_AARx not implemeted\n"); 7211723Sar4jc@virginia.edu return No_Fault; 7311723Sar4jc@virginia.edu case TSDEV_CC_DIM0: 7411723Sar4jc@virginia.edu *(uint64_t*)data = dim[0]; 7511723Sar4jc@virginia.edu return No_Fault; 7611723Sar4jc@virginia.edu case TSDEV_CC_DIM1: 7711723Sar4jc@virginia.edu *(uint64_t*)data = dim[1]; 7811723Sar4jc@virginia.edu return No_Fault; 7911723Sar4jc@virginia.edu case TSDEV_CC_DIM2: 8011723Sar4jc@virginia.edu *(uint64_t*)data = dim[2]; 8111723Sar4jc@virginia.edu return No_Fault; 8211723Sar4jc@virginia.edu case TSDEV_CC_DIM3: 8311723Sar4jc@virginia.edu *(uint64_t*)data = dim[3]; 8411723Sar4jc@virginia.edu return No_Fault; 8511723Sar4jc@virginia.edu case TSDEV_CC_DIR0: 8611723Sar4jc@virginia.edu *(uint64_t*)data = dir[0]; 8711723Sar4jc@virginia.edu return No_Fault; 8811723Sar4jc@virginia.edu case TSDEV_CC_DIR1: 8911723Sar4jc@virginia.edu *(uint64_t*)data = dir[1]; 9011723Sar4jc@virginia.edu return No_Fault; 9111723Sar4jc@virginia.edu case TSDEV_CC_DIR2: 9211723Sar4jc@virginia.edu *(uint64_t*)data = dir[2]; 9311723Sar4jc@virginia.edu return No_Fault; 9411723Sar4jc@virginia.edu case TSDEV_CC_DIR3: 9511723Sar4jc@virginia.edu *(uint64_t*)data = dir[3]; 9611723Sar4jc@virginia.edu return No_Fault; 9711723Sar4jc@virginia.edu case TSDEV_CC_DRIR: 9811723Sar4jc@virginia.edu *(uint64_t*)data = drir; 9911723Sar4jc@virginia.edu return No_Fault; 10011723Sar4jc@virginia.edu case TSDEV_CC_PRBEN: 10111723Sar4jc@virginia.edu panic("TSDEV_CC_PRBEN not implemented\n"); 10211723Sar4jc@virginia.edu return No_Fault; 10311723Sar4jc@virginia.edu case TSDEV_CC_IIC0: 10411723Sar4jc@virginia.edu case TSDEV_CC_IIC1: 10511723Sar4jc@virginia.edu case TSDEV_CC_IIC2: 10611723Sar4jc@virginia.edu case TSDEV_CC_IIC3: 10711723Sar4jc@virginia.edu panic("TSDEV_CC_IICx not implemented\n"); 10811723Sar4jc@virginia.edu return No_Fault; 10911723Sar4jc@virginia.edu case TSDEV_CC_MPR0: 11011723Sar4jc@virginia.edu case TSDEV_CC_MPR1: 11111723Sar4jc@virginia.edu case TSDEV_CC_MPR2: 11211723Sar4jc@virginia.edu case TSDEV_CC_MPR3: 11311723Sar4jc@virginia.edu panic("TSDEV_CC_MPRx not implemented\n"); 11411723Sar4jc@virginia.edu return No_Fault; 11511723Sar4jc@virginia.edu default: 11611723Sar4jc@virginia.edu panic("default in cchip read reached, accessing 0x%x\n"); 11711723Sar4jc@virginia.edu } // uint64_t 11811723Sar4jc@virginia.edu 11911723Sar4jc@virginia.edu break; 12011723Sar4jc@virginia.edu case sizeof(uint32_t): 12111723Sar4jc@virginia.edu case sizeof(uint16_t): 12211723Sar4jc@virginia.edu case sizeof(uint8_t): 12311723Sar4jc@virginia.edu default: 12411723Sar4jc@virginia.edu panic("invalid access size(?) for tsunami register!\n"); 12511723Sar4jc@virginia.edu } 12611723Sar4jc@virginia.edu DPRINTFN("Tsunami CChip ERROR: read daddr=%#x size=%d\n", daddr, req->size); 12711723Sar4jc@virginia.edu 12811723Sar4jc@virginia.edu return No_Fault; 12911723Sar4jc@virginia.edu} 13011723Sar4jc@virginia.edu 13111723Sar4jc@virginia.eduFault 13211723Sar4jc@virginia.eduTsunamiCChip::write(MemReqPtr &req, const uint8_t *data) 13311723Sar4jc@virginia.edu{ 13411723Sar4jc@virginia.edu DPRINTF(Tsunami, "write - va=%#x size=%d \n", 13511723Sar4jc@virginia.edu req->vaddr, req->size); 13611723Sar4jc@virginia.edu 13711723Sar4jc@virginia.edu Addr daddr = (req->paddr - (addr & PA_IMPL_MASK)) >> 6; 13811723Sar4jc@virginia.edu 13911723Sar4jc@virginia.edu bool supportedWrite = false; 14011723Sar4jc@virginia.edu uint64_t size = tsunami->intrctrl->cpu->system->execContexts.size(); 14111723Sar4jc@virginia.edu 14211723Sar4jc@virginia.edu switch (req->size) { 14311723Sar4jc@virginia.edu 14411723Sar4jc@virginia.edu case sizeof(uint64_t): 14511723Sar4jc@virginia.edu switch(daddr) { 14612749Sgiacomo.travaglini@arm.com case TSDEV_CC_CSR: 14711723Sar4jc@virginia.edu panic("TSDEV_CC_CSR write\n"); 14811723Sar4jc@virginia.edu return No_Fault; 14911723Sar4jc@virginia.edu case TSDEV_CC_MTR: 15011723Sar4jc@virginia.edu panic("TSDEV_CC_MTR write not implemented\n"); 15111723Sar4jc@virginia.edu return No_Fault; 15211723Sar4jc@virginia.edu case TSDEV_CC_MISC: 15311723Sar4jc@virginia.edu //If it is the 4-7th bit, clear the RTC interrupt 15411723Sar4jc@virginia.edu uint64_t itintr; 15511723Sar4jc@virginia.edu if ((itintr = (*(uint64_t*) data) & (0xf<<4))) { 15611723Sar4jc@virginia.edu //Clear the bits in ITINTR 15711723Sar4jc@virginia.edu misc &= ~(itintr); 15811723Sar4jc@virginia.edu for (int i=0; i < size; i++) { 15911723Sar4jc@virginia.edu if ((itintr & (1 << (i+4))) && RTCInterrupting[i]) { 16011723Sar4jc@virginia.edu tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ2, 0); 16111723Sar4jc@virginia.edu RTCInterrupting[i] = false; 16211723Sar4jc@virginia.edu DPRINTF(Tsunami, "clearing rtc interrupt to cpu=%d\n", i); 16311723Sar4jc@virginia.edu } 16411723Sar4jc@virginia.edu } 16511723Sar4jc@virginia.edu supportedWrite = true; 16611723Sar4jc@virginia.edu } 16711723Sar4jc@virginia.edu //If it is 12th-15th bit, IPI sent to Processor 1 16811723Sar4jc@virginia.edu uint64_t ipreq; 16911723Sar4jc@virginia.edu if ((ipreq = (*(uint64_t*) data) & (0xf << 12))) { 17011723Sar4jc@virginia.edu //Set the bits in IPINTR 17111723Sar4jc@virginia.edu misc |= (ipreq >> 4); 17211723Sar4jc@virginia.edu for (int i=0; i < size; i++) { 17311723Sar4jc@virginia.edu if ((ipreq & (1 << (i + 12)))) { 17411723Sar4jc@virginia.edu if (!ipiInterrupting[i]) 17511723Sar4jc@virginia.edu tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ3, 0); 17611723Sar4jc@virginia.edu ipiInterrupting[i]++; 17711723Sar4jc@virginia.edu DPRINTF(IPI, "send cpu=%d pending=%d from=%d\n", i, 17811723Sar4jc@virginia.edu ipiInterrupting[i], req->cpu_num); 17911723Sar4jc@virginia.edu } 18011723Sar4jc@virginia.edu } 18111723Sar4jc@virginia.edu supportedWrite = true; 18211723Sar4jc@virginia.edu } 18311723Sar4jc@virginia.edu //If it is bits 8-11, then clearing IPI's 18411723Sar4jc@virginia.edu uint64_t ipintr; 18511723Sar4jc@virginia.edu if ((ipintr = (*(uint64_t*) data) & (0xf << 8))) { 18611723Sar4jc@virginia.edu //Clear the bits in IPINTR 18711723Sar4jc@virginia.edu misc &= ~(ipintr); 18811723Sar4jc@virginia.edu for (int i=0; i < size; i++) { 18911723Sar4jc@virginia.edu if ((ipintr & (1 << (i + 8))) && ipiInterrupting[i]) { 19011723Sar4jc@virginia.edu if (!(--ipiInterrupting[i])) 19111723Sar4jc@virginia.edu tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ3, 0); 19211723Sar4jc@virginia.edu DPRINTF(IPI, "clearing cpu=%d pending=%d from=%d\n", i, 19311723Sar4jc@virginia.edu ipiInterrupting[i] + 1, req->cpu_num); 19411723Sar4jc@virginia.edu } 19511723Sar4jc@virginia.edu } 19611723Sar4jc@virginia.edu supportedWrite = true; 19711723Sar4jc@virginia.edu } 19811723Sar4jc@virginia.edu if(!supportedWrite) panic("TSDEV_CC_MISC write not implemented\n"); 19911723Sar4jc@virginia.edu return No_Fault; 20011723Sar4jc@virginia.edu case TSDEV_CC_AAR0: 20111723Sar4jc@virginia.edu case TSDEV_CC_AAR1: 20211723Sar4jc@virginia.edu case TSDEV_CC_AAR2: 20311723Sar4jc@virginia.edu case TSDEV_CC_AAR3: 20411723Sar4jc@virginia.edu panic("TSDEV_CC_AARx write not implemeted\n"); 20511723Sar4jc@virginia.edu return No_Fault; 20611723Sar4jc@virginia.edu case TSDEV_CC_DIM0: 20711723Sar4jc@virginia.edu case TSDEV_CC_DIM1: 20811723Sar4jc@virginia.edu case TSDEV_CC_DIM2: 20911723Sar4jc@virginia.edu case TSDEV_CC_DIM3: 21011723Sar4jc@virginia.edu int number; 21111723Sar4jc@virginia.edu if(daddr == TSDEV_CC_DIM0) 21211723Sar4jc@virginia.edu number = 0; 21311723Sar4jc@virginia.edu else if(daddr == TSDEV_CC_DIM1) 21411723Sar4jc@virginia.edu number = 1; 21511723Sar4jc@virginia.edu else if(daddr == TSDEV_CC_DIM2) 21611723Sar4jc@virginia.edu number = 2; 21711723Sar4jc@virginia.edu else 21811723Sar4jc@virginia.edu number = 3; 21911723Sar4jc@virginia.edu 22011723Sar4jc@virginia.edu uint64_t bitvector; 22111723Sar4jc@virginia.edu uint64_t olddim; 22211723Sar4jc@virginia.edu uint64_t olddir; 22311723Sar4jc@virginia.edu 22411723Sar4jc@virginia.edu olddim = dim[number]; 22511723Sar4jc@virginia.edu olddir = dir[number]; 22611723Sar4jc@virginia.edu dim[number] = *(uint64_t*)data; 22711723Sar4jc@virginia.edu dir[number] = dim[number] & drir; 22811723Sar4jc@virginia.edu for(int x = 0; x < 64; x++) 22911723Sar4jc@virginia.edu { 23011723Sar4jc@virginia.edu bitvector = (uint64_t)1 << x; 23111723Sar4jc@virginia.edu // Figure out which bits have changed 23211723Sar4jc@virginia.edu if ((dim[number] & bitvector) != (olddim & bitvector)) 23311723Sar4jc@virginia.edu { 23411723Sar4jc@virginia.edu // The bit is now set and it wasn't before (set) 23511723Sar4jc@virginia.edu if((dim[number] & bitvector) && (dir[number] & bitvector)) 23611723Sar4jc@virginia.edu { 23711723Sar4jc@virginia.edu tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x); 23811723Sar4jc@virginia.edu DPRINTF(Tsunami, "posting dir interrupt to cpu 0\n"); 23911723Sar4jc@virginia.edu } 24011723Sar4jc@virginia.edu else if ((olddir & bitvector) && 24111723Sar4jc@virginia.edu !(dir[number] & bitvector)) 24211723Sar4jc@virginia.edu { 24311723Sar4jc@virginia.edu // The bit was set and now its now clear and 24411723Sar4jc@virginia.edu // we were interrupting on that bit before 24511723Sar4jc@virginia.edu tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x); 24611723Sar4jc@virginia.edu DPRINTF(Tsunami, "dim write resulting in clear" 24711723Sar4jc@virginia.edu "dir interrupt to cpu 0\n"); 24811723Sar4jc@virginia.edu 24911723Sar4jc@virginia.edu } 25011723Sar4jc@virginia.edu 25111723Sar4jc@virginia.edu 25211723Sar4jc@virginia.edu } 25311723Sar4jc@virginia.edu } 25411723Sar4jc@virginia.edu return No_Fault; 25511723Sar4jc@virginia.edu case TSDEV_CC_DIR0: 25611723Sar4jc@virginia.edu case TSDEV_CC_DIR1: 25711723Sar4jc@virginia.edu case TSDEV_CC_DIR2: 25811723Sar4jc@virginia.edu case TSDEV_CC_DIR3: 25911723Sar4jc@virginia.edu panic("TSDEV_CC_DIR write not implemented\n"); 26011723Sar4jc@virginia.edu case TSDEV_CC_DRIR: 26111723Sar4jc@virginia.edu panic("TSDEV_CC_DRIR write not implemented\n"); 26211723Sar4jc@virginia.edu case TSDEV_CC_PRBEN: 26311723Sar4jc@virginia.edu panic("TSDEV_CC_PRBEN write not implemented\n"); 26411723Sar4jc@virginia.edu case TSDEV_CC_IIC0: 26511723Sar4jc@virginia.edu case TSDEV_CC_IIC1: 26611723Sar4jc@virginia.edu case TSDEV_CC_IIC2: 26711723Sar4jc@virginia.edu case TSDEV_CC_IIC3: 26811723Sar4jc@virginia.edu panic("TSDEV_CC_IICx write not implemented\n"); 26911723Sar4jc@virginia.edu case TSDEV_CC_MPR0: 27011723Sar4jc@virginia.edu case TSDEV_CC_MPR1: 27111723Sar4jc@virginia.edu case TSDEV_CC_MPR2: 27211723Sar4jc@virginia.edu case TSDEV_CC_MPR3: 27311723Sar4jc@virginia.edu panic("TSDEV_CC_MPRx write not implemented\n"); 27411723Sar4jc@virginia.edu default: 27511723Sar4jc@virginia.edu panic("default in cchip read reached, accessing 0x%x\n"); 27611723Sar4jc@virginia.edu } 27711723Sar4jc@virginia.edu 27811723Sar4jc@virginia.edu break; 27911723Sar4jc@virginia.edu case sizeof(uint32_t): 28011723Sar4jc@virginia.edu case sizeof(uint16_t): 28111723Sar4jc@virginia.edu case sizeof(uint8_t): 28211723Sar4jc@virginia.edu default: 28311723Sar4jc@virginia.edu panic("invalid access size(?) for tsunami register!\n"); 28411723Sar4jc@virginia.edu } 28511723Sar4jc@virginia.edu 28612749Sgiacomo.travaglini@arm.com DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size); 28711723Sar4jc@virginia.edu 28811723Sar4jc@virginia.edu return No_Fault; 28911723Sar4jc@virginia.edu} 29011723Sar4jc@virginia.edu 29111723Sar4jc@virginia.eduvoid 29211723Sar4jc@virginia.eduTsunamiCChip::postRTC() 29311723Sar4jc@virginia.edu{ 29411723Sar4jc@virginia.edu int size = tsunami->intrctrl->cpu->system->execContexts.size(); 29511723Sar4jc@virginia.edu 29611723Sar4jc@virginia.edu for (int i = 0; i < size; i++) { 29711723Sar4jc@virginia.edu if (!RTCInterrupting[i]) { 29811723Sar4jc@virginia.edu misc |= 16 << i; 29911723Sar4jc@virginia.edu RTCInterrupting[i] = true; 30011723Sar4jc@virginia.edu tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ2, 0); 30112749Sgiacomo.travaglini@arm.com DPRINTF(Tsunami, "Posting RTC interrupt to cpu=%d", i); 30211723Sar4jc@virginia.edu } 30311723Sar4jc@virginia.edu } 30411723Sar4jc@virginia.edu 30511723Sar4jc@virginia.edu} 30611962Sar4jc@virginia.edu 30711962Sar4jc@virginia.eduvoid 30811962Sar4jc@virginia.eduTsunamiCChip::postDRIR(uint32_t interrupt) 30911962Sar4jc@virginia.edu{ 31011962Sar4jc@virginia.edu uint64_t bitvector = (uint64_t)0x1 << interrupt; 31111962Sar4jc@virginia.edu drir |= bitvector; 31211962Sar4jc@virginia.edu uint64_t size = tsunami->intrctrl->cpu->system->execContexts.size(); 31311962Sar4jc@virginia.edu for(int i=0; i < size; i++) { 31411962Sar4jc@virginia.edu dir[i] = dim[i] & drir; 31511962Sar4jc@virginia.edu if (dim[i] & bitvector) { 31611962Sar4jc@virginia.edu tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ1, interrupt); 31711723Sar4jc@virginia.edu DPRINTF(Tsunami, "posting dir interrupt to cpu %d," 31811723Sar4jc@virginia.edu "interrupt %d\n",i, interrupt); 31911723Sar4jc@virginia.edu } 32011723Sar4jc@virginia.edu } 32111723Sar4jc@virginia.edu} 32211723Sar4jc@virginia.edu 32311723Sar4jc@virginia.eduvoid 32411723Sar4jc@virginia.eduTsunamiCChip::clearDRIR(uint32_t interrupt) 32511723Sar4jc@virginia.edu{ 32611723Sar4jc@virginia.edu uint64_t bitvector = (uint64_t)0x1 << interrupt; 32712749Sgiacomo.travaglini@arm.com uint64_t size = tsunami->intrctrl->cpu->system->execContexts.size(); 32811723Sar4jc@virginia.edu if (drir & bitvector) 32911723Sar4jc@virginia.edu { 33011723Sar4jc@virginia.edu drir &= ~bitvector; 33111723Sar4jc@virginia.edu for(int i=0; i < size; i++) { 33211723Sar4jc@virginia.edu if (dir[i] & bitvector) { 33311723Sar4jc@virginia.edu tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ1, interrupt); 33411723Sar4jc@virginia.edu DPRINTF(Tsunami, "clearing dir interrupt to cpu %d," 33511723Sar4jc@virginia.edu "interrupt %d\n",i, interrupt); 33612749Sgiacomo.travaglini@arm.com 33711723Sar4jc@virginia.edu } 33811723Sar4jc@virginia.edu dir[i] = dim[i] & drir; 33911723Sar4jc@virginia.edu } 34011723Sar4jc@virginia.edu } 34111723Sar4jc@virginia.edu else 34211723Sar4jc@virginia.edu DPRINTF(Tsunami, "Spurrious clear? interrupt %d\n", interrupt); 34311723Sar4jc@virginia.edu} 34412749Sgiacomo.travaglini@arm.com 34512749Sgiacomo.travaglini@arm.comvoid 34611723Sar4jc@virginia.eduTsunamiCChip::serialize(std::ostream &os) 34711723Sar4jc@virginia.edu{ 34811723Sar4jc@virginia.edu SERIALIZE_ARRAY(dim, Tsunami::Max_CPUs); 34911723Sar4jc@virginia.edu SERIALIZE_ARRAY(dir, Tsunami::Max_CPUs); 35011723Sar4jc@virginia.edu SERIALIZE_ARRAY(dirInterrupting, Tsunami::Max_CPUs); 35111723Sar4jc@virginia.edu SERIALIZE_ARRAY(ipiInterrupting, Tsunami::Max_CPUs); 35211723Sar4jc@virginia.edu SERIALIZE_SCALAR(drir); 35311723Sar4jc@virginia.edu SERIALIZE_SCALAR(misc); 35411723Sar4jc@virginia.edu SERIALIZE_ARRAY(RTCInterrupting, Tsunami::Max_CPUs); 35511723Sar4jc@virginia.edu} 35611723Sar4jc@virginia.edu 35711723Sar4jc@virginia.eduvoid 35811723Sar4jc@virginia.eduTsunamiCChip::unserialize(Checkpoint *cp, const std::string §ion) 35911723Sar4jc@virginia.edu{ 36011723Sar4jc@virginia.edu UNSERIALIZE_ARRAY(dim, Tsunami::Max_CPUs); 36111723Sar4jc@virginia.edu UNSERIALIZE_ARRAY(dir, Tsunami::Max_CPUs); 36211723Sar4jc@virginia.edu UNSERIALIZE_ARRAY(dirInterrupting, Tsunami::Max_CPUs); 36311723Sar4jc@virginia.edu UNSERIALIZE_ARRAY(ipiInterrupting, Tsunami::Max_CPUs); 36411723Sar4jc@virginia.edu UNSERIALIZE_SCALAR(drir); 36511723Sar4jc@virginia.edu UNSERIALIZE_SCALAR(misc); 36611723Sar4jc@virginia.edu UNSERIALIZE_ARRAY(RTCInterrupting, Tsunami::Max_CPUs); 367} 368 369BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip) 370 371 SimObjectParam<Tsunami *> tsunami; 372 SimObjectParam<MemoryController *> mmu; 373 Param<Addr> addr; 374 375END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip) 376 377BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip) 378 379 INIT_PARAM(tsunami, "Tsunami"), 380 INIT_PARAM(mmu, "Memory Controller"), 381 INIT_PARAM(addr, "Device Address") 382 383END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip) 384 385CREATE_SIM_OBJECT(TsunamiCChip) 386{ 387 return new TsunamiCChip(getInstanceName(), tsunami, addr, mmu); 388} 389 390REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip) 391