tsunami_cchip.cc revision 11793:ef606668d247
12SN/A/* 21762SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Ali Saidi 292SN/A * Ron Dreslinski 302SN/A */ 311722SN/A 322SN/A/** @file 332SN/A * Emulation of the Tsunami CChip CSRs 342SN/A */ 3511264Sandreas.sandberg@arm.com 3611264Sandreas.sandberg@arm.com#include "dev/alpha/tsunami_cchip.hh" 372SN/A 382SN/A#include <deque> 3911168SN/A#include <string> 402SN/A#include <vector> 418229SN/A 428229SN/A#include "arch/alpha/ev5.hh" 438229SN/A#include "base/trace.hh" 4456SN/A#include "config/the_isa.hh" 452SN/A#include "cpu/intr_control.hh" 462SN/A#include "cpu/thread_context.hh" 472SN/A#include "debug/IPI.hh" 481722SN/A#include "debug/Tsunami.hh" 492SN/A#include "dev/alpha/tsunami.hh" 502SN/A#include "dev/alpha/tsunamireg.h" 512SN/A#include "mem/packet.hh" 522SN/A#include "mem/packet_access.hh" 532SN/A#include "mem/port.hh" 542SN/A#include "params/TsunamiCChip.hh" 552SN/A#include "sim/system.hh" 562SN/A 575034SN/A//Should this be AlphaISA? 585034SN/Ausing namespace TheISA; 592SN/A 602SN/ATsunamiCChip::TsunamiCChip(const Params *p) 619533SN/A : BasicPioDevice(p, 0x10000000), tsunami(p->tsunami) 622SN/A{ 639533SN/A drir = 0; 649533SN/A ipint = 0; 659533SN/A itint = 0; 669533SN/A 672SN/A for (int x = 0; x < Tsunami::Max_CPUs; x++) 682SN/A { 691722SN/A dim[x] = 0; 702SN/A dir[x] = 0; 712SN/A } 722SN/A 732SN/A //Put back pointer in tsunami 742SN/A tsunami->cchip = this; 752SN/A} 762SN/A 772SN/ATick 789533SN/ATsunamiCChip::read(PacketPtr pkt) 792SN/A{ 802SN/A DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize()); 815034SN/A 825034SN/A assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 832SN/A 842SN/A Addr regnum = (pkt->getAddr() - pioAddr) >> 6; 8511361Sandreas@sandberg.pp.se Addr daddr = (pkt->getAddr() - pioAddr); 8611361Sandreas@sandberg.pp.se 872SN/A switch (pkt->getSize()) { 882SN/A 892SN/A case sizeof(uint64_t): 9011442Sandreas.hansson@arm.com pkt->set<uint64_t>(0); 912SN/A 9211613Sandreas.sandberg@arm.com if (daddr & TSDEV_CC_BDIMS) 9311613Sandreas.sandberg@arm.com { 942SN/A pkt->set(dim[(daddr >> 4) & 0x3F]); 952SN/A break; 961722SN/A } 972SN/A 982SN/A if (daddr & TSDEV_CC_BDIRS) 992SN/A { 1002SN/A pkt->set(dir[(daddr >> 4) & 0x3F]); 1012SN/A break; 1022SN/A } 1032SN/A 1042SN/A switch(regnum) { 1052SN/A case TSDEV_CC_CSR: 1062SN/A pkt->set(0x0); 1072SN/A break; 1082SN/A case TSDEV_CC_MTR: 1096227SN/A panic("TSDEV_CC_MTR not implemeted\n"); 1106227SN/A break; 1112SN/A case TSDEV_CC_MISC: 1122SN/A pkt->set(((ipint << 8) & 0xF) | ((itint << 4) & 0xF) | 1132SN/A (pkt->req->contextId() & 0x3)); 1142SN/A // currently, FS cannot handle MT so contextId and 1152SN/A // cpuId are effectively the same, don't know if it will 11611168SN/A // matter if FS becomes MT enabled. I suspect no because 1172SN/A // we are currently able to boot up to 64 procs anyway 1182SN/A // which would render the CPUID of this register useless 1192SN/A // anyway 1202SN/A break; 1212SN/A case TSDEV_CC_AAR0: 1222SN/A case TSDEV_CC_AAR1: 1232SN/A case TSDEV_CC_AAR2: 1245034SN/A case TSDEV_CC_AAR3: 1255034SN/A pkt->set(0); 1262SN/A break; 1272SN/A case TSDEV_CC_DIM0: 12811361Sandreas@sandberg.pp.se pkt->set(dim[0]); 12911361Sandreas@sandberg.pp.se break; 1308737SN/A case TSDEV_CC_DIM1: 131259SN/A pkt->set(dim[1]); 13210905SN/A break; 13310905SN/A case TSDEV_CC_DIM2: 1342SN/A pkt->set(dim[2]); 13510905SN/A break; 13611168SN/A case TSDEV_CC_DIM3: 13711168SN/A pkt->set(dim[3]); 1382SN/A break; 13911169SN/A case TSDEV_CC_DIR0: 1402SN/A pkt->set(dir[0]); 14111169SN/A break; 14211169SN/A case TSDEV_CC_DIR1: 1432SN/A pkt->set(dir[1]); 1442SN/A break; 1459554SN/A case TSDEV_CC_DIR2: 1469554SN/A pkt->set(dir[2]); 1479554SN/A break; 1489554SN/A case TSDEV_CC_DIR3: 1499554SN/A pkt->set(dir[3]); 1509554SN/A break; 1519554SN/A case TSDEV_CC_DRIR: 1529554SN/A pkt->set(drir); 1539554SN/A break; 1549554SN/A case TSDEV_CC_PRBEN: 1559554SN/A panic("TSDEV_CC_PRBEN not implemented\n"); 1569554SN/A break; 1579554SN/A case TSDEV_CC_IIC0: 1589554SN/A case TSDEV_CC_IIC1: 1599554SN/A case TSDEV_CC_IIC2: 1609554SN/A case TSDEV_CC_IIC3: 16111264Sandreas.sandberg@arm.com panic("TSDEV_CC_IICx not implemented\n"); 162 break; 163 case TSDEV_CC_MPR0: 164 case TSDEV_CC_MPR1: 165 case TSDEV_CC_MPR2: 166 case TSDEV_CC_MPR3: 167 panic("TSDEV_CC_MPRx not implemented\n"); 168 break; 169 case TSDEV_CC_IPIR: 170 pkt->set(ipint); 171 break; 172 case TSDEV_CC_ITIR: 173 pkt->set(itint); 174 break; 175 default: 176 panic("default in cchip read reached, accessing 0x%x\n"); 177 } // uint64_t 178 179 break; 180 case sizeof(uint32_t): 181 case sizeof(uint16_t): 182 case sizeof(uint8_t): 183 default: 184 panic("invalid access size(?) for tsunami register!\n"); 185 } 186 DPRINTF(Tsunami, "Tsunami CChip: read regnum=%#x size=%d data=%lld\n", 187 regnum, pkt->getSize(), pkt->get<uint64_t>()); 188 189 pkt->makeAtomicResponse(); 190 return pioDelay; 191} 192 193Tick 194TsunamiCChip::write(PacketPtr pkt) 195{ 196 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 197 Addr daddr = pkt->getAddr() - pioAddr; 198 Addr regnum = (pkt->getAddr() - pioAddr) >> 6 ; 199 200 201 assert(pkt->getSize() == sizeof(uint64_t)); 202 203 DPRINTF(Tsunami, "write - addr=%#x value=%#x\n", pkt->getAddr(), pkt->get<uint64_t>()); 204 205 bool supportedWrite = false; 206 207 208 if (daddr & TSDEV_CC_BDIMS) 209 { 210 int number = (daddr >> 4) & 0x3F; 211 212 uint64_t bitvector; 213 uint64_t olddim; 214 uint64_t olddir; 215 216 olddim = dim[number]; 217 olddir = dir[number]; 218 dim[number] = pkt->get<uint64_t>(); 219 dir[number] = dim[number] & drir; 220 for (int x = 0; x < Tsunami::Max_CPUs; x++) 221 { 222 bitvector = ULL(1) << x; 223 // Figure out which bits have changed 224 if ((dim[number] & bitvector) != (olddim & bitvector)) 225 { 226 // The bit is now set and it wasn't before (set) 227 if ((dim[number] & bitvector) && (dir[number] & bitvector)) 228 { 229 tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x); 230 DPRINTF(Tsunami, "dim write resulting in posting dir" 231 " interrupt to cpu %d\n", number); 232 } 233 else if ((olddir & bitvector) && 234 !(dir[number] & bitvector)) 235 { 236 // The bit was set and now its now clear and 237 // we were interrupting on that bit before 238 tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x); 239 DPRINTF(Tsunami, "dim write resulting in clear" 240 " dir interrupt to cpu %d\n", number); 241 242 } 243 244 245 } 246 } 247 } else { 248 switch(regnum) { 249 case TSDEV_CC_CSR: 250 panic("TSDEV_CC_CSR write\n"); 251 case TSDEV_CC_MTR: 252 panic("TSDEV_CC_MTR write not implemented\n"); 253 case TSDEV_CC_MISC: 254 uint64_t ipreq; 255 ipreq = (pkt->get<uint64_t>() >> 12) & 0xF; 256 //If it is bit 12-15, this is an IPI post 257 if (ipreq) { 258 reqIPI(ipreq); 259 supportedWrite = true; 260 } 261 262 //If it is bit 8-11, this is an IPI clear 263 uint64_t ipintr; 264 ipintr = (pkt->get<uint64_t>() >> 8) & 0xF; 265 if (ipintr) { 266 clearIPI(ipintr); 267 supportedWrite = true; 268 } 269 270 //If it is the 4-7th bit, clear the RTC interrupt 271 uint64_t itintr; 272 itintr = (pkt->get<uint64_t>() >> 4) & 0xF; 273 if (itintr) { 274 clearITI(itintr); 275 supportedWrite = true; 276 } 277 278 // ignore NXMs 279 if (pkt->get<uint64_t>() & 0x10000000) 280 supportedWrite = true; 281 282 if (!supportedWrite) 283 panic("TSDEV_CC_MISC write not implemented\n"); 284 285 break; 286 case TSDEV_CC_AAR0: 287 case TSDEV_CC_AAR1: 288 case TSDEV_CC_AAR2: 289 case TSDEV_CC_AAR3: 290 panic("TSDEV_CC_AARx write not implemeted\n"); 291 case TSDEV_CC_DIM0: 292 case TSDEV_CC_DIM1: 293 case TSDEV_CC_DIM2: 294 case TSDEV_CC_DIM3: 295 int number; 296 if (regnum == TSDEV_CC_DIM0) 297 number = 0; 298 else if (regnum == TSDEV_CC_DIM1) 299 number = 1; 300 else if (regnum == TSDEV_CC_DIM2) 301 number = 2; 302 else 303 number = 3; 304 305 uint64_t bitvector; 306 uint64_t olddim; 307 uint64_t olddir; 308 309 olddim = dim[number]; 310 olddir = dir[number]; 311 dim[number] = pkt->get<uint64_t>(); 312 dir[number] = dim[number] & drir; 313 for (int x = 0; x < 64; x++) 314 { 315 bitvector = ULL(1) << x; 316 // Figure out which bits have changed 317 if ((dim[number] & bitvector) != (olddim & bitvector)) 318 { 319 // The bit is now set and it wasn't before (set) 320 if ((dim[number] & bitvector) && (dir[number] & bitvector)) 321 { 322 tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x); 323 DPRINTF(Tsunami, "posting dir interrupt to cpu 0\n"); 324 } 325 else if ((olddir & bitvector) && 326 !(dir[number] & bitvector)) 327 { 328 // The bit was set and now its now clear and 329 // we were interrupting on that bit before 330 tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x); 331 DPRINTF(Tsunami, "dim write resulting in clear" 332 " dir interrupt to cpu %d\n", 333 x); 334 335 } 336 337 338 } 339 } 340 break; 341 case TSDEV_CC_DIR0: 342 case TSDEV_CC_DIR1: 343 case TSDEV_CC_DIR2: 344 case TSDEV_CC_DIR3: 345 panic("TSDEV_CC_DIR write not implemented\n"); 346 case TSDEV_CC_DRIR: 347 panic("TSDEV_CC_DRIR write not implemented\n"); 348 case TSDEV_CC_PRBEN: 349 panic("TSDEV_CC_PRBEN write not implemented\n"); 350 case TSDEV_CC_IIC0: 351 case TSDEV_CC_IIC1: 352 case TSDEV_CC_IIC2: 353 case TSDEV_CC_IIC3: 354 panic("TSDEV_CC_IICx write not implemented\n"); 355 case TSDEV_CC_MPR0: 356 case TSDEV_CC_MPR1: 357 case TSDEV_CC_MPR2: 358 case TSDEV_CC_MPR3: 359 panic("TSDEV_CC_MPRx write not implemented\n"); 360 case TSDEV_CC_IPIR: 361 clearIPI(pkt->get<uint64_t>()); 362 break; 363 case TSDEV_CC_ITIR: 364 clearITI(pkt->get<uint64_t>()); 365 break; 366 case TSDEV_CC_IPIQ: 367 reqIPI(pkt->get<uint64_t>()); 368 break; 369 default: 370 panic("default in cchip read reached, accessing 0x%x\n"); 371 } // swtich(regnum) 372 } // not BIG_TSUNAMI write 373 pkt->makeAtomicResponse(); 374 return pioDelay; 375} 376 377void 378TsunamiCChip::clearIPI(uint64_t ipintr) 379{ 380 int numcpus = sys->threadContexts.size(); 381 assert(numcpus <= Tsunami::Max_CPUs); 382 383 if (ipintr) { 384 for (int cpunum=0; cpunum < numcpus; cpunum++) { 385 // Check each cpu bit 386 uint64_t cpumask = ULL(1) << cpunum; 387 if (ipintr & cpumask) { 388 // Check if there is a pending ipi 389 if (ipint & cpumask) { 390 ipint &= ~cpumask; 391 tsunami->intrctrl->clear(cpunum, TheISA::INTLEVEL_IRQ3, 0); 392 DPRINTF(IPI, "clear IPI IPI cpu=%d\n", cpunum); 393 } 394 else 395 warn("clear IPI for CPU=%d, but NO IPI\n", cpunum); 396 } 397 } 398 } 399 else 400 panic("Big IPI Clear, but not processors indicated\n"); 401} 402 403void 404TsunamiCChip::clearITI(uint64_t itintr) 405{ 406 int numcpus = sys->threadContexts.size(); 407 assert(numcpus <= Tsunami::Max_CPUs); 408 409 if (itintr) { 410 for (int i=0; i < numcpus; i++) { 411 uint64_t cpumask = ULL(1) << i; 412 if (itintr & cpumask & itint) { 413 tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ2, 0); 414 itint &= ~cpumask; 415 DPRINTF(Tsunami, "clearing rtc interrupt to cpu=%d\n", i); 416 } 417 } 418 } 419 else 420 panic("Big ITI Clear, but not processors indicated\n"); 421} 422 423void 424TsunamiCChip::reqIPI(uint64_t ipreq) 425{ 426 int numcpus = sys->threadContexts.size(); 427 assert(numcpus <= Tsunami::Max_CPUs); 428 429 if (ipreq) { 430 for (int cpunum=0; cpunum < numcpus; cpunum++) { 431 // Check each cpu bit 432 uint64_t cpumask = ULL(1) << cpunum; 433 if (ipreq & cpumask) { 434 // Check if there is already an ipi (bits 8:11) 435 if (!(ipint & cpumask)) { 436 ipint |= cpumask; 437 tsunami->intrctrl->post(cpunum, TheISA::INTLEVEL_IRQ3, 0); 438 DPRINTF(IPI, "send IPI cpu=%d\n", cpunum); 439 } 440 else 441 warn("post IPI for CPU=%d, but IPI already\n", cpunum); 442 } 443 } 444 } 445 else 446 panic("Big IPI Request, but not processors indicated\n"); 447} 448 449 450void 451TsunamiCChip::postRTC() 452{ 453 int size = sys->threadContexts.size(); 454 assert(size <= Tsunami::Max_CPUs); 455 456 for (int i = 0; i < size; i++) { 457 uint64_t cpumask = ULL(1) << i; 458 if (!(cpumask & itint)) { 459 itint |= cpumask; 460 tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ2, 0); 461 DPRINTF(Tsunami, "Posting RTC interrupt to cpu=%d\n", i); 462 } 463 } 464 465} 466 467void 468TsunamiCChip::postDRIR(uint32_t interrupt) 469{ 470 uint64_t bitvector = ULL(1) << interrupt; 471 uint64_t size = sys->threadContexts.size(); 472 assert(size <= Tsunami::Max_CPUs); 473 drir |= bitvector; 474 475 for (int i=0; i < size; i++) { 476 dir[i] = dim[i] & drir; 477 if (dim[i] & bitvector) { 478 tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ1, interrupt); 479 DPRINTF(Tsunami, "posting dir interrupt to cpu %d," 480 "interrupt %d\n",i, interrupt); 481 } 482 } 483} 484 485void 486TsunamiCChip::clearDRIR(uint32_t interrupt) 487{ 488 uint64_t bitvector = ULL(1) << interrupt; 489 uint64_t size = sys->threadContexts.size(); 490 assert(size <= Tsunami::Max_CPUs); 491 492 if (drir & bitvector) 493 { 494 drir &= ~bitvector; 495 for (int i=0; i < size; i++) { 496 if (dir[i] & bitvector) { 497 tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ1, interrupt); 498 DPRINTF(Tsunami, "clearing dir interrupt to cpu %d," 499 "interrupt %d\n",i, interrupt); 500 501 } 502 dir[i] = dim[i] & drir; 503 } 504 } 505 else 506 DPRINTF(Tsunami, "Spurrious clear? interrupt %d\n", interrupt); 507} 508 509 510void 511TsunamiCChip::serialize(CheckpointOut &cp) const 512{ 513 SERIALIZE_ARRAY(dim, Tsunami::Max_CPUs); 514 SERIALIZE_ARRAY(dir, Tsunami::Max_CPUs); 515 SERIALIZE_SCALAR(ipint); 516 SERIALIZE_SCALAR(itint); 517 SERIALIZE_SCALAR(drir); 518} 519 520void 521TsunamiCChip::unserialize(CheckpointIn &cp) 522{ 523 UNSERIALIZE_ARRAY(dim, Tsunami::Max_CPUs); 524 UNSERIALIZE_ARRAY(dir, Tsunami::Max_CPUs); 525 UNSERIALIZE_SCALAR(ipint); 526 UNSERIALIZE_SCALAR(itint); 527 UNSERIALIZE_SCALAR(drir); 528} 529 530TsunamiCChip * 531TsunamiCChipParams::create() 532{ 533 return new TsunamiCChip(this); 534} 535