tsunami_cchip.cc revision 8232
1892SN/A/* 21762SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 3892SN/A * All rights reserved. 4892SN/A * 5892SN/A * Redistribution and use in source and binary forms, with or without 6892SN/A * modification, are permitted provided that the following conditions are 7892SN/A * met: redistributions of source code must retain the above copyright 8892SN/A * notice, this list of conditions and the following disclaimer; 9892SN/A * redistributions in binary form must reproduce the above copyright 10892SN/A * notice, this list of conditions and the following disclaimer in the 11892SN/A * documentation and/or other materials provided with the distribution; 12892SN/A * neither the name of the copyright holders nor the names of its 13892SN/A * contributors may be used to endorse or promote products derived from 14892SN/A * this software without specific prior written permission. 15892SN/A * 16892SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17892SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18892SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19892SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20892SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21892SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22892SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23892SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24892SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25892SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26892SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Ali Saidi 292665SN/A * Ron Dreslinski 30892SN/A */ 31767SN/A 321730SN/A/** @file 33798SN/A * Emulation of the Tsunami CChip CSRs 34767SN/A */ 35767SN/A 36767SN/A#include <deque> 37767SN/A#include <string> 38767SN/A#include <vector> 39767SN/A 402432SN/A#include "arch/alpha/ev5.hh" 41767SN/A#include "base/trace.hh" 426658Snate@binkert.org#include "config/the_isa.hh" 433348SN/A#include "cpu/intr_control.hh" 443348SN/A#include "cpu/thread_context.hh" 458232Snate@binkert.org#include "debug/IPI.hh" 468232Snate@binkert.org#include "debug/Tsunami.hh" 473540Sgblack@eecs.umich.edu#include "dev/alpha/tsunami.hh" 483540Sgblack@eecs.umich.edu#include "dev/alpha/tsunami_cchip.hh" 493540Sgblack@eecs.umich.edu#include "dev/alpha/tsunamireg.h" 503348SN/A#include "mem/packet.hh" 513348SN/A#include "mem/packet_access.hh" 522523SN/A#include "mem/port.hh" 534762Snate@binkert.org#include "params/TsunamiCChip.hh" 54767SN/A#include "sim/system.hh" 55767SN/A 56767SN/Ausing namespace std; 572107SN/A//Should this be AlphaISA? 582107SN/Ausing namespace TheISA; 59767SN/A 604762Snate@binkert.orgTsunamiCChip::TsunamiCChip(const Params *p) 612523SN/A : BasicPioDevice(p), tsunami(p->tsunami) 62767SN/A{ 633846Shsul@eecs.umich.edu pioSize = 0x10000000; 64909SN/A 65767SN/A drir = 0; 661290SN/A ipint = 0; 671290SN/A itint = 0; 681290SN/A 691290SN/A for (int x = 0; x < Tsunami::Max_CPUs; x++) 701290SN/A { 711290SN/A dim[x] = 0; 721290SN/A dir[x] = 0; 731290SN/A } 74775SN/A 75775SN/A //Put back pointer in tsunami 76775SN/A tsunami->cchip = this; 77767SN/A} 78767SN/A 792523SN/ATick 803349SN/ATsunamiCChip::read(PacketPtr pkt) 81767SN/A{ 822641SN/A DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize()); 83767SN/A 842641SN/A assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 851290SN/A 862641SN/A Addr regnum = (pkt->getAddr() - pioAddr) >> 6; 872641SN/A Addr daddr = (pkt->getAddr() - pioAddr); 88767SN/A 892630SN/A pkt->allocate(); 902641SN/A switch (pkt->getSize()) { 91767SN/A 92767SN/A case sizeof(uint64_t): 933875Sbinkertn@umich.edu pkt->set<uint64_t>(0); 943875Sbinkertn@umich.edu 951290SN/A if (daddr & TSDEV_CC_BDIMS) 961290SN/A { 972630SN/A pkt->set(dim[(daddr >> 4) & 0x3F]); 982523SN/A break; 991290SN/A } 1001290SN/A 1011290SN/A if (daddr & TSDEV_CC_BDIRS) 1021290SN/A { 1032630SN/A pkt->set(dir[(daddr >> 4) & 0x3F]); 1042523SN/A break; 1051290SN/A } 1061290SN/A 1071290SN/A switch(regnum) { 108767SN/A case TSDEV_CC_CSR: 1092630SN/A pkt->set(0x0); 1102523SN/A break; 111767SN/A case TSDEV_CC_MTR: 112767SN/A panic("TSDEV_CC_MTR not implemeted\n"); 1132523SN/A break; 114767SN/A case TSDEV_CC_MISC: 1155570Snate@binkert.org pkt->set(((ipint << 8) & 0xF) | ((itint << 4) & 0xF) | 1165714Shsul@eecs.umich.edu (pkt->req->contextId() & 0x3)); 1175714Shsul@eecs.umich.edu // currently, FS cannot handle MT so contextId and 1185714Shsul@eecs.umich.edu // cpuId are effectively the same, don't know if it will 1195714Shsul@eecs.umich.edu // matter if FS becomes MT enabled. I suspect no because 1205714Shsul@eecs.umich.edu // we are currently able to boot up to 64 procs anyway 1215714Shsul@eecs.umich.edu // which would render the CPUID of this register useless 1225714Shsul@eecs.umich.edu // anyway 1232523SN/A break; 124767SN/A case TSDEV_CC_AAR0: 125767SN/A case TSDEV_CC_AAR1: 126767SN/A case TSDEV_CC_AAR2: 127767SN/A case TSDEV_CC_AAR3: 1282630SN/A pkt->set(0); 1292523SN/A break; 130767SN/A case TSDEV_CC_DIM0: 1312630SN/A pkt->set(dim[0]); 1322523SN/A break; 133767SN/A case TSDEV_CC_DIM1: 1342630SN/A pkt->set(dim[1]); 1352523SN/A break; 136767SN/A case TSDEV_CC_DIM2: 1372630SN/A pkt->set(dim[2]); 1382523SN/A break; 139767SN/A case TSDEV_CC_DIM3: 1402630SN/A pkt->set(dim[3]); 1412523SN/A break; 142767SN/A case TSDEV_CC_DIR0: 1432630SN/A pkt->set(dir[0]); 1442523SN/A break; 145767SN/A case TSDEV_CC_DIR1: 1462630SN/A pkt->set(dir[1]); 1472523SN/A break; 148767SN/A case TSDEV_CC_DIR2: 1492630SN/A pkt->set(dir[2]); 1502523SN/A break; 151767SN/A case TSDEV_CC_DIR3: 1522630SN/A pkt->set(dir[3]); 1532523SN/A break; 154767SN/A case TSDEV_CC_DRIR: 1552630SN/A pkt->set(drir); 1562523SN/A break; 157767SN/A case TSDEV_CC_PRBEN: 158767SN/A panic("TSDEV_CC_PRBEN not implemented\n"); 1592523SN/A break; 160767SN/A case TSDEV_CC_IIC0: 161767SN/A case TSDEV_CC_IIC1: 162767SN/A case TSDEV_CC_IIC2: 163767SN/A case TSDEV_CC_IIC3: 164767SN/A panic("TSDEV_CC_IICx not implemented\n"); 1652523SN/A break; 166767SN/A case TSDEV_CC_MPR0: 167767SN/A case TSDEV_CC_MPR1: 168767SN/A case TSDEV_CC_MPR2: 169767SN/A case TSDEV_CC_MPR3: 170767SN/A panic("TSDEV_CC_MPRx not implemented\n"); 1712523SN/A break; 1721290SN/A case TSDEV_CC_IPIR: 1732630SN/A pkt->set(ipint); 1742523SN/A break; 1751290SN/A case TSDEV_CC_ITIR: 1762630SN/A pkt->set(itint); 1772523SN/A break; 178768SN/A default: 179768SN/A panic("default in cchip read reached, accessing 0x%x\n"); 180767SN/A } // uint64_t 181767SN/A 182767SN/A break; 183767SN/A case sizeof(uint32_t): 184767SN/A case sizeof(uint16_t): 185767SN/A case sizeof(uint8_t): 186767SN/A default: 187768SN/A panic("invalid access size(?) for tsunami register!\n"); 188767SN/A } 1892549SN/A DPRINTF(Tsunami, "Tsunami CChip: read regnum=%#x size=%d data=%lld\n", 1902641SN/A regnum, pkt->getSize(), pkt->get<uint64_t>()); 191767SN/A 1924870Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 1932523SN/A return pioDelay; 194767SN/A} 195767SN/A 1962523SN/ATick 1973349SN/ATsunamiCChip::write(PacketPtr pkt) 198767SN/A{ 1992641SN/A assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 2002641SN/A Addr daddr = pkt->getAddr() - pioAddr; 2012641SN/A Addr regnum = (pkt->getAddr() - pioAddr) >> 6 ; 2022539SN/A 2032523SN/A 2042641SN/A assert(pkt->getSize() == sizeof(uint64_t)); 2052523SN/A 2062641SN/A DPRINTF(Tsunami, "write - addr=%#x value=%#x\n", pkt->getAddr(), pkt->get<uint64_t>()); 207767SN/A 208830SN/A bool supportedWrite = false; 209830SN/A 210767SN/A 2112539SN/A if (daddr & TSDEV_CC_BDIMS) 2122539SN/A { 2132539SN/A int number = (daddr >> 4) & 0x3F; 2141290SN/A 2152539SN/A uint64_t bitvector; 2162539SN/A uint64_t olddim; 2172539SN/A uint64_t olddir; 2181290SN/A 2192539SN/A olddim = dim[number]; 2202539SN/A olddir = dir[number]; 2212630SN/A dim[number] = pkt->get<uint64_t>(); 2222539SN/A dir[number] = dim[number] & drir; 2232539SN/A for(int x = 0; x < Tsunami::Max_CPUs; x++) 2242539SN/A { 2252539SN/A bitvector = ULL(1) << x; 2262539SN/A // Figure out which bits have changed 2272539SN/A if ((dim[number] & bitvector) != (olddim & bitvector)) 2282539SN/A { 2292539SN/A // The bit is now set and it wasn't before (set) 2302539SN/A if((dim[number] & bitvector) && (dir[number] & bitvector)) 2312539SN/A { 2322539SN/A tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x); 2332539SN/A DPRINTF(Tsunami, "dim write resulting in posting dir" 2342539SN/A " interrupt to cpu %d\n", number); 2352539SN/A } 2362539SN/A else if ((olddir & bitvector) && 2372539SN/A !(dir[number] & bitvector)) 2382539SN/A { 2392539SN/A // The bit was set and now its now clear and 2402539SN/A // we were interrupting on that bit before 2412539SN/A tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x); 2422539SN/A DPRINTF(Tsunami, "dim write resulting in clear" 2432539SN/A " dir interrupt to cpu %d\n", number); 2441290SN/A 2451074SN/A } 2461074SN/A 2472539SN/A 2482539SN/A } 2492539SN/A } 2502539SN/A } else { 2512539SN/A switch(regnum) { 2522539SN/A case TSDEV_CC_CSR: 2532539SN/A panic("TSDEV_CC_CSR write\n"); 2542539SN/A case TSDEV_CC_MTR: 2552539SN/A panic("TSDEV_CC_MTR write not implemented\n"); 2562539SN/A case TSDEV_CC_MISC: 2572539SN/A uint64_t ipreq; 2582630SN/A ipreq = (pkt->get<uint64_t>() >> 12) & 0xF; 2592539SN/A //If it is bit 12-15, this is an IPI post 2602539SN/A if (ipreq) { 2612539SN/A reqIPI(ipreq); 2622539SN/A supportedWrite = true; 2632539SN/A } 2642539SN/A 2652539SN/A //If it is bit 8-11, this is an IPI clear 2662539SN/A uint64_t ipintr; 2672630SN/A ipintr = (pkt->get<uint64_t>() >> 8) & 0xF; 2682539SN/A if (ipintr) { 2692539SN/A clearIPI(ipintr); 2702539SN/A supportedWrite = true; 2712539SN/A } 2722539SN/A 2732539SN/A //If it is the 4-7th bit, clear the RTC interrupt 2742539SN/A uint64_t itintr; 2752630SN/A itintr = (pkt->get<uint64_t>() >> 4) & 0xF; 2762539SN/A if (itintr) { 2772539SN/A clearITI(itintr); 2782539SN/A supportedWrite = true; 2792539SN/A } 2802539SN/A 2812539SN/A // ignore NXMs 2822630SN/A if (pkt->get<uint64_t>() & 0x10000000) 2832539SN/A supportedWrite = true; 2842539SN/A 2852539SN/A if(!supportedWrite) 2862539SN/A panic("TSDEV_CC_MISC write not implemented\n"); 2872539SN/A 2882549SN/A break; 2892539SN/A case TSDEV_CC_AAR0: 2902539SN/A case TSDEV_CC_AAR1: 2912539SN/A case TSDEV_CC_AAR2: 2922539SN/A case TSDEV_CC_AAR3: 2932539SN/A panic("TSDEV_CC_AARx write not implemeted\n"); 2942539SN/A case TSDEV_CC_DIM0: 2952539SN/A case TSDEV_CC_DIM1: 2962539SN/A case TSDEV_CC_DIM2: 2972539SN/A case TSDEV_CC_DIM3: 2982539SN/A int number; 2992539SN/A if(regnum == TSDEV_CC_DIM0) 3002539SN/A number = 0; 3012539SN/A else if(regnum == TSDEV_CC_DIM1) 3022539SN/A number = 1; 3032539SN/A else if(regnum == TSDEV_CC_DIM2) 3042539SN/A number = 2; 3052539SN/A else 3062539SN/A number = 3; 3072539SN/A 3082539SN/A uint64_t bitvector; 3092539SN/A uint64_t olddim; 3102539SN/A uint64_t olddir; 3112539SN/A 3122539SN/A olddim = dim[number]; 3132539SN/A olddir = dir[number]; 3142630SN/A dim[number] = pkt->get<uint64_t>(); 3152539SN/A dir[number] = dim[number] & drir; 3162539SN/A for(int x = 0; x < 64; x++) 3172539SN/A { 3182539SN/A bitvector = ULL(1) << x; 3192539SN/A // Figure out which bits have changed 3202539SN/A if ((dim[number] & bitvector) != (olddim & bitvector)) 3212539SN/A { 3222539SN/A // The bit is now set and it wasn't before (set) 3232539SN/A if((dim[number] & bitvector) && (dir[number] & bitvector)) 3242539SN/A { 3252539SN/A tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x); 3262539SN/A DPRINTF(Tsunami, "posting dir interrupt to cpu 0\n"); 3272539SN/A } 3282539SN/A else if ((olddir & bitvector) && 3292539SN/A !(dir[number] & bitvector)) 3302539SN/A { 3312539SN/A // The bit was set and now its now clear and 3322539SN/A // we were interrupting on that bit before 3332539SN/A tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x); 3342539SN/A DPRINTF(Tsunami, "dim write resulting in clear" 3352539SN/A " dir interrupt to cpu %d\n", 3362539SN/A x); 3372539SN/A 3382539SN/A } 3392539SN/A 3402539SN/A 3412539SN/A } 3421074SN/A } 3432539SN/A break; 3442539SN/A case TSDEV_CC_DIR0: 3452539SN/A case TSDEV_CC_DIR1: 3462539SN/A case TSDEV_CC_DIR2: 3472539SN/A case TSDEV_CC_DIR3: 3482539SN/A panic("TSDEV_CC_DIR write not implemented\n"); 3492539SN/A case TSDEV_CC_DRIR: 3502539SN/A panic("TSDEV_CC_DRIR write not implemented\n"); 3512539SN/A case TSDEV_CC_PRBEN: 3522539SN/A panic("TSDEV_CC_PRBEN write not implemented\n"); 3532539SN/A case TSDEV_CC_IIC0: 3542539SN/A case TSDEV_CC_IIC1: 3552539SN/A case TSDEV_CC_IIC2: 3562539SN/A case TSDEV_CC_IIC3: 3572539SN/A panic("TSDEV_CC_IICx write not implemented\n"); 3582539SN/A case TSDEV_CC_MPR0: 3592539SN/A case TSDEV_CC_MPR1: 3602539SN/A case TSDEV_CC_MPR2: 3612539SN/A case TSDEV_CC_MPR3: 3622539SN/A panic("TSDEV_CC_MPRx write not implemented\n"); 3632539SN/A case TSDEV_CC_IPIR: 3642630SN/A clearIPI(pkt->get<uint64_t>()); 3652539SN/A break; 3662539SN/A case TSDEV_CC_ITIR: 3672630SN/A clearITI(pkt->get<uint64_t>()); 3682539SN/A break; 3692539SN/A case TSDEV_CC_IPIQ: 3702630SN/A reqIPI(pkt->get<uint64_t>()); 3712539SN/A break; 3722539SN/A default: 3732539SN/A panic("default in cchip read reached, accessing 0x%x\n"); 3742539SN/A } // swtich(regnum) 3752539SN/A } // not BIG_TSUNAMI write 3764870Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 3772539SN/A return pioDelay; 378767SN/A} 379767SN/A 380767SN/Avoid 3811290SN/ATsunamiCChip::clearIPI(uint64_t ipintr) 3821290SN/A{ 3834103Ssaidi@eecs.umich.edu int numcpus = sys->threadContexts.size(); 3841290SN/A assert(numcpus <= Tsunami::Max_CPUs); 3851290SN/A 3861290SN/A if (ipintr) { 3871290SN/A for (int cpunum=0; cpunum < numcpus; cpunum++) { 3881290SN/A // Check each cpu bit 3891290SN/A uint64_t cpumask = ULL(1) << cpunum; 3901290SN/A if (ipintr & cpumask) { 3911290SN/A // Check if there is a pending ipi 3921290SN/A if (ipint & cpumask) { 3931290SN/A ipint &= ~cpumask; 3941290SN/A tsunami->intrctrl->clear(cpunum, TheISA::INTLEVEL_IRQ3, 0); 3951290SN/A DPRINTF(IPI, "clear IPI IPI cpu=%d\n", cpunum); 3961290SN/A } 3971290SN/A else 3981290SN/A warn("clear IPI for CPU=%d, but NO IPI\n", cpunum); 3991290SN/A } 4001290SN/A } 4011290SN/A } 4021290SN/A else 4031290SN/A panic("Big IPI Clear, but not processors indicated\n"); 4041290SN/A} 4051290SN/A 4061290SN/Avoid 4071290SN/ATsunamiCChip::clearITI(uint64_t itintr) 4081290SN/A{ 4094103Ssaidi@eecs.umich.edu int numcpus = sys->threadContexts.size(); 4101290SN/A assert(numcpus <= Tsunami::Max_CPUs); 4111290SN/A 4121290SN/A if (itintr) { 4131290SN/A for (int i=0; i < numcpus; i++) { 4141290SN/A uint64_t cpumask = ULL(1) << i; 4151290SN/A if (itintr & cpumask & itint) { 4161290SN/A tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ2, 0); 4171290SN/A itint &= ~cpumask; 4181290SN/A DPRINTF(Tsunami, "clearing rtc interrupt to cpu=%d\n", i); 4191290SN/A } 4201290SN/A } 4211290SN/A } 4221290SN/A else 4231290SN/A panic("Big ITI Clear, but not processors indicated\n"); 4241290SN/A} 4251290SN/A 4261290SN/Avoid 4271290SN/ATsunamiCChip::reqIPI(uint64_t ipreq) 4281290SN/A{ 4294103Ssaidi@eecs.umich.edu int numcpus = sys->threadContexts.size(); 4301290SN/A assert(numcpus <= Tsunami::Max_CPUs); 4311290SN/A 4321290SN/A if (ipreq) { 4331290SN/A for (int cpunum=0; cpunum < numcpus; cpunum++) { 4341290SN/A // Check each cpu bit 4351290SN/A uint64_t cpumask = ULL(1) << cpunum; 4361290SN/A if (ipreq & cpumask) { 4371290SN/A // Check if there is already an ipi (bits 8:11) 4381290SN/A if (!(ipint & cpumask)) { 4391290SN/A ipint |= cpumask; 4401290SN/A tsunami->intrctrl->post(cpunum, TheISA::INTLEVEL_IRQ3, 0); 4411290SN/A DPRINTF(IPI, "send IPI cpu=%d\n", cpunum); 4421290SN/A } 4431290SN/A else 4441290SN/A warn("post IPI for CPU=%d, but IPI already\n", cpunum); 4451290SN/A } 4461290SN/A } 4471290SN/A } 4481290SN/A else 4491290SN/A panic("Big IPI Request, but not processors indicated\n"); 4501290SN/A} 4511290SN/A 4521290SN/A 4531290SN/Avoid 454831SN/ATsunamiCChip::postRTC() 455831SN/A{ 4564103Ssaidi@eecs.umich.edu int size = sys->threadContexts.size(); 4571290SN/A assert(size <= Tsunami::Max_CPUs); 458831SN/A 459831SN/A for (int i = 0; i < size; i++) { 4601290SN/A uint64_t cpumask = ULL(1) << i; 4612539SN/A if (!(cpumask & itint)) { 4622539SN/A itint |= cpumask; 4632539SN/A tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ2, 0); 4644739Sstever@eecs.umich.edu DPRINTF(Tsunami, "Posting RTC interrupt to cpu=%d\n", i); 4652539SN/A } 466831SN/A } 467831SN/A 468831SN/A} 469831SN/A 470831SN/Avoid 471817SN/ATsunamiCChip::postDRIR(uint32_t interrupt) 472777SN/A{ 4731290SN/A uint64_t bitvector = ULL(1) << interrupt; 4744103Ssaidi@eecs.umich.edu uint64_t size = sys->threadContexts.size(); 4751290SN/A assert(size <= Tsunami::Max_CPUs); 476777SN/A drir |= bitvector; 4771290SN/A 478831SN/A for(int i=0; i < size; i++) { 479817SN/A dir[i] = dim[i] & drir; 4802539SN/A if (dim[i] & bitvector) { 4812539SN/A tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ1, interrupt); 4822539SN/A DPRINTF(Tsunami, "posting dir interrupt to cpu %d," 483817SN/A "interrupt %d\n",i, interrupt); 4842539SN/A } 485777SN/A } 486777SN/A} 487777SN/A 488777SN/Avoid 489817SN/ATsunamiCChip::clearDRIR(uint32_t interrupt) 490777SN/A{ 4911290SN/A uint64_t bitvector = ULL(1) << interrupt; 4924103Ssaidi@eecs.umich.edu uint64_t size = sys->threadContexts.size(); 4931290SN/A assert(size <= Tsunami::Max_CPUs); 4941290SN/A 495817SN/A if (drir & bitvector) 496817SN/A { 497817SN/A drir &= ~bitvector; 498831SN/A for(int i=0; i < size; i++) { 4992539SN/A if (dir[i] & bitvector) { 5002539SN/A tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ1, interrupt); 5012539SN/A DPRINTF(Tsunami, "clearing dir interrupt to cpu %d," 502817SN/A "interrupt %d\n",i, interrupt); 503777SN/A 5042539SN/A } 5052539SN/A dir[i] = dim[i] & drir; 506777SN/A } 507777SN/A } 508817SN/A else 509817SN/A DPRINTF(Tsunami, "Spurrious clear? interrupt %d\n", interrupt); 510777SN/A} 511777SN/A 512909SN/A 513777SN/Avoid 514767SN/ATsunamiCChip::serialize(std::ostream &os) 515767SN/A{ 516811SN/A SERIALIZE_ARRAY(dim, Tsunami::Max_CPUs); 517811SN/A SERIALIZE_ARRAY(dir, Tsunami::Max_CPUs); 5181290SN/A SERIALIZE_SCALAR(ipint); 5191290SN/A SERIALIZE_SCALAR(itint); 520811SN/A SERIALIZE_SCALAR(drir); 521767SN/A} 522767SN/A 523767SN/Avoid 524767SN/ATsunamiCChip::unserialize(Checkpoint *cp, const std::string §ion) 525767SN/A{ 526811SN/A UNSERIALIZE_ARRAY(dim, Tsunami::Max_CPUs); 527811SN/A UNSERIALIZE_ARRAY(dir, Tsunami::Max_CPUs); 5281290SN/A UNSERIALIZE_SCALAR(ipint); 5291290SN/A UNSERIALIZE_SCALAR(itint); 530811SN/A UNSERIALIZE_SCALAR(drir); 531767SN/A} 532767SN/A 5334762Snate@binkert.orgTsunamiCChip * 5344762Snate@binkert.orgTsunamiCChipParams::create() 535767SN/A{ 5364762Snate@binkert.org return new TsunamiCChip(this); 537767SN/A} 538