tsunami_cchip.cc revision 775 
1/* $Id$ */
2
3/* @file
4 * Tsunami CChip (processor, memory, or IO)
5 */
6
7#include <deque>
8#include <string>
9#include <vector>
10
11#include "base/trace.hh"
12#include "cpu/exec_context.hh"
13#include "dev/console.hh"
14#include "dev/etherdev.hh"
15#include "dev/scsi_ctrl.hh"
16#include "dev/tlaser_clock.hh"
17#include "dev/tsunami_cchip.hh"
18#include "dev/tsunamireg.h"
19#include "dev/tsunami.hh"
20#include "cpu/intr_control.hh"
21#include "mem/functional_mem/memory_control.hh"
22#include "sim/builder.hh"
23#include "sim/system.hh"
24
25using namespace std;
26
27TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t,
28                       Addr addr, Addr mask, MemoryController *mmu)
29    : MmapDevice(name, addr, mask, mmu), tsunami(t)
30{
31    for(int i=0; i < Tsunami::Max_CPUs; i++) {
32        dim[i] = 0;
33        dir[i] = 0;
34    }
35
36    drir = 0;
37    misc = 0;
38    RTCInterrupting = false;
39
40    //Put back pointer in tsunami
41    tsunami->cchip = this;
42}
43
44Fault
45TsunamiCChip::read(MemReqPtr req, uint8_t *data)
46{
47    DPRINTF(Tsunami, "read  va=%#x size=%d\n",
48            req->vaddr, req->size);
49
50    Addr daddr = (req->paddr & addr_mask) >> 6;
51//    ExecContext *xc = req->xc;
52//    int cpuid = xc->cpu_id;
53
54    switch (req->size) {
55
56      case sizeof(uint64_t):
57          switch(daddr) {
58              case TSDEV_CC_CSR:
59                  *(uint64_t*)data = 0x0;
60                  return No_Fault;
61              case TSDEV_CC_MTR:
62                  panic("TSDEV_CC_MTR not implemeted\n");
63                   return No_Fault;
64              case TSDEV_CC_MISC:
65                *(uint64_t*)data = misc;
66                  return No_Fault;
67              case TSDEV_CC_AAR0:
68              case TSDEV_CC_AAR1:
69              case TSDEV_CC_AAR2:
70              case TSDEV_CC_AAR3:
71                  panic("TSDEV_CC_AARx not implemeted\n");
72                  return No_Fault;
73              case TSDEV_CC_DIM0:
74                  *(uint64_t*)data = dim[0];
75                  return No_Fault;
76              case TSDEV_CC_DIM1:
77                  *(uint64_t*)data = dim[1];
78                  return No_Fault;
79              case TSDEV_CC_DIM2:
80                  *(uint64_t*)data = dim[2];
81                  return No_Fault;
82              case TSDEV_CC_DIM3:
83                  *(uint64_t*)data = dim[3];
84                  return No_Fault;
85              case TSDEV_CC_DIR0:
86                  *(uint64_t*)data = dir[0];
87                  return No_Fault;
88              case TSDEV_CC_DIR1:
89                  *(uint64_t*)data = dir[1];
90                  return No_Fault;
91              case TSDEV_CC_DIR2:
92                  *(uint64_t*)data = dir[2];
93                  return No_Fault;
94              case TSDEV_CC_DIR3:
95                  *(uint64_t*)data = dir[3];
96                  return No_Fault;
97              case TSDEV_CC_DRIR:
98                  *(uint64_t*)data = drir;
99                  return No_Fault;
100              case TSDEV_CC_PRBEN:
101                  panic("TSDEV_CC_PRBEN not implemented\n");
102                  return No_Fault;
103              case TSDEV_CC_IIC0:
104              case TSDEV_CC_IIC1:
105              case TSDEV_CC_IIC2:
106              case TSDEV_CC_IIC3:
107                  panic("TSDEV_CC_IICx not implemented\n");
108                  return No_Fault;
109              case TSDEV_CC_MPR0:
110              case TSDEV_CC_MPR1:
111              case TSDEV_CC_MPR2:
112              case TSDEV_CC_MPR3:
113                  panic("TSDEV_CC_MPRx not implemented\n");
114                  return No_Fault;
115              default:
116                  panic("default in cchip read reached, accessing 0x%x\n");
117           } // uint64_t
118
119      break;
120      case sizeof(uint32_t):
121      case sizeof(uint16_t):
122      case sizeof(uint8_t):
123      default:
124        panic("invalid access size(?) for tsunami register!\n");
125    }
126    DPRINTFN("Tsunami CChip ERROR: read  daddr=%#x size=%d\n", daddr, req->size);
127
128    return No_Fault;
129}
130
131Fault
132TsunamiCChip::write(MemReqPtr req, const uint8_t *data)
133{
134    DPRINTF(Tsunami, "write - va=%#x size=%d \n",
135            req->vaddr, req->size);
136
137    Addr daddr = (req->paddr & addr_mask) >> 6;
138
139    switch (req->size) {
140
141      case sizeof(uint64_t):
142          switch(daddr) {
143              case TSDEV_CC_CSR:
144                  panic("TSDEV_CC_CSR write\n");
145                  return No_Fault;
146              case TSDEV_CC_MTR:
147                  panic("TSDEV_CC_MTR write not implemented\n");
148                   return No_Fault;
149              case TSDEV_CC_MISC:
150                //If it is the seventh bit, clear the RTC interrupt
151                if ((*(uint64_t*) data) & (1<<7)) {
152                    RTCInterrupting = false;
153                    tsunami->intrctrl->clear(0, TheISA::INTLEVEL_IRQ2, 0);
154                    misc &= ~(1<<7);
155                } else panic("TSDEV_CC_MISC write not implemented\n");
156                  return No_Fault;
157              case TSDEV_CC_AAR0:
158              case TSDEV_CC_AAR1:
159              case TSDEV_CC_AAR2:
160              case TSDEV_CC_AAR3:
161                  panic("TSDEV_CC_AARx write not implemeted\n");
162                  return No_Fault;
163              case TSDEV_CC_DIM0:
164                   dim[0] = *(uint64_t*)data;
165                  return No_Fault;
166              case TSDEV_CC_DIM1:
167                  dim[1] = *(uint64_t*)data;
168                  return No_Fault;
169              case TSDEV_CC_DIM2:
170                  dim[2] = *(uint64_t*)data;
171                  return No_Fault;
172              case TSDEV_CC_DIM3:
173                  dim[3] = *(uint64_t*)data;
174                  return No_Fault;
175              case TSDEV_CC_DIR0:
176              case TSDEV_CC_DIR1:
177              case TSDEV_CC_DIR2:
178              case TSDEV_CC_DIR3:
179                  panic("TSDEV_CC_DIR write not implemented\n");
180                  return No_Fault;
181              case TSDEV_CC_DRIR:
182                  panic("TSDEV_CC_DRIR write not implemented\n");
183                  return No_Fault;
184              case TSDEV_CC_PRBEN:
185                  panic("TSDEV_CC_PRBEN write not implemented\n");
186                  return No_Fault;
187              case TSDEV_CC_IIC0:
188              case TSDEV_CC_IIC1:
189              case TSDEV_CC_IIC2:
190              case TSDEV_CC_IIC3:
191                  panic("TSDEV_CC_IICx write not implemented\n");
192                  return No_Fault;
193              case TSDEV_CC_MPR0:
194              case TSDEV_CC_MPR1:
195              case TSDEV_CC_MPR2:
196              case TSDEV_CC_MPR3:
197                  panic("TSDEV_CC_MPRx write not implemented\n");
198                  return No_Fault;
199              default:
200                  panic("default in cchip read reached, accessing 0x%x\n");
201          }
202
203      break;
204      case sizeof(uint32_t):
205      case sizeof(uint16_t):
206      case sizeof(uint8_t):
207      default:
208        panic("invalid access size(?) for tsunami register!\n");
209    }
210
211    DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size);
212
213    return No_Fault;
214}
215
216void
217TsunamiCChip::serialize(std::ostream &os)
218{
219    // code should be written
220}
221
222void
223TsunamiCChip::unserialize(Checkpoint *cp, const std::string &section)
224{
225    //code should be written
226}
227
228BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
229
230    SimObjectParam<Tsunami *> tsunami;
231    SimObjectParam<MemoryController *> mmu;
232    Param<Addr> addr;
233    Param<Addr> mask;
234
235END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
236
237BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
238
239    INIT_PARAM(tsunami, "Tsunami"),
240    INIT_PARAM(mmu, "Memory Controller"),
241    INIT_PARAM(addr, "Device Address"),
242    INIT_PARAM(mask, "Address Mask")
243
244END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
245
246CREATE_SIM_OBJECT(TsunamiCChip)
247{
248    return new TsunamiCChip(getInstanceName(), tsunami, addr, mask, mmu);
249}
250
251REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip)
252