tsunami_cchip.cc revision 767
17732SAli.Saidi@ARM.com/* $Id$ */
27732SAli.Saidi@ARM.com
37732SAli.Saidi@ARM.com/* @file
47732SAli.Saidi@ARM.com * Tsunami CChip (processor, memory, or IO)
57732SAli.Saidi@ARM.com */
67732SAli.Saidi@ARM.com
77732SAli.Saidi@ARM.com#include <deque>
87732SAli.Saidi@ARM.com#include <string>
97732SAli.Saidi@ARM.com#include <vector>
107732SAli.Saidi@ARM.com
117732SAli.Saidi@ARM.com#include "base/trace.hh"
127732SAli.Saidi@ARM.com#include "cpu/exec_context.hh"
137732SAli.Saidi@ARM.com#include "dev/console.hh"
147732SAli.Saidi@ARM.com#include "dev/etherdev.hh"
157732SAli.Saidi@ARM.com#include "dev/scsi_ctrl.hh"
167732SAli.Saidi@ARM.com#include "dev/tlaser_clock.hh"
177732SAli.Saidi@ARM.com#include "dev/tsunami_cchip.hh"
187732SAli.Saidi@ARM.com#include "dev/tsunamireg.h"
197732SAli.Saidi@ARM.com#include "dev/tsunami.hh"
207732SAli.Saidi@ARM.com#include "mem/functional_mem/memory_control.hh"
217732SAli.Saidi@ARM.com#include "sim/builder.hh"
227732SAli.Saidi@ARM.com#include "sim/system.hh"
237732SAli.Saidi@ARM.com
247732SAli.Saidi@ARM.comusing namespace std;
257732SAli.Saidi@ARM.com
267732SAli.Saidi@ARM.comTsunamiCChip::TsunamiCChip(const string &name, Tsunami *t,
277732SAli.Saidi@ARM.com                       Addr addr, Addr mask, MemoryController *mmu)
287732SAli.Saidi@ARM.com    : MmapDevice(name, addr, mask, mmu), tsunami(t)
297732SAli.Saidi@ARM.com{
307732SAli.Saidi@ARM.com    for(int i=0; i < Tsunami::Max_CPUs; i++) {
317732SAli.Saidi@ARM.com        dim[i] = 0;
327732SAli.Saidi@ARM.com        dir[i] = 0;
337732SAli.Saidi@ARM.com    }
347732SAli.Saidi@ARM.com
357732SAli.Saidi@ARM.com    drir = 0;
367732SAli.Saidi@ARM.com}
377732SAli.Saidi@ARM.com
387732SAli.Saidi@ARM.comFault
397732SAli.Saidi@ARM.comTsunamiCChip::read(MemReqPtr req, uint8_t *data)
407732SAli.Saidi@ARM.com{
417732SAli.Saidi@ARM.com    DPRINTF(Tsunami, "cchip read  va=%#x size=%d\n",
427732SAli.Saidi@ARM.com            req->vaddr, req->size);
439660SAndreas.Sandberg@ARM.com
447732SAli.Saidi@ARM.com    Addr daddr = (req->paddr & addr_mask) >> 6;
458987SAli.Saidi@ARM.com//    ExecContext *xc = req->xc;
468987SAli.Saidi@ARM.com//    int cpuid = xc->cpu_id;
478987SAli.Saidi@ARM.com
488987SAli.Saidi@ARM.com    switch (req->size) {
497732SAli.Saidi@ARM.com
507732SAli.Saidi@ARM.com      case sizeof(uint64_t):
517732SAli.Saidi@ARM.com          switch(daddr) {
527732SAli.Saidi@ARM.com              case TSDEV_CC_CSR:
537732SAli.Saidi@ARM.com                  *(uint64_t*)data = 0x0;
549660SAndreas.Sandberg@ARM.com                  return No_Fault;
559686Sandreas@sandberg.pp.se              case TSDEV_CC_MTR:
569660SAndreas.Sandberg@ARM.com                  panic("TSDEV_CC_MTR not implemeted\n");
579660SAndreas.Sandberg@ARM.com                   return No_Fault;
589660SAndreas.Sandberg@ARM.com              case TSDEV_CC_MISC:
599660SAndreas.Sandberg@ARM.com                  panic("TSDEV_CC_MISC not implemented\n");
609660SAndreas.Sandberg@ARM.com                  return No_Fault;
619660SAndreas.Sandberg@ARM.com              case TSDEV_CC_AAR0:
629660SAndreas.Sandberg@ARM.com              case TSDEV_CC_AAR1:
639686Sandreas@sandberg.pp.se              case TSDEV_CC_AAR2:
649686Sandreas@sandberg.pp.se              case TSDEV_CC_AAR3:
659686Sandreas@sandberg.pp.se                  panic("TSDEV_CC_AARx not implemeted\n");
669686Sandreas@sandberg.pp.se                  return No_Fault;
679686Sandreas@sandberg.pp.se              case TSDEV_CC_DIM0:
689660SAndreas.Sandberg@ARM.com                  *(uint64_t*)data = dim[0];
699660SAndreas.Sandberg@ARM.com                  return No_Fault;
709660SAndreas.Sandberg@ARM.com              case TSDEV_CC_DIM1:
717732SAli.Saidi@ARM.com                  *(uint64_t*)data = dim[1];
729660SAndreas.Sandberg@ARM.com                  return No_Fault;
739660SAndreas.Sandberg@ARM.com              case TSDEV_CC_DIM2:
749660SAndreas.Sandberg@ARM.com                  *(uint64_t*)data = dim[2];
759660SAndreas.Sandberg@ARM.com                  return No_Fault;
769660SAndreas.Sandberg@ARM.com              case TSDEV_CC_DIM3:
779660SAndreas.Sandberg@ARM.com                  *(uint64_t*)data = dim[3];
789686Sandreas@sandberg.pp.se                  return No_Fault;
799660SAndreas.Sandberg@ARM.com              case TSDEV_CC_DIR0:
809660SAndreas.Sandberg@ARM.com                  *(uint64_t*)data = dir[0];
819660SAndreas.Sandberg@ARM.com                  return No_Fault;
827732SAli.Saidi@ARM.com              case TSDEV_CC_DIR1:
839660SAndreas.Sandberg@ARM.com                  *(uint64_t*)data = dir[1];
849660SAndreas.Sandberg@ARM.com                  return No_Fault;
859660SAndreas.Sandberg@ARM.com              case TSDEV_CC_DIR2:
869660SAndreas.Sandberg@ARM.com                  *(uint64_t*)data = dir[2];
879660SAndreas.Sandberg@ARM.com                  return No_Fault;
889660SAndreas.Sandberg@ARM.com              case TSDEV_CC_DIR3:
899660SAndreas.Sandberg@ARM.com                  *(uint64_t*)data = dir[3];
909660SAndreas.Sandberg@ARM.com                  return No_Fault;
919660SAndreas.Sandberg@ARM.com              case TSDEV_CC_DRIR:
929660SAndreas.Sandberg@ARM.com                  *(uint64_t*)data = drir;
939660SAndreas.Sandberg@ARM.com                  return No_Fault;
949660SAndreas.Sandberg@ARM.com              case TSDEV_CC_PRBEN:
959660SAndreas.Sandberg@ARM.com                  panic("TSDEV_CC_PRBEN not implemented\n");
969660SAndreas.Sandberg@ARM.com                  return No_Fault;
979660SAndreas.Sandberg@ARM.com              case TSDEV_CC_IIC0:
989660SAndreas.Sandberg@ARM.com              case TSDEV_CC_IIC1:
999660SAndreas.Sandberg@ARM.com              case TSDEV_CC_IIC2:
1009660SAndreas.Sandberg@ARM.com              case TSDEV_CC_IIC3:
1019660SAndreas.Sandberg@ARM.com                  panic("TSDEV_CC_IICx not implemented\n");
1029660SAndreas.Sandberg@ARM.com                  return No_Fault;
1039660SAndreas.Sandberg@ARM.com              case TSDEV_CC_MPR0:
1049660SAndreas.Sandberg@ARM.com              case TSDEV_CC_MPR1:
1059660SAndreas.Sandberg@ARM.com              case TSDEV_CC_MPR2:
1069660SAndreas.Sandberg@ARM.com              case TSDEV_CC_MPR3:
1079660SAndreas.Sandberg@ARM.com                  panic("TSDEV_CC_MPRx not implemented\n");
1089660SAndreas.Sandberg@ARM.com                  return No_Fault;
1099660SAndreas.Sandberg@ARM.com           } // uint64_t
1109660SAndreas.Sandberg@ARM.com
1119660SAndreas.Sandberg@ARM.com      break;
1129660SAndreas.Sandberg@ARM.com      case sizeof(uint32_t):
1139660SAndreas.Sandberg@ARM.com      case sizeof(uint16_t):
1149660SAndreas.Sandberg@ARM.com      case sizeof(uint8_t):
1159660SAndreas.Sandberg@ARM.com      default:
1169660SAndreas.Sandberg@ARM.com        panic("invalid access size(?) for tsunami register!");
1179660SAndreas.Sandberg@ARM.com    }
1189660SAndreas.Sandberg@ARM.com    DPRINTFN("Tsunami CChip ERROR: read  daddr=%#x size=%d\n", daddr, req->size);
1199660SAndreas.Sandberg@ARM.com
1209660SAndreas.Sandberg@ARM.com    return No_Fault;
1219660SAndreas.Sandberg@ARM.com}
1229660SAndreas.Sandberg@ARM.com
1239660SAndreas.Sandberg@ARM.comFault
124TsunamiCChip::write(MemReqPtr req, const uint8_t *data)
125{
126    DPRINTF(Tsunami, "Tsunami CChip write - va=%#x size=%d \n",
127            req->vaddr, req->size);
128
129    Addr daddr = (req->paddr & addr_mask) >> 6;
130
131    switch (req->size) {
132
133      case sizeof(uint64_t):
134          switch(daddr) {
135              case TSDEV_CC_CSR:
136                  panic("TSDEV_CC_CSR write\n");
137                  return No_Fault;
138              case TSDEV_CC_MTR:
139                  panic("TSDEV_CC_MTR write not implemented\n");
140                   return No_Fault;
141              case TSDEV_CC_MISC:
142                  panic("TSDEV_CC_MISC write not implemented\n");
143                  return No_Fault;
144              case TSDEV_CC_AAR0:
145              case TSDEV_CC_AAR1:
146              case TSDEV_CC_AAR2:
147              case TSDEV_CC_AAR3:
148                  panic("TSDEV_CC_AARx write not implemeted\n");
149                  return No_Fault;
150              case TSDEV_CC_DIM0:
151                   dim[0] = *(uint64_t*)data;
152                  return No_Fault;
153              case TSDEV_CC_DIM1:
154                  dim[1] = *(uint64_t*)data;
155                  return No_Fault;
156              case TSDEV_CC_DIM2:
157                  dim[2] = *(uint64_t*)data;
158                  return No_Fault;
159              case TSDEV_CC_DIM3:
160                  dim[3] = *(uint64_t*)data;
161                  return No_Fault;
162              case TSDEV_CC_DIR0:
163              case TSDEV_CC_DIR1:
164              case TSDEV_CC_DIR2:
165              case TSDEV_CC_DIR3:
166                  panic("TSDEV_CC_DIR write not implemented\n");
167                  return No_Fault;
168              case TSDEV_CC_DRIR:
169                  panic("TSDEV_CC_DRIR write not implemented\n");
170                  return No_Fault;
171              case TSDEV_CC_PRBEN:
172                  panic("TSDEV_CC_PRBEN write not implemented\n");
173                  return No_Fault;
174              case TSDEV_CC_IIC0:
175              case TSDEV_CC_IIC1:
176              case TSDEV_CC_IIC2:
177              case TSDEV_CC_IIC3:
178                  panic("TSDEV_CC_IICx write not implemented\n");
179                  return No_Fault;
180              case TSDEV_CC_MPR0:
181              case TSDEV_CC_MPR1:
182              case TSDEV_CC_MPR2:
183              case TSDEV_CC_MPR3:
184                  panic("TSDEV_CC_MPRx write not implemented\n");
185                  return No_Fault;
186          }
187
188      break;
189      case sizeof(uint32_t):
190      case sizeof(uint16_t):
191      case sizeof(uint8_t):
192      default:
193        panic("invalid access size(?) for tsunami register!");
194    }
195
196    DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size);
197
198    return No_Fault;
199}
200
201void
202TsunamiCChip::serialize(std::ostream &os)
203{
204    // code should be written
205}
206
207void
208TsunamiCChip::unserialize(Checkpoint *cp, const std::string &section)
209{
210    //code should be written
211}
212
213BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
214
215    SimObjectParam<Tsunami *> tsunami;
216    SimObjectParam<MemoryController *> mmu;
217    Param<Addr> addr;
218    Param<Addr> mask;
219
220END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
221
222BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
223
224    INIT_PARAM(tsunami, "Tsunami"),
225    INIT_PARAM(mmu, "Memory Controller"),
226    INIT_PARAM(addr, "Device Address"),
227    INIT_PARAM(mask, "Address Mask")
228
229END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
230
231CREATE_SIM_OBJECT(TsunamiCChip)
232{
233    return new TsunamiCChip(getInstanceName(), tsunami, addr, mask, mmu);
234}
235
236REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip)
237