tsunami_cchip.cc revision 2641 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @file
30 * Emulation of the Tsunami CChip CSRs
31 */
32
33#include <deque>
34#include <string>
35#include <vector>
36
37#include "arch/alpha/ev5.hh"
38#include "base/trace.hh"
39#include "dev/tsunami_cchip.hh"
40#include "dev/tsunamireg.h"
41#include "dev/tsunami.hh"
42#include "mem/port.hh"
43#include "cpu/exec_context.hh"
44#include "cpu/intr_control.hh"
45#include "sim/builder.hh"
46#include "sim/system.hh"
47
48using namespace std;
49//Should this be AlphaISA?
50using namespace TheISA;
51
52TsunamiCChip::TsunamiCChip(Params *p)
53    : BasicPioDevice(p), tsunami(p->tsunami)
54{
55    pioSize = 0xfffffff;
56
57    drir = 0;
58    ipint = 0;
59    itint = 0;
60
61    for (int x = 0; x < Tsunami::Max_CPUs; x++)
62    {
63        dim[x] = 0;
64        dir[x] = 0;
65    }
66
67    //Put back pointer in tsunami
68    tsunami->cchip = this;
69}
70
71Tick
72TsunamiCChip::read(Packet *pkt)
73{
74    DPRINTF(Tsunami, "read  va=%#x size=%d\n", pkt->getAddr(), pkt->getSize());
75
76    assert(pkt->result == Packet::Unknown);
77    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
78
79    pkt->time += pioDelay;
80    Addr regnum = (pkt->getAddr() - pioAddr) >> 6;
81    Addr daddr = (pkt->getAddr() - pioAddr);
82
83    pkt->allocate();
84    switch (pkt->getSize()) {
85
86      case sizeof(uint64_t):
87          if (daddr & TSDEV_CC_BDIMS)
88          {
89              pkt->set(dim[(daddr >> 4) & 0x3F]);
90              break;
91          }
92
93          if (daddr & TSDEV_CC_BDIRS)
94          {
95              pkt->set(dir[(daddr >> 4) & 0x3F]);
96              break;
97          }
98
99          switch(regnum) {
100              case TSDEV_CC_CSR:
101                  pkt->set(0x0);
102                  break;
103              case TSDEV_CC_MTR:
104                  panic("TSDEV_CC_MTR not implemeted\n");
105                   break;
106              case TSDEV_CC_MISC:
107                  pkt->set((ipint << 8) & 0xF | (itint << 4) & 0xF |
108                                     (pkt->req->getCpuNum() & 0x3));
109                  break;
110              case TSDEV_CC_AAR0:
111              case TSDEV_CC_AAR1:
112              case TSDEV_CC_AAR2:
113              case TSDEV_CC_AAR3:
114                  pkt->set(0);
115                  break;
116              case TSDEV_CC_DIM0:
117                  pkt->set(dim[0]);
118                  break;
119              case TSDEV_CC_DIM1:
120                  pkt->set(dim[1]);
121                  break;
122              case TSDEV_CC_DIM2:
123                  pkt->set(dim[2]);
124                  break;
125              case TSDEV_CC_DIM3:
126                  pkt->set(dim[3]);
127                  break;
128              case TSDEV_CC_DIR0:
129                  pkt->set(dir[0]);
130                  break;
131              case TSDEV_CC_DIR1:
132                  pkt->set(dir[1]);
133                  break;
134              case TSDEV_CC_DIR2:
135                  pkt->set(dir[2]);
136                  break;
137              case TSDEV_CC_DIR3:
138                  pkt->set(dir[3]);
139                  break;
140              case TSDEV_CC_DRIR:
141                  pkt->set(drir);
142                  break;
143              case TSDEV_CC_PRBEN:
144                  panic("TSDEV_CC_PRBEN not implemented\n");
145                  break;
146              case TSDEV_CC_IIC0:
147              case TSDEV_CC_IIC1:
148              case TSDEV_CC_IIC2:
149              case TSDEV_CC_IIC3:
150                  panic("TSDEV_CC_IICx not implemented\n");
151                  break;
152              case TSDEV_CC_MPR0:
153              case TSDEV_CC_MPR1:
154              case TSDEV_CC_MPR2:
155              case TSDEV_CC_MPR3:
156                  panic("TSDEV_CC_MPRx not implemented\n");
157                  break;
158              case TSDEV_CC_IPIR:
159                  pkt->set(ipint);
160                  break;
161              case TSDEV_CC_ITIR:
162                  pkt->set(itint);
163                  break;
164              default:
165                  panic("default in cchip read reached, accessing 0x%x\n");
166           } // uint64_t
167
168      break;
169      case sizeof(uint32_t):
170      case sizeof(uint16_t):
171      case sizeof(uint8_t):
172      default:
173        panic("invalid access size(?) for tsunami register!\n");
174    }
175    DPRINTF(Tsunami, "Tsunami CChip: read  regnum=%#x size=%d data=%lld\n",
176            regnum, pkt->getSize(), pkt->get<uint64_t>());
177
178    pkt->result = Packet::Success;
179    return pioDelay;
180}
181
182Tick
183TsunamiCChip::write(Packet *pkt)
184{
185    pkt->time += pioDelay;
186
187
188    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
189    Addr daddr = pkt->getAddr() - pioAddr;
190    Addr regnum = (pkt->getAddr() - pioAddr) >> 6 ;
191
192
193    assert(pkt->getSize() == sizeof(uint64_t));
194
195    DPRINTF(Tsunami, "write - addr=%#x value=%#x\n", pkt->getAddr(), pkt->get<uint64_t>());
196
197    bool supportedWrite = false;
198
199
200    if (daddr & TSDEV_CC_BDIMS)
201    {
202        int number = (daddr >> 4) & 0x3F;
203
204        uint64_t bitvector;
205        uint64_t olddim;
206        uint64_t olddir;
207
208        olddim = dim[number];
209        olddir = dir[number];
210        dim[number] = pkt->get<uint64_t>();
211        dir[number] = dim[number] & drir;
212        for(int x = 0; x < Tsunami::Max_CPUs; x++)
213        {
214            bitvector = ULL(1) << x;
215            // Figure out which bits have changed
216            if ((dim[number] & bitvector) != (olddim & bitvector))
217            {
218                // The bit is now set and it wasn't before (set)
219                if((dim[number] & bitvector) && (dir[number] & bitvector))
220                {
221                    tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
222                    DPRINTF(Tsunami, "dim write resulting in posting dir"
223                            " interrupt to cpu %d\n", number);
224                }
225                else if ((olddir & bitvector) &&
226                        !(dir[number] & bitvector))
227                {
228                    // The bit was set and now its now clear and
229                    // we were interrupting on that bit before
230                    tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
231                    DPRINTF(Tsunami, "dim write resulting in clear"
232                            " dir interrupt to cpu %d\n", number);
233
234                }
235
236
237            }
238        }
239    } else {
240        switch(regnum) {
241          case TSDEV_CC_CSR:
242              panic("TSDEV_CC_CSR write\n");
243          case TSDEV_CC_MTR:
244              panic("TSDEV_CC_MTR write not implemented\n");
245          case TSDEV_CC_MISC:
246            uint64_t ipreq;
247            ipreq = (pkt->get<uint64_t>() >> 12) & 0xF;
248            //If it is bit 12-15, this is an IPI post
249            if (ipreq) {
250                reqIPI(ipreq);
251                supportedWrite = true;
252            }
253
254            //If it is bit 8-11, this is an IPI clear
255            uint64_t ipintr;
256            ipintr = (pkt->get<uint64_t>() >> 8) & 0xF;
257            if (ipintr) {
258                clearIPI(ipintr);
259                supportedWrite = true;
260            }
261
262            //If it is the 4-7th bit, clear the RTC interrupt
263            uint64_t itintr;
264              itintr = (pkt->get<uint64_t>() >> 4) & 0xF;
265            if (itintr) {
266                  clearITI(itintr);
267                supportedWrite = true;
268            }
269
270              // ignore NXMs
271              if (pkt->get<uint64_t>() & 0x10000000)
272                  supportedWrite = true;
273
274            if(!supportedWrite)
275                  panic("TSDEV_CC_MISC write not implemented\n");
276
277            break;
278            case TSDEV_CC_AAR0:
279            case TSDEV_CC_AAR1:
280            case TSDEV_CC_AAR2:
281            case TSDEV_CC_AAR3:
282                panic("TSDEV_CC_AARx write not implemeted\n");
283            case TSDEV_CC_DIM0:
284            case TSDEV_CC_DIM1:
285            case TSDEV_CC_DIM2:
286            case TSDEV_CC_DIM3:
287                int number;
288                if(regnum == TSDEV_CC_DIM0)
289                    number = 0;
290                else if(regnum == TSDEV_CC_DIM1)
291                    number = 1;
292                else if(regnum == TSDEV_CC_DIM2)
293                    number = 2;
294                else
295                    number = 3;
296
297                uint64_t bitvector;
298                uint64_t olddim;
299                uint64_t olddir;
300
301                olddim = dim[number];
302                olddir = dir[number];
303                dim[number] = pkt->get<uint64_t>();
304                dir[number] = dim[number] & drir;
305                for(int x = 0; x < 64; x++)
306                {
307                    bitvector = ULL(1) << x;
308                    // Figure out which bits have changed
309                    if ((dim[number] & bitvector) != (olddim & bitvector))
310                    {
311                        // The bit is now set and it wasn't before (set)
312                        if((dim[number] & bitvector) && (dir[number] & bitvector))
313                        {
314                          tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x);
315                          DPRINTF(Tsunami, "posting dir interrupt to cpu 0\n");
316                        }
317                        else if ((olddir & bitvector) &&
318                                !(dir[number] & bitvector))
319                        {
320                            // The bit was set and now its now clear and
321                            // we were interrupting on that bit before
322                            tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x);
323                          DPRINTF(Tsunami, "dim write resulting in clear"
324                                    " dir interrupt to cpu %d\n",
325                                    x);
326
327                        }
328
329
330                    }
331                }
332                break;
333            case TSDEV_CC_DIR0:
334            case TSDEV_CC_DIR1:
335            case TSDEV_CC_DIR2:
336            case TSDEV_CC_DIR3:
337                panic("TSDEV_CC_DIR write not implemented\n");
338            case TSDEV_CC_DRIR:
339                panic("TSDEV_CC_DRIR write not implemented\n");
340            case TSDEV_CC_PRBEN:
341                panic("TSDEV_CC_PRBEN write not implemented\n");
342            case TSDEV_CC_IIC0:
343            case TSDEV_CC_IIC1:
344            case TSDEV_CC_IIC2:
345            case TSDEV_CC_IIC3:
346                panic("TSDEV_CC_IICx write not implemented\n");
347            case TSDEV_CC_MPR0:
348            case TSDEV_CC_MPR1:
349            case TSDEV_CC_MPR2:
350            case TSDEV_CC_MPR3:
351                panic("TSDEV_CC_MPRx write not implemented\n");
352            case TSDEV_CC_IPIR:
353                clearIPI(pkt->get<uint64_t>());
354                break;
355            case TSDEV_CC_ITIR:
356                clearITI(pkt->get<uint64_t>());
357                break;
358            case TSDEV_CC_IPIQ:
359                reqIPI(pkt->get<uint64_t>());
360                break;
361            default:
362              panic("default in cchip read reached, accessing 0x%x\n");
363        }  // swtich(regnum)
364    } // not BIG_TSUNAMI write
365    pkt->result = Packet::Success;
366    return pioDelay;
367}
368
369void
370TsunamiCChip::clearIPI(uint64_t ipintr)
371{
372    int numcpus = tsunami->intrctrl->cpu->system->execContexts.size();
373    assert(numcpus <= Tsunami::Max_CPUs);
374
375    if (ipintr) {
376        for (int cpunum=0; cpunum < numcpus; cpunum++) {
377            // Check each cpu bit
378            uint64_t cpumask = ULL(1) << cpunum;
379            if (ipintr & cpumask) {
380                // Check if there is a pending ipi
381                if (ipint & cpumask) {
382                    ipint &= ~cpumask;
383                    tsunami->intrctrl->clear(cpunum, TheISA::INTLEVEL_IRQ3, 0);
384                    DPRINTF(IPI, "clear IPI IPI cpu=%d\n", cpunum);
385                }
386                else
387                    warn("clear IPI for CPU=%d, but NO IPI\n", cpunum);
388            }
389        }
390    }
391    else
392        panic("Big IPI Clear, but not processors indicated\n");
393}
394
395void
396TsunamiCChip::clearITI(uint64_t itintr)
397{
398    int numcpus = tsunami->intrctrl->cpu->system->execContexts.size();
399    assert(numcpus <= Tsunami::Max_CPUs);
400
401    if (itintr) {
402        for (int i=0; i < numcpus; i++) {
403            uint64_t cpumask = ULL(1) << i;
404            if (itintr & cpumask & itint) {
405                tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ2, 0);
406                itint &= ~cpumask;
407                DPRINTF(Tsunami, "clearing rtc interrupt to cpu=%d\n", i);
408            }
409        }
410    }
411    else
412        panic("Big ITI Clear, but not processors indicated\n");
413}
414
415void
416TsunamiCChip::reqIPI(uint64_t ipreq)
417{
418    int numcpus = tsunami->intrctrl->cpu->system->execContexts.size();
419    assert(numcpus <= Tsunami::Max_CPUs);
420
421    if (ipreq) {
422        for (int cpunum=0; cpunum < numcpus; cpunum++) {
423            // Check each cpu bit
424            uint64_t cpumask = ULL(1) << cpunum;
425            if (ipreq & cpumask) {
426                // Check if there is already an ipi (bits 8:11)
427                if (!(ipint & cpumask)) {
428                    ipint  |= cpumask;
429                    tsunami->intrctrl->post(cpunum, TheISA::INTLEVEL_IRQ3, 0);
430                    DPRINTF(IPI, "send IPI cpu=%d\n", cpunum);
431                }
432                else
433                    warn("post IPI for CPU=%d, but IPI already\n", cpunum);
434            }
435        }
436    }
437    else
438        panic("Big IPI Request, but not processors indicated\n");
439}
440
441
442void
443TsunamiCChip::postRTC()
444{
445    int size = tsunami->intrctrl->cpu->system->execContexts.size();
446    assert(size <= Tsunami::Max_CPUs);
447
448    for (int i = 0; i < size; i++) {
449        uint64_t cpumask = ULL(1) << i;
450       if (!(cpumask & itint)) {
451           itint |= cpumask;
452           tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ2, 0);
453           DPRINTF(Tsunami, "Posting RTC interrupt to cpu=%d", i);
454       }
455    }
456
457}
458
459void
460TsunamiCChip::postDRIR(uint32_t interrupt)
461{
462    uint64_t bitvector = ULL(1) << interrupt;
463    uint64_t size = tsunami->intrctrl->cpu->system->execContexts.size();
464    assert(size <= Tsunami::Max_CPUs);
465    drir |= bitvector;
466
467    for(int i=0; i < size; i++) {
468        dir[i] = dim[i] & drir;
469       if (dim[i] & bitvector) {
470              tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ1, interrupt);
471              DPRINTF(Tsunami, "posting dir interrupt to cpu %d,"
472                        "interrupt %d\n",i, interrupt);
473       }
474    }
475}
476
477void
478TsunamiCChip::clearDRIR(uint32_t interrupt)
479{
480    uint64_t bitvector = ULL(1) << interrupt;
481    uint64_t size = tsunami->intrctrl->cpu->system->execContexts.size();
482    assert(size <= Tsunami::Max_CPUs);
483
484    if (drir & bitvector)
485    {
486        drir &= ~bitvector;
487        for(int i=0; i < size; i++) {
488           if (dir[i] & bitvector) {
489               tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ1, interrupt);
490               DPRINTF(Tsunami, "clearing dir interrupt to cpu %d,"
491                    "interrupt %d\n",i, interrupt);
492
493           }
494           dir[i] = dim[i] & drir;
495        }
496    }
497    else
498        DPRINTF(Tsunami, "Spurrious clear? interrupt %d\n", interrupt);
499}
500
501
502void
503TsunamiCChip::serialize(std::ostream &os)
504{
505    SERIALIZE_ARRAY(dim, Tsunami::Max_CPUs);
506    SERIALIZE_ARRAY(dir, Tsunami::Max_CPUs);
507    SERIALIZE_SCALAR(ipint);
508    SERIALIZE_SCALAR(itint);
509    SERIALIZE_SCALAR(drir);
510}
511
512void
513TsunamiCChip::unserialize(Checkpoint *cp, const std::string &section)
514{
515    UNSERIALIZE_ARRAY(dim, Tsunami::Max_CPUs);
516    UNSERIALIZE_ARRAY(dir, Tsunami::Max_CPUs);
517    UNSERIALIZE_SCALAR(ipint);
518    UNSERIALIZE_SCALAR(itint);
519    UNSERIALIZE_SCALAR(drir);
520}
521
522BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
523
524    Param<Addr> pio_addr;
525    Param<Tick> pio_latency;
526    SimObjectParam<Platform *> platform;
527    SimObjectParam<System *> system;
528    SimObjectParam<Tsunami *> tsunami;
529
530END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
531
532BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
533
534    INIT_PARAM(pio_addr, "Device Address"),
535    INIT_PARAM(pio_latency, "Programmed IO latency"),
536    INIT_PARAM(platform, "platform"),
537    INIT_PARAM(system, "system object"),
538    INIT_PARAM(tsunami, "Tsunami")
539
540END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
541
542CREATE_SIM_OBJECT(TsunamiCChip)
543{
544    TsunamiCChip::Params *p = new TsunamiCChip::Params;
545    p->name = getInstanceName();
546    p->pio_addr = pio_addr;
547    p->pio_delay = pio_latency;
548    p->platform = platform;
549    p->system = system;
550    p->tsunami = tsunami;
551    return new TsunamiCChip(p);
552}
553
554REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip)
555