backdoor.cc revision 217
111752Snikos.nikoleris@arm.com/* 210705Sandreas.hansson@arm.com * Copyright (c) 2003 The Regents of The University of Michigan 310705Sandreas.hansson@arm.com * All rights reserved. 410705Sandreas.hansson@arm.com * 510705Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 610705Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 710705Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 810705Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 910705Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 1010705Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 1110705Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 1210705Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 1310705Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 1410705Sandreas.hansson@arm.com * this software without specific prior written permission. 1510705Sandreas.hansson@arm.com * 1610705Sandreas.hansson@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1710705Sandreas.hansson@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810705Sandreas.hansson@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1910705Sandreas.hansson@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010705Sandreas.hansson@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110705Sandreas.hansson@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210705Sandreas.hansson@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310705Sandreas.hansson@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410705Sandreas.hansson@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510705Sandreas.hansson@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610705Sandreas.hansson@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710705Sandreas.hansson@arm.com */ 2810705Sandreas.hansson@arm.com 2910705Sandreas.hansson@arm.com/* @file 3010705Sandreas.hansson@arm.com * System Console Definition 3110705Sandreas.hansson@arm.com */ 3210705Sandreas.hansson@arm.com 3310705Sandreas.hansson@arm.com#include <cstddef> 3410705Sandreas.hansson@arm.com#include <cstdio> 3510705Sandreas.hansson@arm.com#include <string> 3610705Sandreas.hansson@arm.com 3710705Sandreas.hansson@arm.com#include "base/inifile.hh" 3810705Sandreas.hansson@arm.com#include "base/str.hh" // for to_number() 3910705Sandreas.hansson@arm.com#include "base/trace.hh" 4010705Sandreas.hansson@arm.com#include "cpu/base_cpu.hh" 4110705Sandreas.hansson@arm.com#include "cpu/exec_context.hh" 4212564Sgabeblack@google.com#include "dev/alpha_console.hh" 4313774Sandreas.sandberg@arm.com#include "dev/console.hh" 4412564Sgabeblack@google.com#include "dev/simple_disk.hh" 4510705Sandreas.hansson@arm.com#include "dev/tlaser_clock.hh" 4611753Snikos.nikoleris@arm.com#include "mem/functional_mem/memory_control.hh" 4710705Sandreas.hansson@arm.com#include "sim/builder.hh" 4810705Sandreas.hansson@arm.com#include "sim/system.hh" 4910705Sandreas.hansson@arm.com 5010705Sandreas.hansson@arm.comusing namespace std; 5110705Sandreas.hansson@arm.com 5210705Sandreas.hansson@arm.comAlphaConsole::AlphaConsole(const string &name, SimConsole *cons, 5310705Sandreas.hansson@arm.com SimpleDisk *d, int size, System *system, 5410705Sandreas.hansson@arm.com BaseCPU *cpu, TlaserClock *clock, int num_cpus, 5510705Sandreas.hansson@arm.com Addr addr, Addr mask, MemoryController *mmu) 5610705Sandreas.hansson@arm.com : MmapDevice(name, addr, mask, mmu), disk(d), console(cons) 5710705Sandreas.hansson@arm.com{ 5810705Sandreas.hansson@arm.com consoleData = new uint8_t[size]; 5910705Sandreas.hansson@arm.com memset(consoleData, 0, size); 6010705Sandreas.hansson@arm.com 6110705Sandreas.hansson@arm.com alphaAccess->last_offset = size - 1; 6210705Sandreas.hansson@arm.com alphaAccess->kernStart = system->getKernelStart(); 6310705Sandreas.hansson@arm.com alphaAccess->kernEnd = system->getKernelEnd(); 6410705Sandreas.hansson@arm.com alphaAccess->entryPoint = system->getKernelEntry(); 6510705Sandreas.hansson@arm.com 6610705Sandreas.hansson@arm.com alphaAccess->version = ALPHA_ACCESS_VERSION; 6710705Sandreas.hansson@arm.com alphaAccess->numCPUs = num_cpus; 6810705Sandreas.hansson@arm.com alphaAccess->mem_size = system->physmem->getSize(); 6910705Sandreas.hansson@arm.com alphaAccess->cpuClock = cpu->getFreq() / 1000000; 7010705Sandreas.hansson@arm.com alphaAccess->intrClockFrequency = clock->frequency(); 7110705Sandreas.hansson@arm.com 7210705Sandreas.hansson@arm.com alphaAccess->diskUnit = 1; 7310705Sandreas.hansson@arm.com} 7410705Sandreas.hansson@arm.com 7510705Sandreas.hansson@arm.comFault 7610705Sandreas.hansson@arm.comAlphaConsole::read(MemReqPtr req, uint8_t *data) 7710705Sandreas.hansson@arm.com{ 7810705Sandreas.hansson@arm.com memset(data, 0, req->size); 7910705Sandreas.hansson@arm.com 8010705Sandreas.hansson@arm.com if (req->size == sizeof(uint32_t)) { 8110705Sandreas.hansson@arm.com Addr daddr = req->paddr & addr_mask; 8210705Sandreas.hansson@arm.com *(uint32_t *)data = *(uint32_t *)(consoleData + daddr); 8310705Sandreas.hansson@arm.com 8410705Sandreas.hansson@arm.com#if 0 8510705Sandreas.hansson@arm.com DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", 8610705Sandreas.hansson@arm.com daddr, *(uint32_t *)data); 8710705Sandreas.hansson@arm.com#endif 8810705Sandreas.hansson@arm.com } 8910705Sandreas.hansson@arm.com 9010705Sandreas.hansson@arm.com return No_Fault; 9110705Sandreas.hansson@arm.com} 9210705Sandreas.hansson@arm.com 9310705Sandreas.hansson@arm.comFault 9410705Sandreas.hansson@arm.comAlphaConsole::write(MemReqPtr req, const uint8_t *data) 9510705Sandreas.hansson@arm.com{ 9610705Sandreas.hansson@arm.com uint64_t val; 9710705Sandreas.hansson@arm.com 9810705Sandreas.hansson@arm.com switch (req->size) { 9910705Sandreas.hansson@arm.com case sizeof(uint32_t): 10010705Sandreas.hansson@arm.com val = *(uint32_t *)data; 10110705Sandreas.hansson@arm.com break; 10210705Sandreas.hansson@arm.com case sizeof(uint64_t): 10310705Sandreas.hansson@arm.com val = *(uint64_t *)data; 10411753Snikos.nikoleris@arm.com break; 10511753Snikos.nikoleris@arm.com default: 10610705Sandreas.hansson@arm.com return Machine_Check_Fault; 10710705Sandreas.hansson@arm.com } 10810705Sandreas.hansson@arm.com 10910705Sandreas.hansson@arm.com Addr paddr = req->paddr & addr_mask; 11010705Sandreas.hansson@arm.com 11110705Sandreas.hansson@arm.com if (paddr == offsetof(AlphaAccess, diskUnit)) { 11210705Sandreas.hansson@arm.com alphaAccess->diskUnit = val; 11310705Sandreas.hansson@arm.com return No_Fault; 11412564Sgabeblack@google.com } 11510705Sandreas.hansson@arm.com 11610705Sandreas.hansson@arm.com if (paddr == offsetof(AlphaAccess, diskCount)) { 11710705Sandreas.hansson@arm.com alphaAccess->diskCount = val; 11810705Sandreas.hansson@arm.com return No_Fault; 11911753Snikos.nikoleris@arm.com } 12011753Snikos.nikoleris@arm.com 12111753Snikos.nikoleris@arm.com if (paddr == offsetof(AlphaAccess, diskPAddr)) { 12211753Snikos.nikoleris@arm.com alphaAccess->diskPAddr = val; 12311753Snikos.nikoleris@arm.com return No_Fault; 12412564Sgabeblack@google.com } 12512564Sgabeblack@google.com 12611753Snikos.nikoleris@arm.com if (paddr == offsetof(AlphaAccess, diskBlock)) { 12711753Snikos.nikoleris@arm.com alphaAccess->diskBlock = val; 12811753Snikos.nikoleris@arm.com return No_Fault; 12911753Snikos.nikoleris@arm.com } 13011753Snikos.nikoleris@arm.com 13112564Sgabeblack@google.com if (paddr == offsetof(AlphaAccess, diskOperation)) { 13210705Sandreas.hansson@arm.com if (val == 0x13) 13310705Sandreas.hansson@arm.com disk->read(alphaAccess->diskPAddr, alphaAccess->diskBlock, 13411753Snikos.nikoleris@arm.com alphaAccess->diskCount); 13512564Sgabeblack@google.com else 13610705Sandreas.hansson@arm.com panic("Invalid disk operation!"); 13710705Sandreas.hansson@arm.com 13811753Snikos.nikoleris@arm.com return No_Fault; 13912564Sgabeblack@google.com } 14011753Snikos.nikoleris@arm.com 14111753Snikos.nikoleris@arm.com if (paddr == offsetof(AlphaAccess, outputChar)) { 14211753Snikos.nikoleris@arm.com console->out((char)(val & 0xff), false); 14312564Sgabeblack@google.com return No_Fault; 14411753Snikos.nikoleris@arm.com } 14511753Snikos.nikoleris@arm.com 14611753Snikos.nikoleris@arm.com if (paddr == offsetof(AlphaAccess, bootStrapImpure)) { 14711753Snikos.nikoleris@arm.com alphaAccess->bootStrapImpure = val; 14812564Sgabeblack@google.com return No_Fault; 14911753Snikos.nikoleris@arm.com } 15011753Snikos.nikoleris@arm.com 15111753Snikos.nikoleris@arm.com if (paddr == offsetof(AlphaAccess, bootStrapCPU)) { 15211753Snikos.nikoleris@arm.com warn("%d: Trying to launch another CPU!", curTick); 15312564Sgabeblack@google.com int cpu = val; 15411753Snikos.nikoleris@arm.com assert(cpu > 0 && "Must not access primary cpu"); 15511753Snikos.nikoleris@arm.com 15610705Sandreas.hansson@arm.com ExecContext *other_xc = req->xc->system->execContexts[cpu]; 15710705Sandreas.hansson@arm.com other_xc->regs.intRegFile[16] = cpu; 15810705Sandreas.hansson@arm.com other_xc->regs.ipr[TheISA::IPR_PALtemp16] = cpu; 15910705Sandreas.hansson@arm.com other_xc->regs.intRegFile[0] = cpu; 16010705Sandreas.hansson@arm.com other_xc->regs.intRegFile[30] = alphaAccess->bootStrapImpure; 16112564Sgabeblack@google.com other_xc->setStatus(ExecContext::Active); //Start the cpu 16210705Sandreas.hansson@arm.com return No_Fault; 16310705Sandreas.hansson@arm.com } 16410705Sandreas.hansson@arm.com 16510705Sandreas.hansson@arm.com return No_Fault; 16610705Sandreas.hansson@arm.com} 16710705Sandreas.hansson@arm.com 16810705Sandreas.hansson@arm.comvoid 16911053Sandreas.hansson@arm.comAlphaAccess::serialize(ostream &os) 17011722Ssophiane.senni@gmail.com{ 17111053Sandreas.hansson@arm.com SERIALIZE_MEMBER(last_offset); 17210705Sandreas.hansson@arm.com SERIALIZE_MEMBER(version); 17310705Sandreas.hansson@arm.com SERIALIZE_MEMBER(numCPUs); 17410705Sandreas.hansson@arm.com SERIALIZE_MEMBER(mem_size); 17510705Sandreas.hansson@arm.com SERIALIZE_MEMBER(cpuClock); 17610705Sandreas.hansson@arm.com SERIALIZE_MEMBER(intrClockFrequency); 17710705Sandreas.hansson@arm.com SERIALIZE_MEMBER(kernStart); 17810705Sandreas.hansson@arm.com SERIALIZE_MEMBER(kernEnd); 17910705Sandreas.hansson@arm.com SERIALIZE_MEMBER(entryPoint); 18010705Sandreas.hansson@arm.com SERIALIZE_MEMBER(diskUnit); 18110705Sandreas.hansson@arm.com SERIALIZE_MEMBER(diskCount); 18210705Sandreas.hansson@arm.com SERIALIZE_MEMBER(diskPAddr); 18310705Sandreas.hansson@arm.com SERIALIZE_MEMBER(diskBlock); 18410705Sandreas.hansson@arm.com SERIALIZE_MEMBER(diskOperation); 18510705Sandreas.hansson@arm.com SERIALIZE_MEMBER(outputChar); 18610705Sandreas.hansson@arm.com SERIALIZE_MEMBER(bootStrapImpure); 18710705Sandreas.hansson@arm.com SERIALIZE_MEMBER(bootStrapCPU); 18810705Sandreas.hansson@arm.com} 18910705Sandreas.hansson@arm.com 19010705Sandreas.hansson@arm.comvoid 19110705Sandreas.hansson@arm.comAlphaAccess::unserialize(IniFile &db, const std::string §ion) 19211722Ssophiane.senni@gmail.com{ 19311722Ssophiane.senni@gmail.com UNSERIALIZE_MEMBER(last_offset); 19410705Sandreas.hansson@arm.com UNSERIALIZE_MEMBER(version); 19510705Sandreas.hansson@arm.com UNSERIALIZE_MEMBER(numCPUs); 19610705Sandreas.hansson@arm.com UNSERIALIZE_MEMBER(mem_size); 19710705Sandreas.hansson@arm.com UNSERIALIZE_MEMBER(cpuClock); 19810705Sandreas.hansson@arm.com UNSERIALIZE_MEMBER(intrClockFrequency); 19910705Sandreas.hansson@arm.com UNSERIALIZE_MEMBER(kernStart); 20010705Sandreas.hansson@arm.com UNSERIALIZE_MEMBER(kernEnd); 20110705Sandreas.hansson@arm.com UNSERIALIZE_MEMBER(entryPoint); 20210705Sandreas.hansson@arm.com UNSERIALIZE_MEMBER(diskUnit); 20310705Sandreas.hansson@arm.com UNSERIALIZE_MEMBER(diskCount); 20410705Sandreas.hansson@arm.com UNSERIALIZE_MEMBER(diskPAddr); 20511752Snikos.nikoleris@arm.com UNSERIALIZE_MEMBER(diskBlock); 20610705Sandreas.hansson@arm.com UNSERIALIZE_MEMBER(diskOperation); 20711752Snikos.nikoleris@arm.com UNSERIALIZE_MEMBER(outputChar); 20810705Sandreas.hansson@arm.com UNSERIALIZE_MEMBER(bootStrapImpure); 20910705Sandreas.hansson@arm.com UNSERIALIZE_MEMBER(bootStrapCPU); 21010705Sandreas.hansson@arm.com} 21110705Sandreas.hansson@arm.com 21210705Sandreas.hansson@arm.comvoid 21310705Sandreas.hansson@arm.comAlphaConsole::serialize(ostream &os) 21410705Sandreas.hansson@arm.com{ 21510705Sandreas.hansson@arm.com alphaAccess->serialize(os); 21610705Sandreas.hansson@arm.com} 21710705Sandreas.hansson@arm.com 21810705Sandreas.hansson@arm.comvoid 21910705Sandreas.hansson@arm.comAlphaConsole::unserialize(IniFile &db, const std::string §ion) 22010705Sandreas.hansson@arm.com{ 22110705Sandreas.hansson@arm.com alphaAccess->unserialize(db, section); 22211837Swendy.elsasser@arm.com} 22310705Sandreas.hansson@arm.com 22410705Sandreas.hansson@arm.comBEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole) 22510705Sandreas.hansson@arm.com 22610705Sandreas.hansson@arm.com SimObjectParam<SimConsole *> sim_console; 22710705Sandreas.hansson@arm.com SimObjectParam<SimpleDisk *> disk; 22810705Sandreas.hansson@arm.com Param<int> size; 22910705Sandreas.hansson@arm.com Param<int> num_cpus; 23010705Sandreas.hansson@arm.com SimObjectParam<MemoryController *> mmu; 23110705Sandreas.hansson@arm.com Param<Addr> addr; 23210705Sandreas.hansson@arm.com Param<Addr> mask; 23310705Sandreas.hansson@arm.com SimObjectParam<System *> system; 23410705Sandreas.hansson@arm.com SimObjectParam<BaseCPU *> cpu; 23510705Sandreas.hansson@arm.com SimObjectParam<TlaserClock *> clock; 23610705Sandreas.hansson@arm.com 23710705Sandreas.hansson@arm.comEND_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole) 23810705Sandreas.hansson@arm.com 23910705Sandreas.hansson@arm.comBEGIN_INIT_SIM_OBJECT_PARAMS(AlphaConsole) 24010705Sandreas.hansson@arm.com 24110705Sandreas.hansson@arm.com INIT_PARAM(sim_console, "The Simulator Console"), 24210705Sandreas.hansson@arm.com INIT_PARAM(disk, "Simple Disk"), 24310705Sandreas.hansson@arm.com INIT_PARAM_DFLT(size, "AlphaConsole size", sizeof(AlphaAccess)), 24410705Sandreas.hansson@arm.com INIT_PARAM_DFLT(num_cpus, "Number of CPU's", 1), 24510705Sandreas.hansson@arm.com INIT_PARAM(mmu, "Memory Controller"), 24610705Sandreas.hansson@arm.com INIT_PARAM(addr, "Device Address"), 24710705Sandreas.hansson@arm.com INIT_PARAM(mask, "Address Mask"), 24810705Sandreas.hansson@arm.com INIT_PARAM(system, "system object"), 24910705Sandreas.hansson@arm.com INIT_PARAM(cpu, "Processor"), 25013731Sandreas.sandberg@arm.com INIT_PARAM(clock, "Turbolaser Clock") 25110705Sandreas.hansson@arm.com 25213731Sandreas.sandberg@arm.comEND_INIT_SIM_OBJECT_PARAMS(AlphaConsole) 25310705Sandreas.hansson@arm.com 25410705Sandreas.hansson@arm.comCREATE_SIM_OBJECT(AlphaConsole) 25510705Sandreas.hansson@arm.com{ 25610705Sandreas.hansson@arm.com return new AlphaConsole(getInstanceName(), sim_console, 25710705Sandreas.hansson@arm.com disk, size, system, 25810705Sandreas.hansson@arm.com cpu, clock, num_cpus, 25910705Sandreas.hansson@arm.com addr, mask, mmu); 26010720Sandreas.hansson@arm.com} 26110705Sandreas.hansson@arm.com 26210705Sandreas.hansson@arm.comREGISTER_SIM_OBJECT("AlphaConsole", AlphaConsole) 26310705Sandreas.hansson@arm.com