backdoor.cc revision 217 
1/*
2 * Copyright (c) 2003 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/* @file
30 * System Console Definition
31 */
32
33#include <cstddef>
34#include <cstdio>
35#include <string>
36
37#include "base/inifile.hh"
38#include "base/str.hh"	// for to_number()
39#include "base/trace.hh"
40#include "cpu/base_cpu.hh"
41#include "cpu/exec_context.hh"
42#include "dev/alpha_console.hh"
43#include "dev/console.hh"
44#include "dev/simple_disk.hh"
45#include "dev/tlaser_clock.hh"
46#include "mem/functional_mem/memory_control.hh"
47#include "sim/builder.hh"
48#include "sim/system.hh"
49
50using namespace std;
51
52AlphaConsole::AlphaConsole(const string &name, SimConsole *cons,
53                           SimpleDisk *d, int size, System *system,
54                           BaseCPU *cpu, TlaserClock *clock, int num_cpus,
55                           Addr addr, Addr mask, MemoryController *mmu)
56    : MmapDevice(name, addr, mask, mmu), disk(d), console(cons)
57{
58    consoleData = new uint8_t[size];
59    memset(consoleData, 0, size);
60
61    alphaAccess->last_offset = size - 1;
62    alphaAccess->kernStart = system->getKernelStart();
63    alphaAccess->kernEnd = system->getKernelEnd();
64    alphaAccess->entryPoint = system->getKernelEntry();
65
66    alphaAccess->version = ALPHA_ACCESS_VERSION;
67    alphaAccess->numCPUs = num_cpus;
68    alphaAccess->mem_size = system->physmem->getSize();
69    alphaAccess->cpuClock = cpu->getFreq() / 1000000;
70    alphaAccess->intrClockFrequency = clock->frequency();
71
72    alphaAccess->diskUnit = 1;
73}
74
75Fault
76AlphaConsole::read(MemReqPtr req, uint8_t *data)
77{
78    memset(data, 0, req->size);
79
80    if (req->size == sizeof(uint32_t)) {
81        Addr daddr = req->paddr & addr_mask;
82        *(uint32_t *)data = *(uint32_t *)(consoleData + daddr);
83
84#if 0
85        DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n",
86                daddr, *(uint32_t *)data);
87#endif
88    }
89
90    return No_Fault;
91}
92
93Fault
94AlphaConsole::write(MemReqPtr req, const uint8_t *data)
95{
96    uint64_t val;
97
98    switch (req->size) {
99      case sizeof(uint32_t):
100        val = *(uint32_t *)data;
101        break;
102      case sizeof(uint64_t):
103        val = *(uint64_t *)data;
104        break;
105      default:
106        return Machine_Check_Fault;
107    }
108
109    Addr paddr = req->paddr & addr_mask;
110
111    if (paddr == offsetof(AlphaAccess, diskUnit)) {
112        alphaAccess->diskUnit = val;
113        return No_Fault;
114    }
115
116    if (paddr == offsetof(AlphaAccess, diskCount)) {
117        alphaAccess->diskCount = val;
118        return No_Fault;
119    }
120
121    if (paddr == offsetof(AlphaAccess, diskPAddr)) {
122        alphaAccess->diskPAddr = val;
123        return No_Fault;
124    }
125
126    if (paddr == offsetof(AlphaAccess, diskBlock)) {
127        alphaAccess->diskBlock = val;
128        return No_Fault;
129    }
130
131    if (paddr == offsetof(AlphaAccess, diskOperation)) {
132        if (val == 0x13)
133            disk->read(alphaAccess->diskPAddr, alphaAccess->diskBlock,
134                       alphaAccess->diskCount);
135        else
136            panic("Invalid disk operation!");
137
138        return No_Fault;
139    }
140
141    if (paddr == offsetof(AlphaAccess, outputChar)) {
142        console->out((char)(val & 0xff), false);
143        return No_Fault;
144    }
145
146    if (paddr == offsetof(AlphaAccess, bootStrapImpure)) {
147        alphaAccess->bootStrapImpure = val;
148        return No_Fault;
149    }
150
151    if (paddr == offsetof(AlphaAccess, bootStrapCPU)) {
152        warn("%d: Trying to launch another CPU!", curTick);
153        int cpu = val;
154        assert(cpu > 0 && "Must not access primary cpu");
155
156        ExecContext *other_xc = req->xc->system->execContexts[cpu];
157        other_xc->regs.intRegFile[16] = cpu;
158        other_xc->regs.ipr[TheISA::IPR_PALtemp16] = cpu;
159        other_xc->regs.intRegFile[0] = cpu;
160        other_xc->regs.intRegFile[30] = alphaAccess->bootStrapImpure;
161        other_xc->setStatus(ExecContext::Active); //Start the cpu
162        return No_Fault;
163    }
164
165    return No_Fault;
166}
167
168void
169AlphaAccess::serialize(ostream &os)
170{
171    SERIALIZE_MEMBER(last_offset);
172    SERIALIZE_MEMBER(version);
173    SERIALIZE_MEMBER(numCPUs);
174    SERIALIZE_MEMBER(mem_size);
175    SERIALIZE_MEMBER(cpuClock);
176    SERIALIZE_MEMBER(intrClockFrequency);
177    SERIALIZE_MEMBER(kernStart);
178    SERIALIZE_MEMBER(kernEnd);
179    SERIALIZE_MEMBER(entryPoint);
180    SERIALIZE_MEMBER(diskUnit);
181    SERIALIZE_MEMBER(diskCount);
182    SERIALIZE_MEMBER(diskPAddr);
183    SERIALIZE_MEMBER(diskBlock);
184    SERIALIZE_MEMBER(diskOperation);
185    SERIALIZE_MEMBER(outputChar);
186    SERIALIZE_MEMBER(bootStrapImpure);
187    SERIALIZE_MEMBER(bootStrapCPU);
188}
189
190void
191AlphaAccess::unserialize(IniFile &db, const std::string &section)
192{
193    UNSERIALIZE_MEMBER(last_offset);
194    UNSERIALIZE_MEMBER(version);
195    UNSERIALIZE_MEMBER(numCPUs);
196    UNSERIALIZE_MEMBER(mem_size);
197    UNSERIALIZE_MEMBER(cpuClock);
198    UNSERIALIZE_MEMBER(intrClockFrequency);
199    UNSERIALIZE_MEMBER(kernStart);
200    UNSERIALIZE_MEMBER(kernEnd);
201    UNSERIALIZE_MEMBER(entryPoint);
202    UNSERIALIZE_MEMBER(diskUnit);
203    UNSERIALIZE_MEMBER(diskCount);
204    UNSERIALIZE_MEMBER(diskPAddr);
205    UNSERIALIZE_MEMBER(diskBlock);
206    UNSERIALIZE_MEMBER(diskOperation);
207    UNSERIALIZE_MEMBER(outputChar);
208    UNSERIALIZE_MEMBER(bootStrapImpure);
209    UNSERIALIZE_MEMBER(bootStrapCPU);
210}
211
212void
213AlphaConsole::serialize(ostream &os)
214{
215    alphaAccess->serialize(os);
216}
217
218void
219AlphaConsole::unserialize(IniFile &db, const std::string &section)
220{
221    alphaAccess->unserialize(db, section);
222}
223
224BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
225
226    SimObjectParam<SimConsole *> sim_console;
227    SimObjectParam<SimpleDisk *> disk;
228    Param<int> size;
229    Param<int> num_cpus;
230    SimObjectParam<MemoryController *> mmu;
231    Param<Addr> addr;
232    Param<Addr> mask;
233    SimObjectParam<System *> system;
234    SimObjectParam<BaseCPU *> cpu;
235    SimObjectParam<TlaserClock *> clock;
236
237END_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
238
239BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
240
241    INIT_PARAM(sim_console, "The Simulator Console"),
242    INIT_PARAM(disk, "Simple Disk"),
243    INIT_PARAM_DFLT(size, "AlphaConsole size", sizeof(AlphaAccess)),
244    INIT_PARAM_DFLT(num_cpus, "Number of CPU's", 1),
245    INIT_PARAM(mmu, "Memory Controller"),
246    INIT_PARAM(addr, "Device Address"),
247    INIT_PARAM(mask, "Address Mask"),
248    INIT_PARAM(system, "system object"),
249    INIT_PARAM(cpu, "Processor"),
250    INIT_PARAM(clock, "Turbolaser Clock")
251
252END_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
253
254CREATE_SIM_OBJECT(AlphaConsole)
255{
256    return  new AlphaConsole(getInstanceName(), sim_console,
257                             disk, size, system,
258                             cpu, clock, num_cpus,
259                             addr, mask, mmu);
260}
261
262REGISTER_SIM_OBJECT("AlphaConsole", AlphaConsole)
263