timing.hh revision 6023
110037SARM gem5 Developers/* 210037SARM gem5 Developers * Copyright (c) 2002-2005 The Regents of The University of Michigan 312280Sgiacomo.travaglini@arm.com * All rights reserved. 410037SARM gem5 Developers * 510037SARM gem5 Developers * Redistribution and use in source and binary forms, with or without 610037SARM gem5 Developers * modification, are permitted provided that the following conditions are 710037SARM gem5 Developers * met: redistributions of source code must retain the above copyright 810037SARM gem5 Developers * notice, this list of conditions and the following disclaimer; 910037SARM gem5 Developers * redistributions in binary form must reproduce the above copyright 1010037SARM gem5 Developers * notice, this list of conditions and the following disclaimer in the 1110037SARM gem5 Developers * documentation and/or other materials provided with the distribution; 1210037SARM gem5 Developers * neither the name of the copyright holders nor the names of its 1310037SARM gem5 Developers * contributors may be used to endorse or promote products derived from 1410037SARM gem5 Developers * this software without specific prior written permission. 1510037SARM gem5 Developers * 1610037SARM gem5 Developers * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1710037SARM gem5 Developers * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810037SARM gem5 Developers * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1910037SARM gem5 Developers * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010037SARM gem5 Developers * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110037SARM gem5 Developers * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210037SARM gem5 Developers * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310037SARM gem5 Developers * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410037SARM gem5 Developers * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510037SARM gem5 Developers * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610037SARM gem5 Developers * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710037SARM gem5 Developers * 2810037SARM gem5 Developers * Authors: Steve Reinhardt 2910037SARM gem5 Developers */ 3010037SARM gem5 Developers 3110037SARM gem5 Developers#ifndef __CPU_SIMPLE_TIMING_HH__ 3210037SARM gem5 Developers#define __CPU_SIMPLE_TIMING_HH__ 3310037SARM gem5 Developers 3410037SARM gem5 Developers#include "cpu/simple/base.hh" 3510037SARM gem5 Developers 3610037SARM gem5 Developers#include "params/TimingSimpleCPU.hh" 3710037SARM gem5 Developers 3810037SARM gem5 Developersclass TimingSimpleCPU : public BaseSimpleCPU 3910037SARM gem5 Developers{ 4010037SARM gem5 Developers public: 4110037SARM gem5 Developers 4210037SARM gem5 Developers TimingSimpleCPU(TimingSimpleCPUParams * params); 4310037SARM gem5 Developers virtual ~TimingSimpleCPU(); 4410037SARM gem5 Developers 4510037SARM gem5 Developers virtual void init(); 4610037SARM gem5 Developers 4710037SARM gem5 Developers public: 4810037SARM gem5 Developers Event *drainEvent; 4912236Sgabeblack@google.com 5010037SARM gem5 Developers private: 5110037SARM gem5 Developers 5210037SARM gem5 Developers /* 5310037SARM gem5 Developers * If an access needs to be broken into fragments, currently at most two, 5410184SCurtis.Dunham@arm.com * the the following two classes are used as the sender state of the 5510037SARM gem5 Developers * packets so the CPU can keep track of everything. In the main packet 5610037SARM gem5 Developers * sender state, there's an array with a spot for each fragment. If a 5710037SARM gem5 Developers * fragment has already been accepted by the CPU, aka isn't waiting for 5810037SARM gem5 Developers * a retry, it's pointer is NULL. After each fragment has successfully 5910037SARM gem5 Developers * been processed, the "outstanding" counter is decremented. Once the 6010037SARM gem5 Developers * count is zero, the entire larger access is complete. 6110037SARM gem5 Developers */ 6210037SARM gem5 Developers class SplitMainSenderState : public Packet::SenderState 6310037SARM gem5 Developers { 6410037SARM gem5 Developers public: 6510037SARM gem5 Developers int outstanding; 6610037SARM gem5 Developers PacketPtr fragments[2]; 6710037SARM gem5 Developers 6810037SARM gem5 Developers int 6910037SARM gem5 Developers getPendingFragment() 7010037SARM gem5 Developers { 7110037SARM gem5 Developers if (fragments[0]) { 7210037SARM gem5 Developers return 0; 7310037SARM gem5 Developers } else if (fragments[1]) { 7410037SARM gem5 Developers return 1; 7512236Sgabeblack@google.com } else { 7610037SARM gem5 Developers return -1; 7710037SARM gem5 Developers } 7810037SARM gem5 Developers } 7910037SARM gem5 Developers }; 8010184SCurtis.Dunham@arm.com 8110037SARM gem5 Developers class SplitFragmentSenderState : public Packet::SenderState 8210037SARM gem5 Developers { 8310037SARM gem5 Developers public: 8410037SARM gem5 Developers SplitFragmentSenderState(PacketPtr _bigPkt, int _index) : 8510037SARM gem5 Developers bigPkt(_bigPkt), index(_index) 8610037SARM gem5 Developers {} 8710037SARM gem5 Developers PacketPtr bigPkt; 8810037SARM gem5 Developers int index; 8910037SARM gem5 Developers 9010037SARM gem5 Developers void 9110037SARM gem5 Developers clearFromParent() 9212280Sgiacomo.travaglini@arm.com { 9312280Sgiacomo.travaglini@arm.com SplitMainSenderState * main_send_state = 9412280Sgiacomo.travaglini@arm.com dynamic_cast<SplitMainSenderState *>(bigPkt->senderState); 9512280Sgiacomo.travaglini@arm.com main_send_state->fragments[index] = NULL; 9612280Sgiacomo.travaglini@arm.com } 9712280Sgiacomo.travaglini@arm.com }; 9812280Sgiacomo.travaglini@arm.com 9912280Sgiacomo.travaglini@arm.com class FetchTranslation : public BaseTLB::Translation 10012280Sgiacomo.travaglini@arm.com { 10112280Sgiacomo.travaglini@arm.com protected: 10212280Sgiacomo.travaglini@arm.com TimingSimpleCPU *cpu; 10312280Sgiacomo.travaglini@arm.com 10412280Sgiacomo.travaglini@arm.com public: 10512280Sgiacomo.travaglini@arm.com FetchTranslation(TimingSimpleCPU *_cpu) 10612280Sgiacomo.travaglini@arm.com : cpu(_cpu) 10712280Sgiacomo.travaglini@arm.com {} 10812280Sgiacomo.travaglini@arm.com 10912280Sgiacomo.travaglini@arm.com void 11012280Sgiacomo.travaglini@arm.com finish(Fault fault, RequestPtr req, ThreadContext *tc, 11112280Sgiacomo.travaglini@arm.com BaseTLB::Mode mode) 11212280Sgiacomo.travaglini@arm.com { 11312280Sgiacomo.travaglini@arm.com cpu->sendFetch(fault, req, tc); 11412280Sgiacomo.travaglini@arm.com } 11512280Sgiacomo.travaglini@arm.com }; 11612280Sgiacomo.travaglini@arm.com FetchTranslation fetchTranslation; 11712280Sgiacomo.travaglini@arm.com 11812280Sgiacomo.travaglini@arm.com class DataTranslation : public BaseTLB::Translation 11912280Sgiacomo.travaglini@arm.com { 12012280Sgiacomo.travaglini@arm.com protected: 12112280Sgiacomo.travaglini@arm.com TimingSimpleCPU *cpu; 12212280Sgiacomo.travaglini@arm.com uint8_t *data; 12312280Sgiacomo.travaglini@arm.com uint64_t *res; 12412280Sgiacomo.travaglini@arm.com BaseTLB::Mode mode; 12512280Sgiacomo.travaglini@arm.com 12612280Sgiacomo.travaglini@arm.com public: 12712280Sgiacomo.travaglini@arm.com DataTranslation(TimingSimpleCPU *_cpu, 12812280Sgiacomo.travaglini@arm.com uint8_t *_data, uint64_t *_res, BaseTLB::Mode _mode) 12912280Sgiacomo.travaglini@arm.com : cpu(_cpu), data(_data), res(_res), mode(_mode) 13012280Sgiacomo.travaglini@arm.com { 13112280Sgiacomo.travaglini@arm.com assert(mode == BaseTLB::Read || mode == BaseTLB::Write); 13212280Sgiacomo.travaglini@arm.com } 13312280Sgiacomo.travaglini@arm.com 13412280Sgiacomo.travaglini@arm.com void 13512280Sgiacomo.travaglini@arm.com finish(Fault fault, RequestPtr req, ThreadContext *tc, 13612280Sgiacomo.travaglini@arm.com BaseTLB::Mode mode) 13712280Sgiacomo.travaglini@arm.com { 13812280Sgiacomo.travaglini@arm.com assert(mode == this->mode); 139 cpu->sendData(fault, req, data, res, mode == BaseTLB::Read); 140 delete this; 141 } 142 }; 143 144 class SplitDataTranslation : public BaseTLB::Translation 145 { 146 public: 147 struct WholeTranslationState 148 { 149 public: 150 int outstanding; 151 RequestPtr requests[2]; 152 RequestPtr mainReq; 153 Fault faults[2]; 154 uint8_t *data; 155 BaseTLB::Mode mode; 156 157 WholeTranslationState(RequestPtr req1, RequestPtr req2, 158 RequestPtr main, uint8_t *data, BaseTLB::Mode mode) 159 { 160 assert(mode == BaseTLB::Read || mode == BaseTLB::Write); 161 162 outstanding = 2; 163 requests[0] = req1; 164 requests[1] = req2; 165 mainReq = main; 166 faults[0] = faults[1] = NoFault; 167 this->data = data; 168 this->mode = mode; 169 } 170 }; 171 172 TimingSimpleCPU *cpu; 173 int index; 174 WholeTranslationState *state; 175 176 SplitDataTranslation(TimingSimpleCPU *_cpu, int _index, 177 WholeTranslationState *_state) 178 : cpu(_cpu), index(_index), state(_state) 179 {} 180 181 void 182 finish(Fault fault, RequestPtr req, ThreadContext *tc, 183 BaseTLB::Mode mode) 184 { 185 assert(state); 186 assert(state->outstanding); 187 state->faults[index] = fault; 188 if (--state->outstanding == 0) { 189 cpu->sendSplitData(state->faults[0], 190 state->faults[1], 191 state->requests[0], 192 state->requests[1], 193 state->mainReq, 194 state->data, 195 state->mode == BaseTLB::Read); 196 delete state; 197 } 198 delete this; 199 } 200 }; 201 202 void sendData(Fault fault, RequestPtr req, 203 uint8_t *data, uint64_t *res, bool read); 204 void sendSplitData(Fault fault1, Fault fault2, 205 RequestPtr req1, RequestPtr req2, RequestPtr req, 206 uint8_t *data, bool read); 207 208 void translationFault(Fault fault); 209 210 void buildPacket(PacketPtr &pkt, RequestPtr req, bool read); 211 void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 212 RequestPtr req1, RequestPtr req2, RequestPtr req, 213 uint8_t *data, bool read); 214 215 bool handleReadPacket(PacketPtr pkt); 216 // This function always implicitly uses dcache_pkt. 217 bool handleWritePacket(); 218 219 class CpuPort : public Port 220 { 221 protected: 222 TimingSimpleCPU *cpu; 223 Tick lat; 224 225 public: 226 227 CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat) 228 : Port(_name, _cpu), cpu(_cpu), lat(_lat) 229 { } 230 231 bool snoopRangeSent; 232 233 protected: 234 235 virtual Tick recvAtomic(PacketPtr pkt); 236 237 virtual void recvFunctional(PacketPtr pkt); 238 239 virtual void recvStatusChange(Status status); 240 241 virtual void getDeviceAddressRanges(AddrRangeList &resp, 242 bool &snoop) 243 { resp.clear(); snoop = false; } 244 245 struct TickEvent : public Event 246 { 247 PacketPtr pkt; 248 TimingSimpleCPU *cpu; 249 250 TickEvent(TimingSimpleCPU *_cpu) : cpu(_cpu) {} 251 const char *description() const { return "Timing CPU tick"; } 252 void schedule(PacketPtr _pkt, Tick t); 253 }; 254 255 }; 256 257 class IcachePort : public CpuPort 258 { 259 public: 260 261 IcachePort(TimingSimpleCPU *_cpu, Tick _lat) 262 : CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu) 263 { } 264 265 protected: 266 267 virtual bool recvTiming(PacketPtr pkt); 268 269 virtual void recvRetry(); 270 271 struct ITickEvent : public TickEvent 272 { 273 274 ITickEvent(TimingSimpleCPU *_cpu) 275 : TickEvent(_cpu) {} 276 void process(); 277 const char *description() const { return "Timing CPU icache tick"; } 278 }; 279 280 ITickEvent tickEvent; 281 282 }; 283 284 class DcachePort : public CpuPort 285 { 286 public: 287 288 DcachePort(TimingSimpleCPU *_cpu, Tick _lat) 289 : CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu) 290 { } 291 292 virtual void setPeer(Port *port); 293 294 protected: 295 296 virtual bool recvTiming(PacketPtr pkt); 297 298 virtual void recvRetry(); 299 300 struct DTickEvent : public TickEvent 301 { 302 DTickEvent(TimingSimpleCPU *_cpu) 303 : TickEvent(_cpu) {} 304 void process(); 305 const char *description() const { return "Timing CPU dcache tick"; } 306 }; 307 308 DTickEvent tickEvent; 309 310 }; 311 312 IcachePort icachePort; 313 DcachePort dcachePort; 314 315 PacketPtr ifetch_pkt; 316 PacketPtr dcache_pkt; 317 318 Tick previousTick; 319 320 public: 321 322 virtual Port *getPort(const std::string &if_name, int idx = -1); 323 324 virtual void serialize(std::ostream &os); 325 virtual void unserialize(Checkpoint *cp, const std::string §ion); 326 327 virtual unsigned int drain(Event *drain_event); 328 virtual void resume(); 329 330 void switchOut(); 331 void takeOverFrom(BaseCPU *oldCPU); 332 333 virtual void activateContext(int thread_num, int delay); 334 virtual void suspendContext(int thread_num); 335 336 template <class T> 337 Fault read(Addr addr, T &data, unsigned flags); 338 339 template <class T> 340 Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 341 342 void fetch(); 343 void sendFetch(Fault fault, RequestPtr req, ThreadContext *tc); 344 void completeIfetch(PacketPtr ); 345 void completeDataAccess(PacketPtr pkt); 346 void advanceInst(Fault fault); 347 348 /** 349 * Print state of address in memory system via PrintReq (for 350 * debugging). 351 */ 352 void printAddr(Addr a); 353 354 private: 355 356 typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent; 357 FetchEvent fetchEvent; 358 359 struct IprEvent : Event { 360 Packet *pkt; 361 TimingSimpleCPU *cpu; 362 IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t); 363 virtual void process(); 364 virtual const char *description() const; 365 }; 366 367 void completeDrain(); 368}; 369 370#endif // __CPU_SIMPLE_TIMING_HH__ 371