timing.hh revision 6023
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 312623SN/A#ifndef __CPU_SIMPLE_TIMING_HH__ 322623SN/A#define __CPU_SIMPLE_TIMING_HH__ 332623SN/A 342623SN/A#include "cpu/simple/base.hh" 352623SN/A 365529Snate@binkert.org#include "params/TimingSimpleCPU.hh" 375529Snate@binkert.org 382623SN/Aclass TimingSimpleCPU : public BaseSimpleCPU 392623SN/A{ 402623SN/A public: 412623SN/A 425529Snate@binkert.org TimingSimpleCPU(TimingSimpleCPUParams * params); 432623SN/A virtual ~TimingSimpleCPU(); 442623SN/A 452623SN/A virtual void init(); 462623SN/A 472623SN/A public: 482839Sktlim@umich.edu Event *drainEvent; 492798Sktlim@umich.edu 502623SN/A private: 512623SN/A 525728Sgblack@eecs.umich.edu /* 535728Sgblack@eecs.umich.edu * If an access needs to be broken into fragments, currently at most two, 545728Sgblack@eecs.umich.edu * the the following two classes are used as the sender state of the 555728Sgblack@eecs.umich.edu * packets so the CPU can keep track of everything. In the main packet 565728Sgblack@eecs.umich.edu * sender state, there's an array with a spot for each fragment. If a 575728Sgblack@eecs.umich.edu * fragment has already been accepted by the CPU, aka isn't waiting for 585728Sgblack@eecs.umich.edu * a retry, it's pointer is NULL. After each fragment has successfully 595728Sgblack@eecs.umich.edu * been processed, the "outstanding" counter is decremented. Once the 605728Sgblack@eecs.umich.edu * count is zero, the entire larger access is complete. 615728Sgblack@eecs.umich.edu */ 625728Sgblack@eecs.umich.edu class SplitMainSenderState : public Packet::SenderState 635728Sgblack@eecs.umich.edu { 645728Sgblack@eecs.umich.edu public: 655728Sgblack@eecs.umich.edu int outstanding; 665728Sgblack@eecs.umich.edu PacketPtr fragments[2]; 675728Sgblack@eecs.umich.edu 685728Sgblack@eecs.umich.edu int 695728Sgblack@eecs.umich.edu getPendingFragment() 705728Sgblack@eecs.umich.edu { 715728Sgblack@eecs.umich.edu if (fragments[0]) { 725728Sgblack@eecs.umich.edu return 0; 735728Sgblack@eecs.umich.edu } else if (fragments[1]) { 745728Sgblack@eecs.umich.edu return 1; 755728Sgblack@eecs.umich.edu } else { 765728Sgblack@eecs.umich.edu return -1; 775728Sgblack@eecs.umich.edu } 785728Sgblack@eecs.umich.edu } 795728Sgblack@eecs.umich.edu }; 805728Sgblack@eecs.umich.edu 815728Sgblack@eecs.umich.edu class SplitFragmentSenderState : public Packet::SenderState 825728Sgblack@eecs.umich.edu { 835728Sgblack@eecs.umich.edu public: 845728Sgblack@eecs.umich.edu SplitFragmentSenderState(PacketPtr _bigPkt, int _index) : 855728Sgblack@eecs.umich.edu bigPkt(_bigPkt), index(_index) 865728Sgblack@eecs.umich.edu {} 875728Sgblack@eecs.umich.edu PacketPtr bigPkt; 885728Sgblack@eecs.umich.edu int index; 895728Sgblack@eecs.umich.edu 905728Sgblack@eecs.umich.edu void 915728Sgblack@eecs.umich.edu clearFromParent() 925728Sgblack@eecs.umich.edu { 935728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 945728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(bigPkt->senderState); 955728Sgblack@eecs.umich.edu main_send_state->fragments[index] = NULL; 965728Sgblack@eecs.umich.edu } 975728Sgblack@eecs.umich.edu }; 985728Sgblack@eecs.umich.edu 995894Sgblack@eecs.umich.edu class FetchTranslation : public BaseTLB::Translation 1005894Sgblack@eecs.umich.edu { 1015894Sgblack@eecs.umich.edu protected: 1025894Sgblack@eecs.umich.edu TimingSimpleCPU *cpu; 1035894Sgblack@eecs.umich.edu 1045894Sgblack@eecs.umich.edu public: 1056023Snate@binkert.org FetchTranslation(TimingSimpleCPU *_cpu) 1066023Snate@binkert.org : cpu(_cpu) 1075894Sgblack@eecs.umich.edu {} 1085894Sgblack@eecs.umich.edu 1096023Snate@binkert.org void 1106023Snate@binkert.org finish(Fault fault, RequestPtr req, ThreadContext *tc, 1116023Snate@binkert.org BaseTLB::Mode mode) 1125894Sgblack@eecs.umich.edu { 1135894Sgblack@eecs.umich.edu cpu->sendFetch(fault, req, tc); 1145894Sgblack@eecs.umich.edu } 1155894Sgblack@eecs.umich.edu }; 1165894Sgblack@eecs.umich.edu FetchTranslation fetchTranslation; 1175894Sgblack@eecs.umich.edu 1185894Sgblack@eecs.umich.edu class DataTranslation : public BaseTLB::Translation 1195894Sgblack@eecs.umich.edu { 1205894Sgblack@eecs.umich.edu protected: 1215894Sgblack@eecs.umich.edu TimingSimpleCPU *cpu; 1225894Sgblack@eecs.umich.edu uint8_t *data; 1235894Sgblack@eecs.umich.edu uint64_t *res; 1246023Snate@binkert.org BaseTLB::Mode mode; 1255894Sgblack@eecs.umich.edu 1265894Sgblack@eecs.umich.edu public: 1275894Sgblack@eecs.umich.edu DataTranslation(TimingSimpleCPU *_cpu, 1286023Snate@binkert.org uint8_t *_data, uint64_t *_res, BaseTLB::Mode _mode) 1296023Snate@binkert.org : cpu(_cpu), data(_data), res(_res), mode(_mode) 1306023Snate@binkert.org { 1316023Snate@binkert.org assert(mode == BaseTLB::Read || mode == BaseTLB::Write); 1326023Snate@binkert.org } 1335894Sgblack@eecs.umich.edu 1345894Sgblack@eecs.umich.edu void 1356023Snate@binkert.org finish(Fault fault, RequestPtr req, ThreadContext *tc, 1366023Snate@binkert.org BaseTLB::Mode mode) 1375894Sgblack@eecs.umich.edu { 1386023Snate@binkert.org assert(mode == this->mode); 1396023Snate@binkert.org cpu->sendData(fault, req, data, res, mode == BaseTLB::Read); 1405894Sgblack@eecs.umich.edu delete this; 1415894Sgblack@eecs.umich.edu } 1425894Sgblack@eecs.umich.edu }; 1435894Sgblack@eecs.umich.edu 1445894Sgblack@eecs.umich.edu class SplitDataTranslation : public BaseTLB::Translation 1455894Sgblack@eecs.umich.edu { 1465894Sgblack@eecs.umich.edu public: 1475894Sgblack@eecs.umich.edu struct WholeTranslationState 1485894Sgblack@eecs.umich.edu { 1495894Sgblack@eecs.umich.edu public: 1505894Sgblack@eecs.umich.edu int outstanding; 1515894Sgblack@eecs.umich.edu RequestPtr requests[2]; 1525894Sgblack@eecs.umich.edu RequestPtr mainReq; 1535894Sgblack@eecs.umich.edu Fault faults[2]; 1545894Sgblack@eecs.umich.edu uint8_t *data; 1556023Snate@binkert.org BaseTLB::Mode mode; 1565894Sgblack@eecs.umich.edu 1575894Sgblack@eecs.umich.edu WholeTranslationState(RequestPtr req1, RequestPtr req2, 1586023Snate@binkert.org RequestPtr main, uint8_t *data, BaseTLB::Mode mode) 1595894Sgblack@eecs.umich.edu { 1606023Snate@binkert.org assert(mode == BaseTLB::Read || mode == BaseTLB::Write); 1616023Snate@binkert.org 1625894Sgblack@eecs.umich.edu outstanding = 2; 1635894Sgblack@eecs.umich.edu requests[0] = req1; 1645894Sgblack@eecs.umich.edu requests[1] = req2; 1655894Sgblack@eecs.umich.edu mainReq = main; 1665894Sgblack@eecs.umich.edu faults[0] = faults[1] = NoFault; 1676023Snate@binkert.org this->data = data; 1686023Snate@binkert.org this->mode = mode; 1695894Sgblack@eecs.umich.edu } 1705894Sgblack@eecs.umich.edu }; 1715894Sgblack@eecs.umich.edu 1725894Sgblack@eecs.umich.edu TimingSimpleCPU *cpu; 1735894Sgblack@eecs.umich.edu int index; 1745894Sgblack@eecs.umich.edu WholeTranslationState *state; 1755894Sgblack@eecs.umich.edu 1765894Sgblack@eecs.umich.edu SplitDataTranslation(TimingSimpleCPU *_cpu, int _index, 1776023Snate@binkert.org WholeTranslationState *_state) 1786023Snate@binkert.org : cpu(_cpu), index(_index), state(_state) 1795894Sgblack@eecs.umich.edu {} 1805894Sgblack@eecs.umich.edu 1815894Sgblack@eecs.umich.edu void 1826023Snate@binkert.org finish(Fault fault, RequestPtr req, ThreadContext *tc, 1836023Snate@binkert.org BaseTLB::Mode mode) 1845894Sgblack@eecs.umich.edu { 1855894Sgblack@eecs.umich.edu assert(state); 1865894Sgblack@eecs.umich.edu assert(state->outstanding); 1875894Sgblack@eecs.umich.edu state->faults[index] = fault; 1885894Sgblack@eecs.umich.edu if (--state->outstanding == 0) { 1895894Sgblack@eecs.umich.edu cpu->sendSplitData(state->faults[0], 1905894Sgblack@eecs.umich.edu state->faults[1], 1915894Sgblack@eecs.umich.edu state->requests[0], 1925894Sgblack@eecs.umich.edu state->requests[1], 1935894Sgblack@eecs.umich.edu state->mainReq, 1945894Sgblack@eecs.umich.edu state->data, 1956023Snate@binkert.org state->mode == BaseTLB::Read); 1965894Sgblack@eecs.umich.edu delete state; 1975894Sgblack@eecs.umich.edu } 1985894Sgblack@eecs.umich.edu delete this; 1995894Sgblack@eecs.umich.edu } 2005894Sgblack@eecs.umich.edu }; 2015894Sgblack@eecs.umich.edu 2025894Sgblack@eecs.umich.edu void sendData(Fault fault, RequestPtr req, 2035894Sgblack@eecs.umich.edu uint8_t *data, uint64_t *res, bool read); 2045894Sgblack@eecs.umich.edu void sendSplitData(Fault fault1, Fault fault2, 2055894Sgblack@eecs.umich.edu RequestPtr req1, RequestPtr req2, RequestPtr req, 2065894Sgblack@eecs.umich.edu uint8_t *data, bool read); 2075894Sgblack@eecs.umich.edu 2085894Sgblack@eecs.umich.edu void translationFault(Fault fault); 2095894Sgblack@eecs.umich.edu 2105894Sgblack@eecs.umich.edu void buildPacket(PacketPtr &pkt, RequestPtr req, bool read); 2115894Sgblack@eecs.umich.edu void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, 2125894Sgblack@eecs.umich.edu RequestPtr req1, RequestPtr req2, RequestPtr req, 2135894Sgblack@eecs.umich.edu uint8_t *data, bool read); 2145744Sgblack@eecs.umich.edu 2155728Sgblack@eecs.umich.edu bool handleReadPacket(PacketPtr pkt); 2165728Sgblack@eecs.umich.edu // This function always implicitly uses dcache_pkt. 2175728Sgblack@eecs.umich.edu bool handleWritePacket(); 2185728Sgblack@eecs.umich.edu 2192623SN/A class CpuPort : public Port 2202623SN/A { 2212623SN/A protected: 2222623SN/A TimingSimpleCPU *cpu; 2232948Ssaidi@eecs.umich.edu Tick lat; 2242623SN/A 2252623SN/A public: 2262623SN/A 2272948Ssaidi@eecs.umich.edu CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat) 2283401Sktlim@umich.edu : Port(_name, _cpu), cpu(_cpu), lat(_lat) 2292623SN/A { } 2302623SN/A 2313647Srdreslin@umich.edu bool snoopRangeSent; 2323647Srdreslin@umich.edu 2332623SN/A protected: 2342623SN/A 2353349Sbinkertn@umich.edu virtual Tick recvAtomic(PacketPtr pkt); 2362623SN/A 2373349Sbinkertn@umich.edu virtual void recvFunctional(PacketPtr pkt); 2382623SN/A 2392623SN/A virtual void recvStatusChange(Status status); 2402623SN/A 2412623SN/A virtual void getDeviceAddressRanges(AddrRangeList &resp, 2424475Sstever@eecs.umich.edu bool &snoop) 2434475Sstever@eecs.umich.edu { resp.clear(); snoop = false; } 2442948Ssaidi@eecs.umich.edu 2452948Ssaidi@eecs.umich.edu struct TickEvent : public Event 2462948Ssaidi@eecs.umich.edu { 2473349Sbinkertn@umich.edu PacketPtr pkt; 2482948Ssaidi@eecs.umich.edu TimingSimpleCPU *cpu; 2492948Ssaidi@eecs.umich.edu 2505606Snate@binkert.org TickEvent(TimingSimpleCPU *_cpu) : cpu(_cpu) {} 2515336Shines@cs.fsu.edu const char *description() const { return "Timing CPU tick"; } 2523349Sbinkertn@umich.edu void schedule(PacketPtr _pkt, Tick t); 2532948Ssaidi@eecs.umich.edu }; 2542948Ssaidi@eecs.umich.edu 2552623SN/A }; 2562623SN/A 2572623SN/A class IcachePort : public CpuPort 2582623SN/A { 2592623SN/A public: 2602623SN/A 2612948Ssaidi@eecs.umich.edu IcachePort(TimingSimpleCPU *_cpu, Tick _lat) 2622948Ssaidi@eecs.umich.edu : CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu) 2632623SN/A { } 2642623SN/A 2652623SN/A protected: 2662623SN/A 2673349Sbinkertn@umich.edu virtual bool recvTiming(PacketPtr pkt); 2682623SN/A 2692657Ssaidi@eecs.umich.edu virtual void recvRetry(); 2702948Ssaidi@eecs.umich.edu 2712948Ssaidi@eecs.umich.edu struct ITickEvent : public TickEvent 2722948Ssaidi@eecs.umich.edu { 2732948Ssaidi@eecs.umich.edu 2742948Ssaidi@eecs.umich.edu ITickEvent(TimingSimpleCPU *_cpu) 2752948Ssaidi@eecs.umich.edu : TickEvent(_cpu) {} 2762948Ssaidi@eecs.umich.edu void process(); 2775336Shines@cs.fsu.edu const char *description() const { return "Timing CPU icache tick"; } 2782948Ssaidi@eecs.umich.edu }; 2792948Ssaidi@eecs.umich.edu 2802948Ssaidi@eecs.umich.edu ITickEvent tickEvent; 2812948Ssaidi@eecs.umich.edu 2822623SN/A }; 2832623SN/A 2842623SN/A class DcachePort : public CpuPort 2852623SN/A { 2862623SN/A public: 2872623SN/A 2882948Ssaidi@eecs.umich.edu DcachePort(TimingSimpleCPU *_cpu, Tick _lat) 2892948Ssaidi@eecs.umich.edu : CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu) 2902623SN/A { } 2912623SN/A 2924192Sktlim@umich.edu virtual void setPeer(Port *port); 2934192Sktlim@umich.edu 2942623SN/A protected: 2952623SN/A 2963349Sbinkertn@umich.edu virtual bool recvTiming(PacketPtr pkt); 2972623SN/A 2982657Ssaidi@eecs.umich.edu virtual void recvRetry(); 2992948Ssaidi@eecs.umich.edu 3002948Ssaidi@eecs.umich.edu struct DTickEvent : public TickEvent 3012948Ssaidi@eecs.umich.edu { 3022948Ssaidi@eecs.umich.edu DTickEvent(TimingSimpleCPU *_cpu) 3032948Ssaidi@eecs.umich.edu : TickEvent(_cpu) {} 3042948Ssaidi@eecs.umich.edu void process(); 3055336Shines@cs.fsu.edu const char *description() const { return "Timing CPU dcache tick"; } 3062948Ssaidi@eecs.umich.edu }; 3072948Ssaidi@eecs.umich.edu 3082948Ssaidi@eecs.umich.edu DTickEvent tickEvent; 3092948Ssaidi@eecs.umich.edu 3102623SN/A }; 3112623SN/A 3122623SN/A IcachePort icachePort; 3132623SN/A DcachePort dcachePort; 3142623SN/A 3153349Sbinkertn@umich.edu PacketPtr ifetch_pkt; 3163349Sbinkertn@umich.edu PacketPtr dcache_pkt; 3172623SN/A 3183222Sktlim@umich.edu Tick previousTick; 3193170Sstever@eecs.umich.edu 3202623SN/A public: 3212623SN/A 3222856Srdreslin@umich.edu virtual Port *getPort(const std::string &if_name, int idx = -1); 3232856Srdreslin@umich.edu 3242623SN/A virtual void serialize(std::ostream &os); 3252623SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 3262623SN/A 3272901Ssaidi@eecs.umich.edu virtual unsigned int drain(Event *drain_event); 3282798Sktlim@umich.edu virtual void resume(); 3292798Sktlim@umich.edu 3302798Sktlim@umich.edu void switchOut(); 3312623SN/A void takeOverFrom(BaseCPU *oldCPU); 3322623SN/A 3332623SN/A virtual void activateContext(int thread_num, int delay); 3342623SN/A virtual void suspendContext(int thread_num); 3352623SN/A 3362623SN/A template <class T> 3372623SN/A Fault read(Addr addr, T &data, unsigned flags); 3382623SN/A 3392623SN/A template <class T> 3402623SN/A Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 3412623SN/A 3422623SN/A void fetch(); 3435894Sgblack@eecs.umich.edu void sendFetch(Fault fault, RequestPtr req, ThreadContext *tc); 3443349Sbinkertn@umich.edu void completeIfetch(PacketPtr ); 3455894Sgblack@eecs.umich.edu void completeDataAccess(PacketPtr pkt); 3462644Sstever@eecs.umich.edu void advanceInst(Fault fault); 3474471Sstever@eecs.umich.edu 3485315Sstever@gmail.com /** 3495315Sstever@gmail.com * Print state of address in memory system via PrintReq (for 3505315Sstever@gmail.com * debugging). 3515315Sstever@gmail.com */ 3525315Sstever@gmail.com void printAddr(Addr a); 3535315Sstever@gmail.com 3542798Sktlim@umich.edu private: 3554471Sstever@eecs.umich.edu 3564471Sstever@eecs.umich.edu typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent; 3575710Scws3k@cs.virginia.edu FetchEvent fetchEvent; 3584471Sstever@eecs.umich.edu 3595103Ssaidi@eecs.umich.edu struct IprEvent : Event { 3605103Ssaidi@eecs.umich.edu Packet *pkt; 3615103Ssaidi@eecs.umich.edu TimingSimpleCPU *cpu; 3625103Ssaidi@eecs.umich.edu IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t); 3635103Ssaidi@eecs.umich.edu virtual void process(); 3645336Shines@cs.fsu.edu virtual const char *description() const; 3655103Ssaidi@eecs.umich.edu }; 3665103Ssaidi@eecs.umich.edu 3672839Sktlim@umich.edu void completeDrain(); 3682623SN/A}; 3692623SN/A 3702623SN/A#endif // __CPU_SIMPLE_TIMING_HH__ 371