timing.hh revision 6023 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#ifndef __CPU_SIMPLE_TIMING_HH__
32#define __CPU_SIMPLE_TIMING_HH__
33
34#include "cpu/simple/base.hh"
35
36#include "params/TimingSimpleCPU.hh"
37
38class TimingSimpleCPU : public BaseSimpleCPU
39{
40  public:
41
42    TimingSimpleCPU(TimingSimpleCPUParams * params);
43    virtual ~TimingSimpleCPU();
44
45    virtual void init();
46
47  public:
48    Event *drainEvent;
49
50  private:
51
52    /*
53     * If an access needs to be broken into fragments, currently at most two,
54     * the the following two classes are used as the sender state of the
55     * packets so the CPU can keep track of everything. In the main packet
56     * sender state, there's an array with a spot for each fragment. If a
57     * fragment has already been accepted by the CPU, aka isn't waiting for
58     * a retry, it's pointer is NULL. After each fragment has successfully
59     * been processed, the "outstanding" counter is decremented. Once the
60     * count is zero, the entire larger access is complete.
61     */
62    class SplitMainSenderState : public Packet::SenderState
63    {
64      public:
65        int outstanding;
66        PacketPtr fragments[2];
67
68        int
69        getPendingFragment()
70        {
71            if (fragments[0]) {
72                return 0;
73            } else if (fragments[1]) {
74                return 1;
75            } else {
76                return -1;
77            }
78        }
79    };
80
81    class SplitFragmentSenderState : public Packet::SenderState
82    {
83      public:
84        SplitFragmentSenderState(PacketPtr _bigPkt, int _index) :
85            bigPkt(_bigPkt), index(_index)
86        {}
87        PacketPtr bigPkt;
88        int index;
89
90        void
91        clearFromParent()
92        {
93            SplitMainSenderState * main_send_state =
94                dynamic_cast<SplitMainSenderState *>(bigPkt->senderState);
95            main_send_state->fragments[index] = NULL;
96        }
97    };
98
99    class FetchTranslation : public BaseTLB::Translation
100    {
101      protected:
102        TimingSimpleCPU *cpu;
103
104      public:
105        FetchTranslation(TimingSimpleCPU *_cpu)
106            : cpu(_cpu)
107        {}
108
109        void
110        finish(Fault fault, RequestPtr req, ThreadContext *tc,
111               BaseTLB::Mode mode)
112        {
113            cpu->sendFetch(fault, req, tc);
114        }
115    };
116    FetchTranslation fetchTranslation;
117
118    class DataTranslation : public BaseTLB::Translation
119    {
120      protected:
121        TimingSimpleCPU *cpu;
122        uint8_t *data;
123        uint64_t *res;
124        BaseTLB::Mode mode;
125
126      public:
127        DataTranslation(TimingSimpleCPU *_cpu,
128                uint8_t *_data, uint64_t *_res, BaseTLB::Mode _mode)
129            : cpu(_cpu), data(_data), res(_res), mode(_mode)
130        {
131            assert(mode == BaseTLB::Read || mode == BaseTLB::Write);
132        }
133
134        void
135        finish(Fault fault, RequestPtr req, ThreadContext *tc,
136               BaseTLB::Mode mode)
137        {
138            assert(mode == this->mode);
139            cpu->sendData(fault, req, data, res, mode == BaseTLB::Read);
140            delete this;
141        }
142    };
143
144    class SplitDataTranslation : public BaseTLB::Translation
145    {
146      public:
147        struct WholeTranslationState
148        {
149          public:
150            int outstanding;
151            RequestPtr requests[2];
152            RequestPtr mainReq;
153            Fault faults[2];
154            uint8_t *data;
155            BaseTLB::Mode mode;
156
157            WholeTranslationState(RequestPtr req1, RequestPtr req2,
158                    RequestPtr main, uint8_t *data, BaseTLB::Mode mode)
159            {
160                assert(mode == BaseTLB::Read || mode == BaseTLB::Write);
161
162                outstanding = 2;
163                requests[0] = req1;
164                requests[1] = req2;
165                mainReq = main;
166                faults[0] = faults[1] = NoFault;
167                this->data = data;
168                this->mode = mode;
169            }
170        };
171
172        TimingSimpleCPU *cpu;
173        int index;
174        WholeTranslationState *state;
175
176        SplitDataTranslation(TimingSimpleCPU *_cpu, int _index,
177                WholeTranslationState *_state)
178            : cpu(_cpu), index(_index), state(_state)
179        {}
180
181        void
182        finish(Fault fault, RequestPtr req, ThreadContext *tc,
183               BaseTLB::Mode mode)
184        {
185            assert(state);
186            assert(state->outstanding);
187            state->faults[index] = fault;
188            if (--state->outstanding == 0) {
189                cpu->sendSplitData(state->faults[0],
190                                   state->faults[1],
191                                   state->requests[0],
192                                   state->requests[1],
193                                   state->mainReq,
194                                   state->data,
195                                   state->mode == BaseTLB::Read);
196                delete state;
197            }
198            delete this;
199        }
200    };
201
202    void sendData(Fault fault, RequestPtr req,
203            uint8_t *data, uint64_t *res, bool read);
204    void sendSplitData(Fault fault1, Fault fault2,
205            RequestPtr req1, RequestPtr req2, RequestPtr req,
206            uint8_t *data, bool read);
207
208    void translationFault(Fault fault);
209
210    void buildPacket(PacketPtr &pkt, RequestPtr req, bool read);
211    void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
212            RequestPtr req1, RequestPtr req2, RequestPtr req,
213            uint8_t *data, bool read);
214
215    bool handleReadPacket(PacketPtr pkt);
216    // This function always implicitly uses dcache_pkt.
217    bool handleWritePacket();
218
219    class CpuPort : public Port
220    {
221      protected:
222        TimingSimpleCPU *cpu;
223        Tick lat;
224
225      public:
226
227        CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat)
228            : Port(_name, _cpu), cpu(_cpu), lat(_lat)
229        { }
230
231        bool snoopRangeSent;
232
233      protected:
234
235        virtual Tick recvAtomic(PacketPtr pkt);
236
237        virtual void recvFunctional(PacketPtr pkt);
238
239        virtual void recvStatusChange(Status status);
240
241        virtual void getDeviceAddressRanges(AddrRangeList &resp,
242                                            bool &snoop)
243        { resp.clear(); snoop = false; }
244
245        struct TickEvent : public Event
246        {
247            PacketPtr pkt;
248            TimingSimpleCPU *cpu;
249
250            TickEvent(TimingSimpleCPU *_cpu) : cpu(_cpu) {}
251            const char *description() const { return "Timing CPU tick"; }
252            void schedule(PacketPtr _pkt, Tick t);
253        };
254
255    };
256
257    class IcachePort : public CpuPort
258    {
259      public:
260
261        IcachePort(TimingSimpleCPU *_cpu, Tick _lat)
262            : CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu)
263        { }
264
265      protected:
266
267        virtual bool recvTiming(PacketPtr pkt);
268
269        virtual void recvRetry();
270
271        struct ITickEvent : public TickEvent
272        {
273
274            ITickEvent(TimingSimpleCPU *_cpu)
275                : TickEvent(_cpu) {}
276            void process();
277            const char *description() const { return "Timing CPU icache tick"; }
278        };
279
280        ITickEvent tickEvent;
281
282    };
283
284    class DcachePort : public CpuPort
285    {
286      public:
287
288        DcachePort(TimingSimpleCPU *_cpu, Tick _lat)
289            : CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu)
290        { }
291
292        virtual void setPeer(Port *port);
293
294      protected:
295
296        virtual bool recvTiming(PacketPtr pkt);
297
298        virtual void recvRetry();
299
300        struct DTickEvent : public TickEvent
301        {
302            DTickEvent(TimingSimpleCPU *_cpu)
303                : TickEvent(_cpu) {}
304            void process();
305            const char *description() const { return "Timing CPU dcache tick"; }
306        };
307
308        DTickEvent tickEvent;
309
310    };
311
312    IcachePort icachePort;
313    DcachePort dcachePort;
314
315    PacketPtr ifetch_pkt;
316    PacketPtr dcache_pkt;
317
318    Tick previousTick;
319
320  public:
321
322    virtual Port *getPort(const std::string &if_name, int idx = -1);
323
324    virtual void serialize(std::ostream &os);
325    virtual void unserialize(Checkpoint *cp, const std::string &section);
326
327    virtual unsigned int drain(Event *drain_event);
328    virtual void resume();
329
330    void switchOut();
331    void takeOverFrom(BaseCPU *oldCPU);
332
333    virtual void activateContext(int thread_num, int delay);
334    virtual void suspendContext(int thread_num);
335
336    template <class T>
337    Fault read(Addr addr, T &data, unsigned flags);
338
339    template <class T>
340    Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
341
342    void fetch();
343    void sendFetch(Fault fault, RequestPtr req, ThreadContext *tc);
344    void completeIfetch(PacketPtr );
345    void completeDataAccess(PacketPtr pkt);
346    void advanceInst(Fault fault);
347
348    /**
349     * Print state of address in memory system via PrintReq (for
350     * debugging).
351     */
352    void printAddr(Addr a);
353
354  private:
355
356    typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent;
357    FetchEvent fetchEvent;
358
359    struct IprEvent : Event {
360        Packet *pkt;
361        TimingSimpleCPU *cpu;
362        IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t);
363        virtual void process();
364        virtual const char *description() const;
365    };
366
367    void completeDrain();
368};
369
370#endif // __CPU_SIMPLE_TIMING_HH__
371