timing.hh revision 5728
12623SN/A/* 22623SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292623SN/A */ 302623SN/A 312623SN/A#ifndef __CPU_SIMPLE_TIMING_HH__ 322623SN/A#define __CPU_SIMPLE_TIMING_HH__ 332623SN/A 342623SN/A#include "cpu/simple/base.hh" 352623SN/A 365529Snate@binkert.org#include "params/TimingSimpleCPU.hh" 375529Snate@binkert.org 382623SN/Aclass TimingSimpleCPU : public BaseSimpleCPU 392623SN/A{ 402623SN/A public: 412623SN/A 425529Snate@binkert.org TimingSimpleCPU(TimingSimpleCPUParams * params); 432623SN/A virtual ~TimingSimpleCPU(); 442623SN/A 452623SN/A virtual void init(); 462623SN/A 472623SN/A public: 482839Sktlim@umich.edu Event *drainEvent; 492798Sktlim@umich.edu 502623SN/A private: 512623SN/A 525728Sgblack@eecs.umich.edu /* 535728Sgblack@eecs.umich.edu * If an access needs to be broken into fragments, currently at most two, 545728Sgblack@eecs.umich.edu * the the following two classes are used as the sender state of the 555728Sgblack@eecs.umich.edu * packets so the CPU can keep track of everything. In the main packet 565728Sgblack@eecs.umich.edu * sender state, there's an array with a spot for each fragment. If a 575728Sgblack@eecs.umich.edu * fragment has already been accepted by the CPU, aka isn't waiting for 585728Sgblack@eecs.umich.edu * a retry, it's pointer is NULL. After each fragment has successfully 595728Sgblack@eecs.umich.edu * been processed, the "outstanding" counter is decremented. Once the 605728Sgblack@eecs.umich.edu * count is zero, the entire larger access is complete. 615728Sgblack@eecs.umich.edu */ 625728Sgblack@eecs.umich.edu class SplitMainSenderState : public Packet::SenderState 635728Sgblack@eecs.umich.edu { 645728Sgblack@eecs.umich.edu public: 655728Sgblack@eecs.umich.edu int outstanding; 665728Sgblack@eecs.umich.edu PacketPtr fragments[2]; 675728Sgblack@eecs.umich.edu 685728Sgblack@eecs.umich.edu SplitMainSenderState() 695728Sgblack@eecs.umich.edu { 705728Sgblack@eecs.umich.edu fragments[0] = NULL; 715728Sgblack@eecs.umich.edu fragments[1] = NULL; 725728Sgblack@eecs.umich.edu } 735728Sgblack@eecs.umich.edu 745728Sgblack@eecs.umich.edu int 755728Sgblack@eecs.umich.edu getPendingFragment() 765728Sgblack@eecs.umich.edu { 775728Sgblack@eecs.umich.edu if (fragments[0]) { 785728Sgblack@eecs.umich.edu return 0; 795728Sgblack@eecs.umich.edu } else if (fragments[1]) { 805728Sgblack@eecs.umich.edu return 1; 815728Sgblack@eecs.umich.edu } else { 825728Sgblack@eecs.umich.edu return -1; 835728Sgblack@eecs.umich.edu } 845728Sgblack@eecs.umich.edu } 855728Sgblack@eecs.umich.edu }; 865728Sgblack@eecs.umich.edu 875728Sgblack@eecs.umich.edu class SplitFragmentSenderState : public Packet::SenderState 885728Sgblack@eecs.umich.edu { 895728Sgblack@eecs.umich.edu public: 905728Sgblack@eecs.umich.edu SplitFragmentSenderState(PacketPtr _bigPkt, int _index) : 915728Sgblack@eecs.umich.edu bigPkt(_bigPkt), index(_index) 925728Sgblack@eecs.umich.edu {} 935728Sgblack@eecs.umich.edu PacketPtr bigPkt; 945728Sgblack@eecs.umich.edu int index; 955728Sgblack@eecs.umich.edu 965728Sgblack@eecs.umich.edu void 975728Sgblack@eecs.umich.edu clearFromParent() 985728Sgblack@eecs.umich.edu { 995728Sgblack@eecs.umich.edu SplitMainSenderState * main_send_state = 1005728Sgblack@eecs.umich.edu dynamic_cast<SplitMainSenderState *>(bigPkt->senderState); 1015728Sgblack@eecs.umich.edu main_send_state->fragments[index] = NULL; 1025728Sgblack@eecs.umich.edu } 1035728Sgblack@eecs.umich.edu }; 1045728Sgblack@eecs.umich.edu 1055728Sgblack@eecs.umich.edu bool handleReadPacket(PacketPtr pkt); 1065728Sgblack@eecs.umich.edu // This function always implicitly uses dcache_pkt. 1075728Sgblack@eecs.umich.edu bool handleWritePacket(); 1085728Sgblack@eecs.umich.edu 1092623SN/A class CpuPort : public Port 1102623SN/A { 1112623SN/A protected: 1122623SN/A TimingSimpleCPU *cpu; 1132948Ssaidi@eecs.umich.edu Tick lat; 1142623SN/A 1152623SN/A public: 1162623SN/A 1172948Ssaidi@eecs.umich.edu CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat) 1183401Sktlim@umich.edu : Port(_name, _cpu), cpu(_cpu), lat(_lat) 1192623SN/A { } 1202623SN/A 1213647Srdreslin@umich.edu bool snoopRangeSent; 1223647Srdreslin@umich.edu 1232623SN/A protected: 1242623SN/A 1253349Sbinkertn@umich.edu virtual Tick recvAtomic(PacketPtr pkt); 1262623SN/A 1273349Sbinkertn@umich.edu virtual void recvFunctional(PacketPtr pkt); 1282623SN/A 1292623SN/A virtual void recvStatusChange(Status status); 1302623SN/A 1312623SN/A virtual void getDeviceAddressRanges(AddrRangeList &resp, 1324475Sstever@eecs.umich.edu bool &snoop) 1334475Sstever@eecs.umich.edu { resp.clear(); snoop = false; } 1342948Ssaidi@eecs.umich.edu 1352948Ssaidi@eecs.umich.edu struct TickEvent : public Event 1362948Ssaidi@eecs.umich.edu { 1373349Sbinkertn@umich.edu PacketPtr pkt; 1382948Ssaidi@eecs.umich.edu TimingSimpleCPU *cpu; 1392948Ssaidi@eecs.umich.edu 1405606Snate@binkert.org TickEvent(TimingSimpleCPU *_cpu) : cpu(_cpu) {} 1415336Shines@cs.fsu.edu const char *description() const { return "Timing CPU tick"; } 1423349Sbinkertn@umich.edu void schedule(PacketPtr _pkt, Tick t); 1432948Ssaidi@eecs.umich.edu }; 1442948Ssaidi@eecs.umich.edu 1452623SN/A }; 1462623SN/A 1472623SN/A class IcachePort : public CpuPort 1482623SN/A { 1492623SN/A public: 1502623SN/A 1512948Ssaidi@eecs.umich.edu IcachePort(TimingSimpleCPU *_cpu, Tick _lat) 1522948Ssaidi@eecs.umich.edu : CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu) 1532623SN/A { } 1542623SN/A 1552623SN/A protected: 1562623SN/A 1573349Sbinkertn@umich.edu virtual bool recvTiming(PacketPtr pkt); 1582623SN/A 1592657Ssaidi@eecs.umich.edu virtual void recvRetry(); 1602948Ssaidi@eecs.umich.edu 1612948Ssaidi@eecs.umich.edu struct ITickEvent : public TickEvent 1622948Ssaidi@eecs.umich.edu { 1632948Ssaidi@eecs.umich.edu 1642948Ssaidi@eecs.umich.edu ITickEvent(TimingSimpleCPU *_cpu) 1652948Ssaidi@eecs.umich.edu : TickEvent(_cpu) {} 1662948Ssaidi@eecs.umich.edu void process(); 1675336Shines@cs.fsu.edu const char *description() const { return "Timing CPU icache tick"; } 1682948Ssaidi@eecs.umich.edu }; 1692948Ssaidi@eecs.umich.edu 1702948Ssaidi@eecs.umich.edu ITickEvent tickEvent; 1712948Ssaidi@eecs.umich.edu 1722623SN/A }; 1732623SN/A 1742623SN/A class DcachePort : public CpuPort 1752623SN/A { 1762623SN/A public: 1772623SN/A 1782948Ssaidi@eecs.umich.edu DcachePort(TimingSimpleCPU *_cpu, Tick _lat) 1792948Ssaidi@eecs.umich.edu : CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu) 1802623SN/A { } 1812623SN/A 1824192Sktlim@umich.edu virtual void setPeer(Port *port); 1834192Sktlim@umich.edu 1842623SN/A protected: 1852623SN/A 1863349Sbinkertn@umich.edu virtual bool recvTiming(PacketPtr pkt); 1872623SN/A 1882657Ssaidi@eecs.umich.edu virtual void recvRetry(); 1892948Ssaidi@eecs.umich.edu 1902948Ssaidi@eecs.umich.edu struct DTickEvent : public TickEvent 1912948Ssaidi@eecs.umich.edu { 1922948Ssaidi@eecs.umich.edu DTickEvent(TimingSimpleCPU *_cpu) 1932948Ssaidi@eecs.umich.edu : TickEvent(_cpu) {} 1942948Ssaidi@eecs.umich.edu void process(); 1955336Shines@cs.fsu.edu const char *description() const { return "Timing CPU dcache tick"; } 1962948Ssaidi@eecs.umich.edu }; 1972948Ssaidi@eecs.umich.edu 1982948Ssaidi@eecs.umich.edu DTickEvent tickEvent; 1992948Ssaidi@eecs.umich.edu 2002623SN/A }; 2012623SN/A 2022623SN/A IcachePort icachePort; 2032623SN/A DcachePort dcachePort; 2042623SN/A 2053349Sbinkertn@umich.edu PacketPtr ifetch_pkt; 2063349Sbinkertn@umich.edu PacketPtr dcache_pkt; 2072623SN/A 2083222Sktlim@umich.edu Tick previousTick; 2093170Sstever@eecs.umich.edu 2102623SN/A public: 2112623SN/A 2122856Srdreslin@umich.edu virtual Port *getPort(const std::string &if_name, int idx = -1); 2132856Srdreslin@umich.edu 2142623SN/A virtual void serialize(std::ostream &os); 2152623SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 2162623SN/A 2172901Ssaidi@eecs.umich.edu virtual unsigned int drain(Event *drain_event); 2182798Sktlim@umich.edu virtual void resume(); 2192798Sktlim@umich.edu 2202798Sktlim@umich.edu void switchOut(); 2212623SN/A void takeOverFrom(BaseCPU *oldCPU); 2222623SN/A 2232623SN/A virtual void activateContext(int thread_num, int delay); 2242623SN/A virtual void suspendContext(int thread_num); 2252623SN/A 2262623SN/A template <class T> 2272623SN/A Fault read(Addr addr, T &data, unsigned flags); 2282623SN/A 2295177Sgblack@eecs.umich.edu Fault translateDataReadAddr(Addr vaddr, Addr &paddr, 2305177Sgblack@eecs.umich.edu int size, unsigned flags); 2315177Sgblack@eecs.umich.edu 2322623SN/A template <class T> 2332623SN/A Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 2342623SN/A 2355177Sgblack@eecs.umich.edu Fault translateDataWriteAddr(Addr vaddr, Addr &paddr, 2365177Sgblack@eecs.umich.edu int size, unsigned flags); 2375177Sgblack@eecs.umich.edu 2382623SN/A void fetch(); 2393349Sbinkertn@umich.edu void completeIfetch(PacketPtr ); 2403349Sbinkertn@umich.edu void completeDataAccess(PacketPtr ); 2412644Sstever@eecs.umich.edu void advanceInst(Fault fault); 2424471Sstever@eecs.umich.edu 2435315Sstever@gmail.com /** 2445315Sstever@gmail.com * Print state of address in memory system via PrintReq (for 2455315Sstever@gmail.com * debugging). 2465315Sstever@gmail.com */ 2475315Sstever@gmail.com void printAddr(Addr a); 2485315Sstever@gmail.com 2492798Sktlim@umich.edu private: 2504471Sstever@eecs.umich.edu 2514471Sstever@eecs.umich.edu typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent; 2525710Scws3k@cs.virginia.edu FetchEvent fetchEvent; 2534471Sstever@eecs.umich.edu 2545103Ssaidi@eecs.umich.edu struct IprEvent : Event { 2555103Ssaidi@eecs.umich.edu Packet *pkt; 2565103Ssaidi@eecs.umich.edu TimingSimpleCPU *cpu; 2575103Ssaidi@eecs.umich.edu IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t); 2585103Ssaidi@eecs.umich.edu virtual void process(); 2595336Shines@cs.fsu.edu virtual const char *description() const; 2605103Ssaidi@eecs.umich.edu }; 2615103Ssaidi@eecs.umich.edu 2622839Sktlim@umich.edu void completeDrain(); 2632623SN/A}; 2642623SN/A 2652623SN/A#endif // __CPU_SIMPLE_TIMING_HH__ 266