timing.hh revision 5728 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#ifndef __CPU_SIMPLE_TIMING_HH__
32#define __CPU_SIMPLE_TIMING_HH__
33
34#include "cpu/simple/base.hh"
35
36#include "params/TimingSimpleCPU.hh"
37
38class TimingSimpleCPU : public BaseSimpleCPU
39{
40  public:
41
42    TimingSimpleCPU(TimingSimpleCPUParams * params);
43    virtual ~TimingSimpleCPU();
44
45    virtual void init();
46
47  public:
48    Event *drainEvent;
49
50  private:
51
52    /*
53     * If an access needs to be broken into fragments, currently at most two,
54     * the the following two classes are used as the sender state of the
55     * packets so the CPU can keep track of everything. In the main packet
56     * sender state, there's an array with a spot for each fragment. If a
57     * fragment has already been accepted by the CPU, aka isn't waiting for
58     * a retry, it's pointer is NULL. After each fragment has successfully
59     * been processed, the "outstanding" counter is decremented. Once the
60     * count is zero, the entire larger access is complete.
61     */
62    class SplitMainSenderState : public Packet::SenderState
63    {
64      public:
65        int outstanding;
66        PacketPtr fragments[2];
67
68        SplitMainSenderState()
69        {
70            fragments[0] = NULL;
71            fragments[1] = NULL;
72        }
73
74        int
75        getPendingFragment()
76        {
77            if (fragments[0]) {
78                return 0;
79            } else if (fragments[1]) {
80                return 1;
81            } else {
82                return -1;
83            }
84        }
85    };
86
87    class SplitFragmentSenderState : public Packet::SenderState
88    {
89      public:
90        SplitFragmentSenderState(PacketPtr _bigPkt, int _index) :
91            bigPkt(_bigPkt), index(_index)
92        {}
93        PacketPtr bigPkt;
94        int index;
95
96        void
97        clearFromParent()
98        {
99            SplitMainSenderState * main_send_state =
100                dynamic_cast<SplitMainSenderState *>(bigPkt->senderState);
101            main_send_state->fragments[index] = NULL;
102        }
103    };
104
105    bool handleReadPacket(PacketPtr pkt);
106    // This function always implicitly uses dcache_pkt.
107    bool handleWritePacket();
108
109    class CpuPort : public Port
110    {
111      protected:
112        TimingSimpleCPU *cpu;
113        Tick lat;
114
115      public:
116
117        CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat)
118            : Port(_name, _cpu), cpu(_cpu), lat(_lat)
119        { }
120
121        bool snoopRangeSent;
122
123      protected:
124
125        virtual Tick recvAtomic(PacketPtr pkt);
126
127        virtual void recvFunctional(PacketPtr pkt);
128
129        virtual void recvStatusChange(Status status);
130
131        virtual void getDeviceAddressRanges(AddrRangeList &resp,
132                                            bool &snoop)
133        { resp.clear(); snoop = false; }
134
135        struct TickEvent : public Event
136        {
137            PacketPtr pkt;
138            TimingSimpleCPU *cpu;
139
140            TickEvent(TimingSimpleCPU *_cpu) : cpu(_cpu) {}
141            const char *description() const { return "Timing CPU tick"; }
142            void schedule(PacketPtr _pkt, Tick t);
143        };
144
145    };
146
147    class IcachePort : public CpuPort
148    {
149      public:
150
151        IcachePort(TimingSimpleCPU *_cpu, Tick _lat)
152            : CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu)
153        { }
154
155      protected:
156
157        virtual bool recvTiming(PacketPtr pkt);
158
159        virtual void recvRetry();
160
161        struct ITickEvent : public TickEvent
162        {
163
164            ITickEvent(TimingSimpleCPU *_cpu)
165                : TickEvent(_cpu) {}
166            void process();
167            const char *description() const { return "Timing CPU icache tick"; }
168        };
169
170        ITickEvent tickEvent;
171
172    };
173
174    class DcachePort : public CpuPort
175    {
176      public:
177
178        DcachePort(TimingSimpleCPU *_cpu, Tick _lat)
179            : CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu)
180        { }
181
182        virtual void setPeer(Port *port);
183
184      protected:
185
186        virtual bool recvTiming(PacketPtr pkt);
187
188        virtual void recvRetry();
189
190        struct DTickEvent : public TickEvent
191        {
192            DTickEvent(TimingSimpleCPU *_cpu)
193                : TickEvent(_cpu) {}
194            void process();
195            const char *description() const { return "Timing CPU dcache tick"; }
196        };
197
198        DTickEvent tickEvent;
199
200    };
201
202    IcachePort icachePort;
203    DcachePort dcachePort;
204
205    PacketPtr ifetch_pkt;
206    PacketPtr dcache_pkt;
207
208    Tick previousTick;
209
210  public:
211
212    virtual Port *getPort(const std::string &if_name, int idx = -1);
213
214    virtual void serialize(std::ostream &os);
215    virtual void unserialize(Checkpoint *cp, const std::string &section);
216
217    virtual unsigned int drain(Event *drain_event);
218    virtual void resume();
219
220    void switchOut();
221    void takeOverFrom(BaseCPU *oldCPU);
222
223    virtual void activateContext(int thread_num, int delay);
224    virtual void suspendContext(int thread_num);
225
226    template <class T>
227    Fault read(Addr addr, T &data, unsigned flags);
228
229    Fault translateDataReadAddr(Addr vaddr, Addr &paddr,
230            int size, unsigned flags);
231
232    template <class T>
233    Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
234
235    Fault translateDataWriteAddr(Addr vaddr, Addr &paddr,
236            int size, unsigned flags);
237
238    void fetch();
239    void completeIfetch(PacketPtr );
240    void completeDataAccess(PacketPtr );
241    void advanceInst(Fault fault);
242
243    /**
244     * Print state of address in memory system via PrintReq (for
245     * debugging).
246     */
247    void printAddr(Addr a);
248
249  private:
250
251    typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent;
252    FetchEvent fetchEvent;
253
254    struct IprEvent : Event {
255        Packet *pkt;
256        TimingSimpleCPU *cpu;
257        IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t);
258        virtual void process();
259        virtual const char *description() const;
260    };
261
262    void completeDrain();
263};
264
265#endif // __CPU_SIMPLE_TIMING_HH__
266