base.cc revision 9920:028e4da64b42 
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2002-2005 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 */
43
44#include "arch/kernel_stats.hh"
45#include "arch/stacktrace.hh"
46#include "arch/tlb.hh"
47#include "arch/utility.hh"
48#include "arch/vtophys.hh"
49#include "base/loader/symtab.hh"
50#include "base/cp_annotate.hh"
51#include "base/cprintf.hh"
52#include "base/inifile.hh"
53#include "base/misc.hh"
54#include "base/pollevent.hh"
55#include "base/trace.hh"
56#include "base/types.hh"
57#include "config/the_isa.hh"
58#include "cpu/simple/base.hh"
59#include "cpu/base.hh"
60#include "cpu/checker/cpu.hh"
61#include "cpu/checker/thread_context.hh"
62#include "cpu/exetrace.hh"
63#include "cpu/profile.hh"
64#include "cpu/simple_thread.hh"
65#include "cpu/smt.hh"
66#include "cpu/static_inst.hh"
67#include "cpu/thread_context.hh"
68#include "debug/Decode.hh"
69#include "debug/Fetch.hh"
70#include "debug/Quiesce.hh"
71#include "mem/mem_object.hh"
72#include "mem/packet.hh"
73#include "mem/request.hh"
74#include "params/BaseSimpleCPU.hh"
75#include "sim/byteswap.hh"
76#include "sim/debug.hh"
77#include "sim/faults.hh"
78#include "sim/full_system.hh"
79#include "sim/sim_events.hh"
80#include "sim/sim_object.hh"
81#include "sim/stats.hh"
82#include "sim/system.hh"
83
84using namespace std;
85using namespace TheISA;
86
87BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
88    : BaseCPU(p), traceData(NULL), thread(NULL)
89{
90    if (FullSystem)
91        thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb,
92                                  p->isa[0]);
93    else
94        thread = new SimpleThread(this, /* thread_num */ 0, p->system,
95                                  p->workload[0], p->itb, p->dtb, p->isa[0]);
96
97    thread->setStatus(ThreadContext::Halted);
98
99    tc = thread->getTC();
100
101    if (p->checker) {
102        BaseCPU *temp_checker = p->checker;
103        checker = dynamic_cast<CheckerCPU *>(temp_checker);
104        checker->setSystem(p->system);
105        // Manipulate thread context
106        ThreadContext *cpu_tc = tc;
107        tc = new CheckerThreadContext<ThreadContext>(cpu_tc, this->checker);
108    } else {
109        checker = NULL;
110    }
111
112    numInst = 0;
113    startNumInst = 0;
114    numOp = 0;
115    startNumOp = 0;
116    numLoad = 0;
117    startNumLoad = 0;
118    lastIcacheStall = 0;
119    lastDcacheStall = 0;
120
121    threadContexts.push_back(tc);
122
123
124    fetchOffset = 0;
125    stayAtPC = false;
126}
127
128BaseSimpleCPU::~BaseSimpleCPU()
129{
130}
131
132void
133BaseSimpleCPU::deallocateContext(ThreadID thread_num)
134{
135    // for now, these are equivalent
136    suspendContext(thread_num);
137}
138
139
140void
141BaseSimpleCPU::haltContext(ThreadID thread_num)
142{
143    // for now, these are equivalent
144    suspendContext(thread_num);
145}
146
147
148void
149BaseSimpleCPU::regStats()
150{
151    using namespace Stats;
152
153    BaseCPU::regStats();
154
155    numInsts
156        .name(name() + ".committedInsts")
157        .desc("Number of instructions committed")
158        ;
159
160    numOps
161        .name(name() + ".committedOps")
162        .desc("Number of ops (including micro ops) committed")
163        ;
164
165    numIntAluAccesses
166        .name(name() + ".num_int_alu_accesses")
167        .desc("Number of integer alu accesses")
168        ;
169
170    numFpAluAccesses
171        .name(name() + ".num_fp_alu_accesses")
172        .desc("Number of float alu accesses")
173        ;
174
175    numCallsReturns
176        .name(name() + ".num_func_calls")
177        .desc("number of times a function call or return occured")
178        ;
179
180    numCondCtrlInsts
181        .name(name() + ".num_conditional_control_insts")
182        .desc("number of instructions that are conditional controls")
183        ;
184
185    numIntInsts
186        .name(name() + ".num_int_insts")
187        .desc("number of integer instructions")
188        ;
189
190    numFpInsts
191        .name(name() + ".num_fp_insts")
192        .desc("number of float instructions")
193        ;
194
195    numIntRegReads
196        .name(name() + ".num_int_register_reads")
197        .desc("number of times the integer registers were read")
198        ;
199
200    numIntRegWrites
201        .name(name() + ".num_int_register_writes")
202        .desc("number of times the integer registers were written")
203        ;
204
205    numFpRegReads
206        .name(name() + ".num_fp_register_reads")
207        .desc("number of times the floating registers were read")
208        ;
209
210    numFpRegWrites
211        .name(name() + ".num_fp_register_writes")
212        .desc("number of times the floating registers were written")
213        ;
214
215    numCCRegReads
216        .name(name() + ".num_cc_register_reads")
217        .desc("number of times the CC registers were read")
218        .flags(nozero)
219        ;
220
221    numCCRegWrites
222        .name(name() + ".num_cc_register_writes")
223        .desc("number of times the CC registers were written")
224        .flags(nozero)
225        ;
226
227    numMemRefs
228        .name(name()+".num_mem_refs")
229        .desc("number of memory refs")
230        ;
231
232    numStoreInsts
233        .name(name() + ".num_store_insts")
234        .desc("Number of store instructions")
235        ;
236
237    numLoadInsts
238        .name(name() + ".num_load_insts")
239        .desc("Number of load instructions")
240        ;
241
242    notIdleFraction
243        .name(name() + ".not_idle_fraction")
244        .desc("Percentage of non-idle cycles")
245        ;
246
247    idleFraction
248        .name(name() + ".idle_fraction")
249        .desc("Percentage of idle cycles")
250        ;
251
252    numBusyCycles
253        .name(name() + ".num_busy_cycles")
254        .desc("Number of busy cycles")
255        ;
256
257    numIdleCycles
258        .name(name()+".num_idle_cycles")
259        .desc("Number of idle cycles")
260        ;
261
262    icacheStallCycles
263        .name(name() + ".icache_stall_cycles")
264        .desc("ICache total stall cycles")
265        .prereq(icacheStallCycles)
266        ;
267
268    dcacheStallCycles
269        .name(name() + ".dcache_stall_cycles")
270        .desc("DCache total stall cycles")
271        .prereq(dcacheStallCycles)
272        ;
273
274    icacheRetryCycles
275        .name(name() + ".icache_retry_cycles")
276        .desc("ICache total retry cycles")
277        .prereq(icacheRetryCycles)
278        ;
279
280    dcacheRetryCycles
281        .name(name() + ".dcache_retry_cycles")
282        .desc("DCache total retry cycles")
283        .prereq(dcacheRetryCycles)
284        ;
285
286    idleFraction = constant(1.0) - notIdleFraction;
287    numIdleCycles = idleFraction * numCycles;
288    numBusyCycles = (notIdleFraction)*numCycles;
289}
290
291void
292BaseSimpleCPU::resetStats()
293{
294//    startNumInst = numInst;
295     notIdleFraction = (_status != Idle);
296}
297
298void
299BaseSimpleCPU::serializeThread(ostream &os, ThreadID tid)
300{
301    assert(_status == Idle || _status == Running);
302    assert(tid == 0);
303
304    thread->serialize(os);
305}
306
307void
308BaseSimpleCPU::unserializeThread(Checkpoint *cp, const string &section,
309                                 ThreadID tid)
310{
311    if (tid != 0)
312        fatal("Trying to load more than one thread into a SimpleCPU\n");
313    thread->unserialize(cp, section);
314}
315
316void
317change_thread_state(ThreadID tid, int activate, int priority)
318{
319}
320
321Addr
322BaseSimpleCPU::dbg_vtophys(Addr addr)
323{
324    return vtophys(tc, addr);
325}
326
327void
328BaseSimpleCPU::wakeup()
329{
330    if (thread->status() != ThreadContext::Suspended)
331        return;
332
333    DPRINTF(Quiesce,"Suspended Processor awoke\n");
334    thread->activate();
335}
336
337void
338BaseSimpleCPU::checkForInterrupts()
339{
340    if (checkInterrupts(tc)) {
341        Fault interrupt = interrupts->getInterrupt(tc);
342
343        if (interrupt != NoFault) {
344            fetchOffset = 0;
345            interrupts->updateIntrInfo(tc);
346            interrupt->invoke(tc);
347            thread->decoder.reset();
348        }
349    }
350}
351
352
353void
354BaseSimpleCPU::setupFetchRequest(Request *req)
355{
356    Addr instAddr = thread->instAddr();
357
358    // set up memory request for instruction fetch
359    DPRINTF(Fetch, "Fetch: PC:%08p\n", instAddr);
360
361    Addr fetchPC = (instAddr & PCMask) + fetchOffset;
362    req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instMasterId(),
363            instAddr);
364}
365
366
367void
368BaseSimpleCPU::preExecute()
369{
370    // maintain $r0 semantics
371    thread->setIntReg(ZeroReg, 0);
372#if THE_ISA == ALPHA_ISA
373    thread->setFloatReg(ZeroReg, 0.0);
374#endif // ALPHA_ISA
375
376    // check for instruction-count-based events
377    comInstEventQueue[0]->serviceEvents(numInst);
378    system->instEventQueue.serviceEvents(system->totalNumInsts);
379
380    // decode the instruction
381    inst = gtoh(inst);
382
383    TheISA::PCState pcState = thread->pcState();
384
385    if (isRomMicroPC(pcState.microPC())) {
386        stayAtPC = false;
387        curStaticInst = microcodeRom.fetchMicroop(pcState.microPC(),
388                                                  curMacroStaticInst);
389    } else if (!curMacroStaticInst) {
390        //We're not in the middle of a macro instruction
391        StaticInstPtr instPtr = NULL;
392
393        TheISA::Decoder *decoder = &(thread->decoder);
394
395        //Predecode, ie bundle up an ExtMachInst
396        //If more fetch data is needed, pass it in.
397        Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset;
398        //if(decoder->needMoreBytes())
399            decoder->moreBytes(pcState, fetchPC, inst);
400        //else
401        //    decoder->process();
402
403        //Decode an instruction if one is ready. Otherwise, we'll have to
404        //fetch beyond the MachInst at the current pc.
405        instPtr = decoder->decode(pcState);
406        if (instPtr) {
407            stayAtPC = false;
408            thread->pcState(pcState);
409        } else {
410            stayAtPC = true;
411            fetchOffset += sizeof(MachInst);
412        }
413
414        //If we decoded an instruction and it's microcoded, start pulling
415        //out micro ops
416        if (instPtr && instPtr->isMacroop()) {
417            curMacroStaticInst = instPtr;
418            curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC());
419        } else {
420            curStaticInst = instPtr;
421        }
422    } else {
423        //Read the next micro op from the macro op
424        curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC());
425    }
426
427    //If we decoded an instruction this "tick", record information about it.
428    if (curStaticInst) {
429#if TRACING_ON
430        traceData = tracer->getInstRecord(curTick(), tc,
431                curStaticInst, thread->pcState(), curMacroStaticInst);
432
433        DPRINTF(Decode,"Decode: Decoded %s instruction: %#x\n",
434                curStaticInst->getName(), curStaticInst->machInst);
435#endif // TRACING_ON
436    }
437}
438
439void
440BaseSimpleCPU::postExecute()
441{
442    assert(curStaticInst);
443
444    TheISA::PCState pc = tc->pcState();
445    Addr instAddr = pc.instAddr();
446    if (FullSystem && thread->profile) {
447        bool usermode = TheISA::inUserMode(tc);
448        thread->profilePC = usermode ? 1 : instAddr;
449        ProfileNode *node = thread->profile->consume(tc, curStaticInst);
450        if (node)
451            thread->profileNode = node;
452    }
453
454    if (curStaticInst->isMemRef()) {
455        numMemRefs++;
456    }
457
458    if (curStaticInst->isLoad()) {
459        ++numLoad;
460        comLoadEventQueue[0]->serviceEvents(numLoad);
461    }
462
463    if (CPA::available()) {
464        CPA::cpa()->swAutoBegin(tc, pc.nextInstAddr());
465    }
466
467    /* Power model statistics */
468    //integer alu accesses
469    if (curStaticInst->isInteger()){
470        numIntAluAccesses++;
471        numIntInsts++;
472    }
473
474    //float alu accesses
475    if (curStaticInst->isFloating()){
476        numFpAluAccesses++;
477        numFpInsts++;
478    }
479
480    //number of function calls/returns to get window accesses
481    if (curStaticInst->isCall() || curStaticInst->isReturn()){
482        numCallsReturns++;
483    }
484
485    //the number of branch predictions that will be made
486    if (curStaticInst->isCondCtrl()){
487        numCondCtrlInsts++;
488    }
489
490    //result bus acceses
491    if (curStaticInst->isLoad()){
492        numLoadInsts++;
493    }
494
495    if (curStaticInst->isStore()){
496        numStoreInsts++;
497    }
498    /* End power model statistics */
499
500    if (FullSystem)
501        traceFunctions(instAddr);
502
503    if (traceData) {
504        traceData->dump();
505        delete traceData;
506        traceData = NULL;
507    }
508}
509
510
511void
512BaseSimpleCPU::advancePC(Fault fault)
513{
514    //Since we're moving to a new pc, zero out the offset
515    fetchOffset = 0;
516    if (fault != NoFault) {
517        curMacroStaticInst = StaticInst::nullStaticInstPtr;
518        fault->invoke(tc, curStaticInst);
519        thread->decoder.reset();
520    } else {
521        if (curStaticInst) {
522            if (curStaticInst->isLastMicroop())
523                curMacroStaticInst = StaticInst::nullStaticInstPtr;
524            TheISA::PCState pcState = thread->pcState();
525            TheISA::advancePC(pcState, curStaticInst);
526            thread->pcState(pcState);
527        }
528    }
529}
530
531void
532BaseSimpleCPU::startup()
533{
534    BaseCPU::startup();
535    thread->startup();
536}
537