base.cc revision 9294
1/* 2 * Copyright (c) 2010-2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Steve Reinhardt 41 */ 42 43#include "arch/kernel_stats.hh" 44#include "arch/stacktrace.hh" 45#include "arch/tlb.hh" 46#include "arch/utility.hh" 47#include "arch/vtophys.hh" 48#include "base/loader/symtab.hh" 49#include "base/cp_annotate.hh" 50#include "base/cprintf.hh" 51#include "base/inifile.hh" 52#include "base/misc.hh" 53#include "base/pollevent.hh" 54#include "base/trace.hh" 55#include "base/types.hh" 56#include "config/the_isa.hh" 57#include "cpu/simple/base.hh" 58#include "cpu/base.hh" 59#include "cpu/checker/cpu.hh" 60#include "cpu/checker/thread_context.hh" 61#include "cpu/exetrace.hh" 62#include "cpu/profile.hh" 63#include "cpu/simple_thread.hh" 64#include "cpu/smt.hh" 65#include "cpu/static_inst.hh" 66#include "cpu/thread_context.hh" 67#include "debug/Decode.hh" 68#include "debug/Fetch.hh" 69#include "debug/Quiesce.hh" 70#include "mem/mem_object.hh" 71#include "mem/packet.hh" 72#include "mem/request.hh" 73#include "params/BaseSimpleCPU.hh" 74#include "sim/byteswap.hh" 75#include "sim/debug.hh" 76#include "sim/faults.hh" 77#include "sim/full_system.hh" 78#include "sim/sim_events.hh" 79#include "sim/sim_object.hh" 80#include "sim/stats.hh" 81#include "sim/system.hh" 82 83using namespace std; 84using namespace TheISA; 85 86BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p) 87 : BaseCPU(p), traceData(NULL), thread(NULL) 88{ 89 if (FullSystem) 90 thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb); 91 else 92 thread = new SimpleThread(this, /* thread_num */ 0, p->system, 93 p->workload[0], p->itb, p->dtb); 94 95 thread->setStatus(ThreadContext::Halted); 96 97 tc = thread->getTC(); 98 99 if (p->checker) { 100 BaseCPU *temp_checker = p->checker; 101 checker = dynamic_cast<CheckerCPU *>(temp_checker); 102 checker->setSystem(p->system); 103 // Manipulate thread context 104 ThreadContext *cpu_tc = tc; 105 tc = new CheckerThreadContext<ThreadContext>(cpu_tc, this->checker); 106 } else { 107 checker = NULL; 108 } 109 110 numInst = 0; 111 startNumInst = 0; 112 numOp = 0; 113 startNumOp = 0; 114 numLoad = 0; 115 startNumLoad = 0; 116 lastIcacheStall = 0; 117 lastDcacheStall = 0; 118 119 threadContexts.push_back(tc); 120 121 122 fetchOffset = 0; 123 stayAtPC = false; 124} 125 126BaseSimpleCPU::~BaseSimpleCPU() 127{ 128} 129 130void 131BaseSimpleCPU::deallocateContext(ThreadID thread_num) 132{ 133 // for now, these are equivalent 134 suspendContext(thread_num); 135} 136 137 138void 139BaseSimpleCPU::haltContext(ThreadID thread_num) 140{ 141 // for now, these are equivalent 142 suspendContext(thread_num); 143} 144 145 146void 147BaseSimpleCPU::regStats() 148{ 149 using namespace Stats; 150 151 BaseCPU::regStats(); 152 153 numInsts 154 .name(name() + ".committedInsts") 155 .desc("Number of instructions committed") 156 ; 157 158 numOps 159 .name(name() + ".committedOps") 160 .desc("Number of ops (including micro ops) committed") 161 ; 162 163 numIntAluAccesses 164 .name(name() + ".num_int_alu_accesses") 165 .desc("Number of integer alu accesses") 166 ; 167 168 numFpAluAccesses 169 .name(name() + ".num_fp_alu_accesses") 170 .desc("Number of float alu accesses") 171 ; 172 173 numCallsReturns 174 .name(name() + ".num_func_calls") 175 .desc("number of times a function call or return occured") 176 ; 177 178 numCondCtrlInsts 179 .name(name() + ".num_conditional_control_insts") 180 .desc("number of instructions that are conditional controls") 181 ; 182 183 numIntInsts 184 .name(name() + ".num_int_insts") 185 .desc("number of integer instructions") 186 ; 187 188 numFpInsts 189 .name(name() + ".num_fp_insts") 190 .desc("number of float instructions") 191 ; 192 193 numIntRegReads 194 .name(name() + ".num_int_register_reads") 195 .desc("number of times the integer registers were read") 196 ; 197 198 numIntRegWrites 199 .name(name() + ".num_int_register_writes") 200 .desc("number of times the integer registers were written") 201 ; 202 203 numFpRegReads 204 .name(name() + ".num_fp_register_reads") 205 .desc("number of times the floating registers were read") 206 ; 207 208 numFpRegWrites 209 .name(name() + ".num_fp_register_writes") 210 .desc("number of times the floating registers were written") 211 ; 212 213 numMemRefs 214 .name(name()+".num_mem_refs") 215 .desc("number of memory refs") 216 ; 217 218 numStoreInsts 219 .name(name() + ".num_store_insts") 220 .desc("Number of store instructions") 221 ; 222 223 numLoadInsts 224 .name(name() + ".num_load_insts") 225 .desc("Number of load instructions") 226 ; 227 228 notIdleFraction 229 .name(name() + ".not_idle_fraction") 230 .desc("Percentage of non-idle cycles") 231 ; 232 233 idleFraction 234 .name(name() + ".idle_fraction") 235 .desc("Percentage of idle cycles") 236 ; 237 238 numBusyCycles 239 .name(name() + ".num_busy_cycles") 240 .desc("Number of busy cycles") 241 ; 242 243 numIdleCycles 244 .name(name()+".num_idle_cycles") 245 .desc("Number of idle cycles") 246 ; 247 248 icacheStallCycles 249 .name(name() + ".icache_stall_cycles") 250 .desc("ICache total stall cycles") 251 .prereq(icacheStallCycles) 252 ; 253 254 dcacheStallCycles 255 .name(name() + ".dcache_stall_cycles") 256 .desc("DCache total stall cycles") 257 .prereq(dcacheStallCycles) 258 ; 259 260 icacheRetryCycles 261 .name(name() + ".icache_retry_cycles") 262 .desc("ICache total retry cycles") 263 .prereq(icacheRetryCycles) 264 ; 265 266 dcacheRetryCycles 267 .name(name() + ".dcache_retry_cycles") 268 .desc("DCache total retry cycles") 269 .prereq(dcacheRetryCycles) 270 ; 271 272 idleFraction = constant(1.0) - notIdleFraction; 273 numIdleCycles = idleFraction * numCycles; 274 numBusyCycles = (notIdleFraction)*numCycles; 275} 276 277void 278BaseSimpleCPU::resetStats() 279{ 280// startNumInst = numInst; 281 notIdleFraction = (_status != Idle); 282} 283 284void 285BaseSimpleCPU::serialize(ostream &os) 286{ 287 SERIALIZE_ENUM(_status); 288 BaseCPU::serialize(os); 289// SERIALIZE_SCALAR(inst); 290 nameOut(os, csprintf("%s.xc.0", name())); 291 thread->serialize(os); 292} 293 294void 295BaseSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 296{ 297 UNSERIALIZE_ENUM(_status); 298 BaseCPU::unserialize(cp, section); 299// UNSERIALIZE_SCALAR(inst); 300 thread->unserialize(cp, csprintf("%s.xc.0", section)); 301} 302 303void 304change_thread_state(ThreadID tid, int activate, int priority) 305{ 306} 307 308Addr 309BaseSimpleCPU::dbg_vtophys(Addr addr) 310{ 311 return vtophys(tc, addr); 312} 313 314void 315BaseSimpleCPU::wakeup() 316{ 317 if (thread->status() != ThreadContext::Suspended) 318 return; 319 320 DPRINTF(Quiesce,"Suspended Processor awoke\n"); 321 thread->activate(); 322} 323 324void 325BaseSimpleCPU::checkForInterrupts() 326{ 327 if (checkInterrupts(tc)) { 328 Fault interrupt = interrupts->getInterrupt(tc); 329 330 if (interrupt != NoFault) { 331 fetchOffset = 0; 332 interrupts->updateIntrInfo(tc); 333 interrupt->invoke(tc); 334 thread->decoder.reset(); 335 } 336 } 337} 338 339 340void 341BaseSimpleCPU::setupFetchRequest(Request *req) 342{ 343 Addr instAddr = thread->instAddr(); 344 345 // set up memory request for instruction fetch 346 DPRINTF(Fetch, "Fetch: PC:%08p\n", instAddr); 347 348 Addr fetchPC = (instAddr & PCMask) + fetchOffset; 349 req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instMasterId(), 350 instAddr); 351} 352 353 354void 355BaseSimpleCPU::preExecute() 356{ 357 // maintain $r0 semantics 358 thread->setIntReg(ZeroReg, 0); 359#if THE_ISA == ALPHA_ISA 360 thread->setFloatReg(ZeroReg, 0.0); 361#endif // ALPHA_ISA 362 363 // check for instruction-count-based events 364 comInstEventQueue[0]->serviceEvents(numInst); 365 system->instEventQueue.serviceEvents(system->totalNumInsts); 366 367 // decode the instruction 368 inst = gtoh(inst); 369 370 TheISA::PCState pcState = thread->pcState(); 371 372 if (isRomMicroPC(pcState.microPC())) { 373 stayAtPC = false; 374 curStaticInst = microcodeRom.fetchMicroop(pcState.microPC(), 375 curMacroStaticInst); 376 } else if (!curMacroStaticInst) { 377 //We're not in the middle of a macro instruction 378 StaticInstPtr instPtr = NULL; 379 380 TheISA::Decoder *decoder = &(thread->decoder); 381 382 //Predecode, ie bundle up an ExtMachInst 383 //This should go away once the constructor can be set up properly 384 decoder->setTC(thread->getTC()); 385 //If more fetch data is needed, pass it in. 386 Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset; 387 //if(decoder->needMoreBytes()) 388 decoder->moreBytes(pcState, fetchPC, inst); 389 //else 390 // decoder->process(); 391 392 //Decode an instruction if one is ready. Otherwise, we'll have to 393 //fetch beyond the MachInst at the current pc. 394 instPtr = decoder->decode(pcState); 395 if (instPtr) { 396 stayAtPC = false; 397 thread->pcState(pcState); 398 } else { 399 stayAtPC = true; 400 fetchOffset += sizeof(MachInst); 401 } 402 403 //If we decoded an instruction and it's microcoded, start pulling 404 //out micro ops 405 if (instPtr && instPtr->isMacroop()) { 406 curMacroStaticInst = instPtr; 407 curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC()); 408 } else { 409 curStaticInst = instPtr; 410 } 411 } else { 412 //Read the next micro op from the macro op 413 curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC()); 414 } 415 416 //If we decoded an instruction this "tick", record information about it. 417 if (curStaticInst) { 418#if TRACING_ON 419 traceData = tracer->getInstRecord(curTick(), tc, 420 curStaticInst, thread->pcState(), curMacroStaticInst); 421 422 DPRINTF(Decode,"Decode: Decoded %s instruction: %#x\n", 423 curStaticInst->getName(), curStaticInst->machInst); 424#endif // TRACING_ON 425 } 426} 427 428void 429BaseSimpleCPU::postExecute() 430{ 431 assert(curStaticInst); 432 433 TheISA::PCState pc = tc->pcState(); 434 Addr instAddr = pc.instAddr(); 435 if (FullSystem && thread->profile) { 436 bool usermode = TheISA::inUserMode(tc); 437 thread->profilePC = usermode ? 1 : instAddr; 438 ProfileNode *node = thread->profile->consume(tc, curStaticInst); 439 if (node) 440 thread->profileNode = node; 441 } 442 443 if (curStaticInst->isMemRef()) { 444 numMemRefs++; 445 } 446 447 if (curStaticInst->isLoad()) { 448 ++numLoad; 449 comLoadEventQueue[0]->serviceEvents(numLoad); 450 } 451 452 if (CPA::available()) { 453 CPA::cpa()->swAutoBegin(tc, pc.nextInstAddr()); 454 } 455 456 /* Power model statistics */ 457 //integer alu accesses 458 if (curStaticInst->isInteger()){ 459 numIntAluAccesses++; 460 numIntInsts++; 461 } 462 463 //float alu accesses 464 if (curStaticInst->isFloating()){ 465 numFpAluAccesses++; 466 numFpInsts++; 467 } 468 469 //number of function calls/returns to get window accesses 470 if (curStaticInst->isCall() || curStaticInst->isReturn()){ 471 numCallsReturns++; 472 } 473 474 //the number of branch predictions that will be made 475 if (curStaticInst->isCondCtrl()){ 476 numCondCtrlInsts++; 477 } 478 479 //result bus acceses 480 if (curStaticInst->isLoad()){ 481 numLoadInsts++; 482 } 483 484 if (curStaticInst->isStore()){ 485 numStoreInsts++; 486 } 487 /* End power model statistics */ 488 489 if (FullSystem) 490 traceFunctions(instAddr); 491 492 if (traceData) { 493 traceData->dump(); 494 delete traceData; 495 traceData = NULL; 496 } 497} 498 499 500void 501BaseSimpleCPU::advancePC(Fault fault) 502{ 503 //Since we're moving to a new pc, zero out the offset 504 fetchOffset = 0; 505 if (fault != NoFault) { 506 curMacroStaticInst = StaticInst::nullStaticInstPtr; 507 fault->invoke(tc, curStaticInst); 508 thread->decoder.reset(); 509 } else { 510 if (curStaticInst) { 511 if (curStaticInst->isLastMicroop()) 512 curMacroStaticInst = StaticInst::nullStaticInstPtr; 513 TheISA::PCState pcState = thread->pcState(); 514 TheISA::advancePC(pcState, curStaticInst); 515 thread->pcState(pcState); 516 } 517 } 518} 519 520/*Fault 521BaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr) 522{ 523 // translate to physical address 524 Fault fault = NoFault; 525 int CacheID = Op & 0x3; // Lower 3 bits identify Cache 526 int CacheOP = Op >> 2; // Upper 3 bits identify Cache Operation 527 if(CacheID > 1) 528 { 529 warn("CacheOps not implemented for secondary/tertiary caches\n"); 530 } 531 else 532 { 533 switch(CacheOP) 534 { // Fill Packet Type 535 case 0: warn("Invalidate Cache Op\n"); 536 break; 537 case 1: warn("Index Load Tag Cache Op\n"); 538 break; 539 case 2: warn("Index Store Tag Cache Op\n"); 540 break; 541 case 4: warn("Hit Invalidate Cache Op\n"); 542 break; 543 case 5: warn("Fill/Hit Writeback Invalidate Cache Op\n"); 544 break; 545 case 6: warn("Hit Writeback\n"); 546 break; 547 case 7: warn("Fetch & Lock Cache Op\n"); 548 break; 549 default: warn("Unimplemented Cache Op\n"); 550 } 551 } 552 return fault; 553}*/ 554