base.cc revision 8955:bbceb6297329
16019Shines@cs.fsu.edu/* 210037SARM gem5 Developers * Copyright (c) 2010-2011 ARM Limited 37093Sgblack@eecs.umich.edu * All rights reserved 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67093Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77093Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87093Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97093Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107093Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117093Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127093Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137093Sgblack@eecs.umich.edu * 146019Shines@cs.fsu.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 156019Shines@cs.fsu.edu * All rights reserved. 166019Shines@cs.fsu.edu * 176019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 186019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 196019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 206019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 216019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 226019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 236019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 246019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 256019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 266019Shines@cs.fsu.edu * this software without specific prior written permission. 276019Shines@cs.fsu.edu * 286019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396019Shines@cs.fsu.edu * 407399SAli.Saidi@ARM.com * Authors: Steve Reinhardt 417399SAli.Saidi@ARM.com */ 426019Shines@cs.fsu.edu 436019Shines@cs.fsu.edu#include "arch/kernel_stats.hh" 446019Shines@cs.fsu.edu#include "arch/stacktrace.hh" 4510474Sandreas.hansson@arm.com#include "arch/tlb.hh" 466019Shines@cs.fsu.edu#include "arch/utility.hh" 476019Shines@cs.fsu.edu#include "arch/vtophys.hh" 486019Shines@cs.fsu.edu#include "base/loader/symtab.hh" 496116Snate@binkert.org#include "base/cp_annotate.hh" 506019Shines@cs.fsu.edu#include "base/cprintf.hh" 518782Sgblack@eecs.umich.edu#include "base/inifile.hh" 528756Sgblack@eecs.umich.edu#include "base/misc.hh" 5310037SARM gem5 Developers#include "base/pollevent.hh" 5410037SARM gem5 Developers#include "base/range.hh" 556019Shines@cs.fsu.edu#include "base/trace.hh" 566019Shines@cs.fsu.edu#include "base/types.hh" 576019Shines@cs.fsu.edu#include "config/the_isa.hh" 586019Shines@cs.fsu.edu#include "cpu/simple/base.hh" 596019Shines@cs.fsu.edu#include "cpu/base.hh" 6010024Sdam.sunwoo@arm.com#include "cpu/checker/cpu.hh" 616019Shines@cs.fsu.edu#include "cpu/checker/thread_context.hh" 628232Snate@binkert.org#include "cpu/exetrace.hh" 638232Snate@binkert.org#include "cpu/profile.hh" 648232Snate@binkert.org#include "cpu/simple_thread.hh" 656116Snate@binkert.org#include "cpu/smt.hh" 666116Snate@binkert.org#include "cpu/static_inst.hh" 678756Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 686019Shines@cs.fsu.edu#include "debug/Decode.hh" 696019Shines@cs.fsu.edu#include "debug/Fetch.hh" 706019Shines@cs.fsu.edu#include "debug/Quiesce.hh" 716019Shines@cs.fsu.edu#include "mem/mem_object.hh" 726019Shines@cs.fsu.edu#include "mem/packet.hh" 7310037SARM gem5 Developers#include "mem/request.hh" 7410037SARM gem5 Developers#include "params/BaseSimpleCPU.hh" 7510418Sandreas.hansson@arm.com#include "sim/byteswap.hh" 7610418Sandreas.hansson@arm.com#include "sim/debug.hh" 7710418Sandreas.hansson@arm.com#include "sim/faults.hh" 7810537Sandreas.hansson@arm.com#include "sim/full_system.hh" 7910537Sandreas.hansson@arm.com#include "sim/sim_events.hh" 8010418Sandreas.hansson@arm.com#include "sim/sim_object.hh" 816019Shines@cs.fsu.edu#include "sim/stats.hh" 8210037SARM gem5 Developers#include "sim/system.hh" 837399SAli.Saidi@ARM.com 8410037SARM gem5 Developersusing namespace std; 8510037SARM gem5 Developersusing namespace TheISA; 8610037SARM gem5 Developers 8710037SARM gem5 DevelopersBaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p) 886019Shines@cs.fsu.edu : BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL) 896019Shines@cs.fsu.edu{ 906019Shines@cs.fsu.edu if (FullSystem) 916019Shines@cs.fsu.edu thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb); 9210037SARM gem5 Developers else 9310037SARM gem5 Developers thread = new SimpleThread(this, /* thread_num */ 0, p->system, 9410037SARM gem5 Developers p->workload[0], p->itb, p->dtb); 9510037SARM gem5 Developers 9610037SARM gem5 Developers thread->setStatus(ThreadContext::Halted); 9710037SARM gem5 Developers 9810037SARM gem5 Developers tc = thread->getTC(); 9910037SARM gem5 Developers 10010037SARM gem5 Developers if (p->checker) { 10110037SARM gem5 Developers BaseCPU *temp_checker = p->checker; 10210037SARM gem5 Developers checker = dynamic_cast<CheckerCPU *>(temp_checker); 10310037SARM gem5 Developers checker->setSystem(p->system); 10410037SARM gem5 Developers // Manipulate thread context 10510037SARM gem5 Developers ThreadContext *cpu_tc = tc; 10610037SARM gem5 Developers tc = new CheckerThreadContext<ThreadContext>(cpu_tc, this->checker); 1076019Shines@cs.fsu.edu } else { 1086019Shines@cs.fsu.edu checker = NULL; 1097694SAli.Saidi@ARM.com } 1107694SAli.Saidi@ARM.com 1117694SAli.Saidi@ARM.com numInst = 0; 11210037SARM gem5 Developers startNumInst = 0; 11310037SARM gem5 Developers numOp = 0; 11410037SARM gem5 Developers startNumOp = 0; 11510037SARM gem5 Developers numLoad = 0; 11610037SARM gem5 Developers startNumLoad = 0; 11710037SARM gem5 Developers lastIcacheStall = 0; 11810037SARM gem5 Developers lastDcacheStall = 0; 11910037SARM gem5 Developers 12010037SARM gem5 Developers threadContexts.push_back(tc); 1217694SAli.Saidi@ARM.com 1227694SAli.Saidi@ARM.com 1237694SAli.Saidi@ARM.com fetchOffset = 0; 1247694SAli.Saidi@ARM.com stayAtPC = false; 1257694SAli.Saidi@ARM.com} 1267694SAli.Saidi@ARM.com 1279738Sandreas@sandberg.pp.seBaseSimpleCPU::~BaseSimpleCPU() 1289738Sandreas@sandberg.pp.se{ 1299738Sandreas@sandberg.pp.se} 1309738Sandreas@sandberg.pp.se 1319738Sandreas@sandberg.pp.sevoid 1329738Sandreas@sandberg.pp.seBaseSimpleCPU::deallocateContext(ThreadID thread_num) 1337404SAli.Saidi@ARM.com{ 13410037SARM gem5 Developers // for now, these are equivalent 13510037SARM gem5 Developers suspendContext(thread_num); 1366019Shines@cs.fsu.edu} 1377404SAli.Saidi@ARM.com 1387404SAli.Saidi@ARM.com 1397404SAli.Saidi@ARM.comvoid 14010037SARM gem5 DevelopersBaseSimpleCPU::haltContext(ThreadID thread_num) 1417404SAli.Saidi@ARM.com{ 1427404SAli.Saidi@ARM.com // for now, these are equivalent 14310037SARM gem5 Developers suspendContext(thread_num); 14410037SARM gem5 Developers} 14510037SARM gem5 Developers 14610037SARM gem5 Developers 14710037SARM gem5 Developersvoid 1489535Smrinmoy.ghosh@arm.comBaseSimpleCPU::regStats() 1497697SAli.Saidi@ARM.com{ 1507697SAli.Saidi@ARM.com using namespace Stats; 15110037SARM gem5 Developers 1527697SAli.Saidi@ARM.com BaseCPU::regStats(); 1537697SAli.Saidi@ARM.com 1547697SAli.Saidi@ARM.com numInsts 1557697SAli.Saidi@ARM.com .name(name() + ".committedInsts") 1567697SAli.Saidi@ARM.com .desc("Number of instructions committed") 1577404SAli.Saidi@ARM.com ; 1587404SAli.Saidi@ARM.com 15910037SARM gem5 Developers numOps 1607404SAli.Saidi@ARM.com .name(name() + ".committedOps") 1617404SAli.Saidi@ARM.com .desc("Number of ops (including micro ops) committed") 16210037SARM gem5 Developers ; 16310037SARM gem5 Developers 16410037SARM gem5 Developers numIntAluAccesses 16510037SARM gem5 Developers .name(name() + ".num_int_alu_accesses") 16610037SARM gem5 Developers .desc("Number of integer alu accesses") 16710037SARM gem5 Developers ; 16810037SARM gem5 Developers 16910037SARM gem5 Developers numFpAluAccesses 17010367SAndrew.Bardsley@arm.com .name(name() + ".num_fp_alu_accesses") 17110037SARM gem5 Developers .desc("Number of float alu accesses") 1727404SAli.Saidi@ARM.com ; 1736019Shines@cs.fsu.edu 1746019Shines@cs.fsu.edu numCallsReturns 1756019Shines@cs.fsu.edu .name(name() + ".num_func_calls") 1766019Shines@cs.fsu.edu .desc("number of times a function call or return occured") 1777404SAli.Saidi@ARM.com ; 1786019Shines@cs.fsu.edu 1797404SAli.Saidi@ARM.com numCondCtrlInsts 18010037SARM gem5 Developers .name(name() + ".num_conditional_control_insts") 18110037SARM gem5 Developers .desc("number of instructions that are conditional controls") 18210037SARM gem5 Developers ; 18310037SARM gem5 Developers 18410037SARM gem5 Developers numIntInsts 18510037SARM gem5 Developers .name(name() + ".num_int_insts") 1867404SAli.Saidi@ARM.com .desc("number of integer instructions") 18710037SARM gem5 Developers ; 18810037SARM gem5 Developers 18910037SARM gem5 Developers numFpInsts 1907697SAli.Saidi@ARM.com .name(name() + ".num_fp_insts") 19110037SARM gem5 Developers .desc("number of float instructions") 19210037SARM gem5 Developers ; 19310037SARM gem5 Developers 19410037SARM gem5 Developers numIntRegReads 1957404SAli.Saidi@ARM.com .name(name() + ".num_int_register_reads") 1967697SAli.Saidi@ARM.com .desc("number of times the integer registers were read") 1977404SAli.Saidi@ARM.com ; 19810037SARM gem5 Developers 19910037SARM gem5 Developers numIntRegWrites 2007697SAli.Saidi@ARM.com .name(name() + ".num_int_register_writes") 2017734SAli.Saidi@ARM.com .desc("number of times the integer registers were written") 2027734SAli.Saidi@ARM.com ; 20310463SAndreas.Sandberg@ARM.com 2046019Shines@cs.fsu.edu numFpRegReads 2056019Shines@cs.fsu.edu .name(name() + ".num_fp_register_reads") 2066019Shines@cs.fsu.edu .desc("number of times the floating registers were read") 20710037SARM gem5 Developers ; 2087404SAli.Saidi@ARM.com 2097404SAli.Saidi@ARM.com numFpRegWrites 2107404SAli.Saidi@ARM.com .name(name() + ".num_fp_register_writes") 2117404SAli.Saidi@ARM.com .desc("number of times the floating registers were written") 2127404SAli.Saidi@ARM.com ; 21310037SARM gem5 Developers 21410037SARM gem5 Developers numMemRefs 21510037SARM gem5 Developers .name(name()+".num_mem_refs") 21610037SARM gem5 Developers .desc("number of memory refs") 2177404SAli.Saidi@ARM.com ; 2187404SAli.Saidi@ARM.com 2197404SAli.Saidi@ARM.com numStoreInsts 2207404SAli.Saidi@ARM.com .name(name() + ".num_store_insts") 22110037SARM gem5 Developers .desc("Number of store instructions") 2226019Shines@cs.fsu.edu ; 22310037SARM gem5 Developers 22410037SARM gem5 Developers numLoadInsts 2257404SAli.Saidi@ARM.com .name(name() + ".num_load_insts") 2267404SAli.Saidi@ARM.com .desc("Number of load instructions") 2277404SAli.Saidi@ARM.com ; 22810037SARM gem5 Developers 22910037SARM gem5 Developers notIdleFraction 23010037SARM gem5 Developers .name(name() + ".not_idle_fraction") 23110037SARM gem5 Developers .desc("Percentage of non-idle cycles") 23210037SARM gem5 Developers ; 23310037SARM gem5 Developers 23410037SARM gem5 Developers idleFraction 23510037SARM gem5 Developers .name(name() + ".idle_fraction") 23610037SARM gem5 Developers .desc("Percentage of idle cycles") 23710037SARM gem5 Developers ; 2387404SAli.Saidi@ARM.com 2397404SAli.Saidi@ARM.com numBusyCycles 24010037SARM gem5 Developers .name(name() + ".num_busy_cycles") 24110037SARM gem5 Developers .desc("Number of busy cycles") 24210037SARM gem5 Developers ; 24310037SARM gem5 Developers 24410037SARM gem5 Developers numIdleCycles 24510037SARM gem5 Developers .name(name()+".num_idle_cycles") 24610037SARM gem5 Developers .desc("Number of idle cycles") 24710037SARM gem5 Developers ; 24810037SARM gem5 Developers 24910037SARM gem5 Developers icacheStallCycles 25010037SARM gem5 Developers .name(name() + ".icache_stall_cycles") 25110037SARM gem5 Developers .desc("ICache total stall cycles") 25210037SARM gem5 Developers .prereq(icacheStallCycles) 25310037SARM gem5 Developers ; 25410037SARM gem5 Developers 25510037SARM gem5 Developers dcacheStallCycles 25610037SARM gem5 Developers .name(name() + ".dcache_stall_cycles") 25710037SARM gem5 Developers .desc("DCache total stall cycles") 25810037SARM gem5 Developers .prereq(dcacheStallCycles) 25910037SARM gem5 Developers ; 26010037SARM gem5 Developers 26110037SARM gem5 Developers icacheRetryCycles 26210037SARM gem5 Developers .name(name() + ".icache_retry_cycles") 26310037SARM gem5 Developers .desc("ICache total retry cycles") 26410037SARM gem5 Developers .prereq(icacheRetryCycles) 26510037SARM gem5 Developers ; 26610037SARM gem5 Developers 2677734SAli.Saidi@ARM.com dcacheRetryCycles 2687734SAli.Saidi@ARM.com .name(name() + ".dcache_retry_cycles") 26910037SARM gem5 Developers .desc("DCache total retry cycles") 27010037SARM gem5 Developers .prereq(dcacheRetryCycles) 27110037SARM gem5 Developers ; 27210037SARM gem5 Developers 27310037SARM gem5 Developers idleFraction = constant(1.0) - notIdleFraction; 2746019Shines@cs.fsu.edu numIdleCycles = idleFraction * numCycles; 2756019Shines@cs.fsu.edu numBusyCycles = (notIdleFraction)*numCycles; 2767404SAli.Saidi@ARM.com} 27710037SARM gem5 Developers 2787404SAli.Saidi@ARM.comvoid 27910037SARM gem5 DevelopersBaseSimpleCPU::resetStats() 28010037SARM gem5 Developers{ 28110037SARM gem5 Developers// startNumInst = numInst; 28210037SARM gem5 Developers notIdleFraction = (_status != Idle); 2837734SAli.Saidi@ARM.com} 2847404SAli.Saidi@ARM.com 2857404SAli.Saidi@ARM.comvoid 2867404SAli.Saidi@ARM.comBaseSimpleCPU::serialize(ostream &os) 28710037SARM gem5 Developers{ 2887404SAli.Saidi@ARM.com SERIALIZE_ENUM(_status); 28910037SARM gem5 Developers BaseCPU::serialize(os); 29010037SARM gem5 Developers// SERIALIZE_SCALAR(inst); 2917404SAli.Saidi@ARM.com nameOut(os, csprintf("%s.xc.0", name())); 29210037SARM gem5 Developers thread->serialize(os); 2937404SAli.Saidi@ARM.com} 2947404SAli.Saidi@ARM.com 2957404SAli.Saidi@ARM.comvoid 2967404SAli.Saidi@ARM.comBaseSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 29710037SARM gem5 Developers{ 29810037SARM gem5 Developers UNSERIALIZE_ENUM(_status); 29910037SARM gem5 Developers BaseCPU::unserialize(cp, section); 30010037SARM gem5 Developers// UNSERIALIZE_SCALAR(inst); 3017404SAli.Saidi@ARM.com thread->unserialize(cp, csprintf("%s.xc.0", section)); 30210037SARM gem5 Developers} 3037734SAli.Saidi@ARM.com 3047404SAli.Saidi@ARM.comvoid 30510037SARM gem5 Developerschange_thread_state(ThreadID tid, int activate, int priority) 3067404SAli.Saidi@ARM.com{ 3077734SAli.Saidi@ARM.com} 3087404SAli.Saidi@ARM.com 3097404SAli.Saidi@ARM.comAddr 3107404SAli.Saidi@ARM.comBaseSimpleCPU::dbg_vtophys(Addr addr) 31110037SARM gem5 Developers{ 3127404SAli.Saidi@ARM.com return vtophys(tc, addr); 31310037SARM gem5 Developers} 31410037SARM gem5 Developers 31510037SARM gem5 Developersvoid 31610037SARM gem5 DevelopersBaseSimpleCPU::wakeup() 31710037SARM gem5 Developers{ 3187404SAli.Saidi@ARM.com if (thread->status() != ThreadContext::Suspended) 31910037SARM gem5 Developers return; 32010037SARM gem5 Developers 32110037SARM gem5 Developers DPRINTF(Quiesce,"Suspended Processor awoke\n"); 32210037SARM gem5 Developers thread->activate(); 3237404SAli.Saidi@ARM.com} 32410037SARM gem5 Developers 32510037SARM gem5 Developersvoid 32610037SARM gem5 DevelopersBaseSimpleCPU::checkForInterrupts() 32710037SARM gem5 Developers{ 32810037SARM gem5 Developers if (checkInterrupts(tc)) { 32910037SARM gem5 Developers Fault interrupt = interrupts->getInterrupt(tc); 33010037SARM gem5 Developers 3317404SAli.Saidi@ARM.com if (interrupt != NoFault) { 3327734SAli.Saidi@ARM.com fetchOffset = 0; 3337404SAli.Saidi@ARM.com interrupts->updateIntrInfo(tc); 33410037SARM gem5 Developers interrupt->invoke(tc); 33510037SARM gem5 Developers predecoder.reset(); 3367404SAli.Saidi@ARM.com } 33710037SARM gem5 Developers } 33810037SARM gem5 Developers} 33910037SARM gem5 Developers 34010037SARM gem5 Developers 34110037SARM gem5 Developersvoid 34210037SARM gem5 DevelopersBaseSimpleCPU::setupFetchRequest(Request *req) 34310037SARM gem5 Developers{ 34410037SARM gem5 Developers Addr instAddr = thread->instAddr(); 34510037SARM gem5 Developers 34610037SARM gem5 Developers // set up memory request for instruction fetch 34710037SARM gem5 Developers DPRINTF(Fetch, "Fetch: PC:%08p\n", instAddr); 34810037SARM gem5 Developers 34910037SARM gem5 Developers Addr fetchPC = (instAddr & PCMask) + fetchOffset; 35010037SARM gem5 Developers req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instMasterId(), 3517404SAli.Saidi@ARM.com instAddr); 3527404SAli.Saidi@ARM.com} 3536019Shines@cs.fsu.edu 3549439SAndreas.Sandberg@ARM.com 3559439SAndreas.Sandberg@ARM.comvoid 3569439SAndreas.Sandberg@ARM.comBaseSimpleCPU::preExecute() 3579439SAndreas.Sandberg@ARM.com{ 3589439SAndreas.Sandberg@ARM.com // maintain $r0 semantics 3599439SAndreas.Sandberg@ARM.com thread->setIntReg(ZeroReg, 0); 3609439SAndreas.Sandberg@ARM.com#if THE_ISA == ALPHA_ISA 3619439SAndreas.Sandberg@ARM.com thread->setFloatReg(ZeroReg, 0.0); 36210194SGeoffrey.Blake@arm.com#endif // ALPHA_ISA 36310194SGeoffrey.Blake@arm.com 36410194SGeoffrey.Blake@arm.com // check for instruction-count-based events 36510194SGeoffrey.Blake@arm.com comInstEventQueue[0]->serviceEvents(numInst); 36610194SGeoffrey.Blake@arm.com system->instEventQueue.serviceEvents(system->totalNumInsts); 36710194SGeoffrey.Blake@arm.com 36810194SGeoffrey.Blake@arm.com // decode the instruction 36910194SGeoffrey.Blake@arm.com inst = gtoh(inst); 37010194SGeoffrey.Blake@arm.com 37110194SGeoffrey.Blake@arm.com TheISA::PCState pcState = thread->pcState(); 37210194SGeoffrey.Blake@arm.com 37310194SGeoffrey.Blake@arm.com if (isRomMicroPC(pcState.microPC())) { 37410194SGeoffrey.Blake@arm.com stayAtPC = false; 37510194SGeoffrey.Blake@arm.com curStaticInst = microcodeRom.fetchMicroop(pcState.microPC(), 37610194SGeoffrey.Blake@arm.com curMacroStaticInst); 37710194SGeoffrey.Blake@arm.com } else if (!curMacroStaticInst) { 37810194SGeoffrey.Blake@arm.com //We're not in the middle of a macro instruction 37910194SGeoffrey.Blake@arm.com StaticInstPtr instPtr = NULL; 38010194SGeoffrey.Blake@arm.com 38110194SGeoffrey.Blake@arm.com //Predecode, ie bundle up an ExtMachInst 38210194SGeoffrey.Blake@arm.com //This should go away once the constructor can be set up properly 38310194SGeoffrey.Blake@arm.com predecoder.setTC(thread->getTC()); 38410194SGeoffrey.Blake@arm.com //If more fetch data is needed, pass it in. 38510194SGeoffrey.Blake@arm.com Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset; 3866019Shines@cs.fsu.edu //if(predecoder.needMoreBytes()) 3876019Shines@cs.fsu.edu predecoder.moreBytes(pcState, fetchPC, inst); 3887733SAli.Saidi@ARM.com //else 3897733SAli.Saidi@ARM.com // predecoder.process(); 3907733SAli.Saidi@ARM.com 39110037SARM gem5 Developers //If an instruction is ready, decode it. Otherwise, we'll have to 39210037SARM gem5 Developers //fetch beyond the MachInst at the current pc. 39310037SARM gem5 Developers if (predecoder.extMachInstReady()) { 39410037SARM gem5 Developers stayAtPC = false; 3958353SAli.Saidi@ARM.com ExtMachInst machInst = predecoder.getExtMachInst(pcState); 3968353SAli.Saidi@ARM.com thread->pcState(pcState); 3978353SAli.Saidi@ARM.com instPtr = thread->decoder.decode(machInst, pcState.instAddr()); 3987733SAli.Saidi@ARM.com } else { 3997733SAli.Saidi@ARM.com stayAtPC = true; 4007733SAli.Saidi@ARM.com fetchOffset += sizeof(MachInst); 4017733SAli.Saidi@ARM.com } 4026019Shines@cs.fsu.edu 4036019Shines@cs.fsu.edu //If we decoded an instruction and it's microcoded, start pulling 4046019Shines@cs.fsu.edu //out micro ops 4056019Shines@cs.fsu.edu if (instPtr && instPtr->isMacroop()) { 4066019Shines@cs.fsu.edu curMacroStaticInst = instPtr; 4077733SAli.Saidi@ARM.com curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC()); 4086019Shines@cs.fsu.edu } else { 4097733SAli.Saidi@ARM.com curStaticInst = instPtr; 41010037SARM gem5 Developers } 41110037SARM gem5 Developers } else { 41210037SARM gem5 Developers //Read the next micro op from the macro op 41310037SARM gem5 Developers curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC()); 41410037SARM gem5 Developers } 4158353SAli.Saidi@ARM.com 4168353SAli.Saidi@ARM.com //If we decoded an instruction this "tick", record information about it. 4178353SAli.Saidi@ARM.com if (curStaticInst) { 4187733SAli.Saidi@ARM.com#if TRACING_ON 4197733SAli.Saidi@ARM.com traceData = tracer->getInstRecord(curTick(), tc, 4206019Shines@cs.fsu.edu curStaticInst, thread->pcState(), curMacroStaticInst); 4216019Shines@cs.fsu.edu 4226019Shines@cs.fsu.edu DPRINTF(Decode,"Decode: Decoded %s instruction: %#x\n", 4236019Shines@cs.fsu.edu curStaticInst->getName(), curStaticInst->machInst); 4246019Shines@cs.fsu.edu#endif // TRACING_ON 4257734SAli.Saidi@ARM.com } 4267734SAli.Saidi@ARM.com} 4277734SAli.Saidi@ARM.com 4287734SAli.Saidi@ARM.comvoid 4297734SAli.Saidi@ARM.comBaseSimpleCPU::postExecute() 4307734SAli.Saidi@ARM.com{ 4317734SAli.Saidi@ARM.com assert(curStaticInst); 4327734SAli.Saidi@ARM.com 4337734SAli.Saidi@ARM.com TheISA::PCState pc = tc->pcState(); 4347734SAli.Saidi@ARM.com Addr instAddr = pc.instAddr(); 4357734SAli.Saidi@ARM.com if (FullSystem && thread->profile) { 4367734SAli.Saidi@ARM.com bool usermode = TheISA::inUserMode(tc); 4377734SAli.Saidi@ARM.com thread->profilePC = usermode ? 1 : instAddr; 4387734SAli.Saidi@ARM.com ProfileNode *node = thread->profile->consume(tc, curStaticInst); 4397734SAli.Saidi@ARM.com if (node) 4407734SAli.Saidi@ARM.com thread->profileNode = node; 4416019Shines@cs.fsu.edu } 4426019Shines@cs.fsu.edu 4436019Shines@cs.fsu.edu if (curStaticInst->isMemRef()) { 4446019Shines@cs.fsu.edu numMemRefs++; 4457734SAli.Saidi@ARM.com } 4466019Shines@cs.fsu.edu 4476019Shines@cs.fsu.edu if (curStaticInst->isLoad()) { 4486019Shines@cs.fsu.edu ++numLoad; 4496019Shines@cs.fsu.edu comLoadEventQueue[0]->serviceEvents(numLoad); 4507734SAli.Saidi@ARM.com } 4516019Shines@cs.fsu.edu 4526019Shines@cs.fsu.edu if (CPA::available()) { 4536019Shines@cs.fsu.edu CPA::cpa()->swAutoBegin(tc, pc.nextInstAddr()); 4546019Shines@cs.fsu.edu } 4557734SAli.Saidi@ARM.com 4566019Shines@cs.fsu.edu /* Power model statistics */ 4576019Shines@cs.fsu.edu //integer alu accesses 4586019Shines@cs.fsu.edu if (curStaticInst->isInteger()){ 4596019Shines@cs.fsu.edu numIntAluAccesses++; 4607734SAli.Saidi@ARM.com numIntInsts++; 4616019Shines@cs.fsu.edu } 4626019Shines@cs.fsu.edu 4636019Shines@cs.fsu.edu //float alu accesses 4646019Shines@cs.fsu.edu if (curStaticInst->isFloating()){ 4657734SAli.Saidi@ARM.com numFpAluAccesses++; 4666019Shines@cs.fsu.edu numFpInsts++; 4676019Shines@cs.fsu.edu } 4686019Shines@cs.fsu.edu 4696019Shines@cs.fsu.edu //number of function calls/returns to get window accesses 4706019Shines@cs.fsu.edu if (curStaticInst->isCall() || curStaticInst->isReturn()){ 4716019Shines@cs.fsu.edu numCallsReturns++; 4726019Shines@cs.fsu.edu } 4736019Shines@cs.fsu.edu 4746019Shines@cs.fsu.edu //the number of branch predictions that will be made 4756019Shines@cs.fsu.edu if (curStaticInst->isCondCtrl()){ 4766019Shines@cs.fsu.edu numCondCtrlInsts++; 4776019Shines@cs.fsu.edu } 4786019Shines@cs.fsu.edu 4796019Shines@cs.fsu.edu //result bus acceses 4806019Shines@cs.fsu.edu if (curStaticInst->isLoad()){ 4816019Shines@cs.fsu.edu numLoadInsts++; 4826019Shines@cs.fsu.edu } 4836019Shines@cs.fsu.edu 4846019Shines@cs.fsu.edu if (curStaticInst->isStore()){ 4857734SAli.Saidi@ARM.com numStoreInsts++; 4867734SAli.Saidi@ARM.com } 4877734SAli.Saidi@ARM.com /* End power model statistics */ 4887734SAli.Saidi@ARM.com 4897734SAli.Saidi@ARM.com if (FullSystem) 4907734SAli.Saidi@ARM.com traceFunctions(instAddr); 4917734SAli.Saidi@ARM.com 4927734SAli.Saidi@ARM.com if (traceData) { 4937734SAli.Saidi@ARM.com traceData->dump(); 4947734SAli.Saidi@ARM.com delete traceData; 4957734SAli.Saidi@ARM.com traceData = NULL; 4967734SAli.Saidi@ARM.com } 4977734SAli.Saidi@ARM.com} 4987734SAli.Saidi@ARM.com 4997734SAli.Saidi@ARM.com 5007734SAli.Saidi@ARM.comvoid 5017734SAli.Saidi@ARM.comBaseSimpleCPU::advancePC(Fault fault) 5027734SAli.Saidi@ARM.com{ 5037734SAli.Saidi@ARM.com //Since we're moving to a new pc, zero out the offset 5047734SAli.Saidi@ARM.com fetchOffset = 0; 5057734SAli.Saidi@ARM.com if (fault != NoFault) { 5067734SAli.Saidi@ARM.com curMacroStaticInst = StaticInst::nullStaticInstPtr; 5077734SAli.Saidi@ARM.com fault->invoke(tc, curStaticInst); 5087734SAli.Saidi@ARM.com predecoder.reset(); 5097734SAli.Saidi@ARM.com } else { 5107734SAli.Saidi@ARM.com if (curStaticInst) { 5117734SAli.Saidi@ARM.com if (curStaticInst->isLastMicroop()) 5127734SAli.Saidi@ARM.com curMacroStaticInst = StaticInst::nullStaticInstPtr; 5137734SAli.Saidi@ARM.com TheISA::PCState pcState = thread->pcState(); 5147734SAli.Saidi@ARM.com TheISA::advancePC(pcState, curStaticInst); 5157734SAli.Saidi@ARM.com thread->pcState(pcState); 5167734SAli.Saidi@ARM.com } 5177734SAli.Saidi@ARM.com } 5187734SAli.Saidi@ARM.com} 5197734SAli.Saidi@ARM.com 5207734SAli.Saidi@ARM.com/*Fault 5217734SAli.Saidi@ARM.comBaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr) 5227734SAli.Saidi@ARM.com{ 5237734SAli.Saidi@ARM.com // translate to physical address 5247734SAli.Saidi@ARM.com Fault fault = NoFault; 5257734SAli.Saidi@ARM.com int CacheID = Op & 0x3; // Lower 3 bits identify Cache 5267734SAli.Saidi@ARM.com int CacheOP = Op >> 2; // Upper 3 bits identify Cache Operation 5277734SAli.Saidi@ARM.com if(CacheID > 1) 5287734SAli.Saidi@ARM.com { 5297734SAli.Saidi@ARM.com warn("CacheOps not implemented for secondary/tertiary caches\n"); 5307734SAli.Saidi@ARM.com } 5317734SAli.Saidi@ARM.com else 5327734SAli.Saidi@ARM.com { 5337734SAli.Saidi@ARM.com switch(CacheOP) 5347734SAli.Saidi@ARM.com { // Fill Packet Type 5357734SAli.Saidi@ARM.com case 0: warn("Invalidate Cache Op\n"); 5366019Shines@cs.fsu.edu break; 5376019Shines@cs.fsu.edu case 1: warn("Index Load Tag Cache Op\n"); 53810463SAndreas.Sandberg@ARM.com break; 53910463SAndreas.Sandberg@ARM.com case 2: warn("Index Store Tag Cache Op\n"); 54010463SAndreas.Sandberg@ARM.com break; 54110463SAndreas.Sandberg@ARM.com case 4: warn("Hit Invalidate Cache Op\n"); 54210463SAndreas.Sandberg@ARM.com break; 54310463SAndreas.Sandberg@ARM.com case 5: warn("Fill/Hit Writeback Invalidate Cache Op\n"); 5447404SAli.Saidi@ARM.com break; 5457404SAli.Saidi@ARM.com case 6: warn("Hit Writeback\n"); 54610037SARM gem5 Developers break; 5477404SAli.Saidi@ARM.com case 7: warn("Fetch & Lock Cache Op\n"); 54810037SARM gem5 Developers break; 54910037SARM gem5 Developers default: warn("Unimplemented Cache Op\n"); 55010037SARM gem5 Developers } 55110037SARM gem5 Developers } 55210037SARM gem5 Developers return fault; 55310037SARM gem5 Developers}*/ 55410037SARM gem5 Developers