base.cc revision 8232:b28d06a175be 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Steve Reinhardt
41 */
42
43#include "arch/faults.hh"
44#include "arch/utility.hh"
45#include "base/loader/symtab.hh"
46#include "base/cp_annotate.hh"
47#include "base/cprintf.hh"
48#include "base/inifile.hh"
49#include "base/misc.hh"
50#include "base/pollevent.hh"
51#include "base/range.hh"
52#include "base/trace.hh"
53#include "base/types.hh"
54#include "config/the_isa.hh"
55#include "cpu/simple/base.hh"
56#include "cpu/base.hh"
57#include "cpu/exetrace.hh"
58#include "cpu/profile.hh"
59#include "cpu/simple_thread.hh"
60#include "cpu/smt.hh"
61#include "cpu/static_inst.hh"
62#include "cpu/thread_context.hh"
63#include "debug/Decode.hh"
64#include "debug/Fetch.hh"
65#include "debug/Quiesce.hh"
66#include "mem/packet.hh"
67#include "mem/request.hh"
68#include "params/BaseSimpleCPU.hh"
69#include "sim/byteswap.hh"
70#include "sim/debug.hh"
71#include "sim/sim_events.hh"
72#include "sim/sim_object.hh"
73#include "sim/stats.hh"
74#include "sim/system.hh"
75
76#if FULL_SYSTEM
77#include "arch/kernel_stats.hh"
78#include "arch/stacktrace.hh"
79#include "arch/tlb.hh"
80#include "arch/vtophys.hh"
81#else // !FULL_SYSTEM
82#include "mem/mem_object.hh"
83#endif // FULL_SYSTEM
84
85using namespace std;
86using namespace TheISA;
87
88BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
89    : BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL)
90{
91#if FULL_SYSTEM
92    thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
93#else
94    thread = new SimpleThread(this, /* thread_num */ 0, p->workload[0],
95            p->itb, p->dtb);
96#endif // !FULL_SYSTEM
97
98    thread->setStatus(ThreadContext::Halted);
99
100    tc = thread->getTC();
101
102    numInst = 0;
103    startNumInst = 0;
104    numLoad = 0;
105    startNumLoad = 0;
106    lastIcacheStall = 0;
107    lastDcacheStall = 0;
108
109    threadContexts.push_back(tc);
110
111
112    fetchOffset = 0;
113    stayAtPC = false;
114}
115
116BaseSimpleCPU::~BaseSimpleCPU()
117{
118}
119
120void
121BaseSimpleCPU::deallocateContext(int thread_num)
122{
123    // for now, these are equivalent
124    suspendContext(thread_num);
125}
126
127
128void
129BaseSimpleCPU::haltContext(int thread_num)
130{
131    // for now, these are equivalent
132    suspendContext(thread_num);
133}
134
135
136void
137BaseSimpleCPU::regStats()
138{
139    using namespace Stats;
140
141    BaseCPU::regStats();
142
143    numInsts
144        .name(name() + ".num_insts")
145        .desc("Number of instructions executed")
146        ;
147
148    numIntAluAccesses
149        .name(name() + ".num_int_alu_accesses")
150        .desc("Number of integer alu accesses")
151        ;
152
153    numFpAluAccesses
154        .name(name() + ".num_fp_alu_accesses")
155        .desc("Number of float alu accesses")
156        ;
157
158    numCallsReturns
159        .name(name() + ".num_func_calls")
160        .desc("number of times a function call or return occured")
161        ;
162
163    numCondCtrlInsts
164        .name(name() + ".num_conditional_control_insts")
165        .desc("number of instructions that are conditional controls")
166        ;
167
168    numIntInsts
169        .name(name() + ".num_int_insts")
170        .desc("number of integer instructions")
171        ;
172
173    numFpInsts
174        .name(name() + ".num_fp_insts")
175        .desc("number of float instructions")
176        ;
177
178    numIntRegReads
179        .name(name() + ".num_int_register_reads")
180        .desc("number of times the integer registers were read")
181        ;
182
183    numIntRegWrites
184        .name(name() + ".num_int_register_writes")
185        .desc("number of times the integer registers were written")
186        ;
187
188    numFpRegReads
189        .name(name() + ".num_fp_register_reads")
190        .desc("number of times the floating registers were read")
191        ;
192
193    numFpRegWrites
194        .name(name() + ".num_fp_register_writes")
195        .desc("number of times the floating registers were written")
196        ;
197
198    numMemRefs
199        .name(name()+".num_mem_refs")
200        .desc("number of memory refs")
201        ;
202
203    numStoreInsts
204        .name(name() + ".num_store_insts")
205        .desc("Number of store instructions")
206        ;
207
208    numLoadInsts
209        .name(name() + ".num_load_insts")
210        .desc("Number of load instructions")
211        ;
212
213    notIdleFraction
214        .name(name() + ".not_idle_fraction")
215        .desc("Percentage of non-idle cycles")
216        ;
217
218    idleFraction
219        .name(name() + ".idle_fraction")
220        .desc("Percentage of idle cycles")
221        ;
222
223    numBusyCycles
224        .name(name() + ".num_busy_cycles")
225        .desc("Number of busy cycles")
226        ;
227
228    numIdleCycles
229        .name(name()+".num_idle_cycles")
230        .desc("Number of idle cycles")
231        ;
232
233    icacheStallCycles
234        .name(name() + ".icache_stall_cycles")
235        .desc("ICache total stall cycles")
236        .prereq(icacheStallCycles)
237        ;
238
239    dcacheStallCycles
240        .name(name() + ".dcache_stall_cycles")
241        .desc("DCache total stall cycles")
242        .prereq(dcacheStallCycles)
243        ;
244
245    icacheRetryCycles
246        .name(name() + ".icache_retry_cycles")
247        .desc("ICache total retry cycles")
248        .prereq(icacheRetryCycles)
249        ;
250
251    dcacheRetryCycles
252        .name(name() + ".dcache_retry_cycles")
253        .desc("DCache total retry cycles")
254        .prereq(dcacheRetryCycles)
255        ;
256
257    idleFraction = constant(1.0) - notIdleFraction;
258    numIdleCycles = idleFraction * numCycles;
259    numBusyCycles = (notIdleFraction)*numCycles;
260}
261
262void
263BaseSimpleCPU::resetStats()
264{
265//    startNumInst = numInst;
266     notIdleFraction = (_status != Idle);
267}
268
269void
270BaseSimpleCPU::serialize(ostream &os)
271{
272    SERIALIZE_ENUM(_status);
273    BaseCPU::serialize(os);
274//    SERIALIZE_SCALAR(inst);
275    nameOut(os, csprintf("%s.xc.0", name()));
276    thread->serialize(os);
277}
278
279void
280BaseSimpleCPU::unserialize(Checkpoint *cp, const string &section)
281{
282    UNSERIALIZE_ENUM(_status);
283    BaseCPU::unserialize(cp, section);
284//    UNSERIALIZE_SCALAR(inst);
285    thread->unserialize(cp, csprintf("%s.xc.0", section));
286}
287
288void
289change_thread_state(ThreadID tid, int activate, int priority)
290{
291}
292
293#if FULL_SYSTEM
294Addr
295BaseSimpleCPU::dbg_vtophys(Addr addr)
296{
297    return vtophys(tc, addr);
298}
299#endif // FULL_SYSTEM
300
301#if FULL_SYSTEM
302void
303BaseSimpleCPU::wakeup()
304{
305    if (thread->status() != ThreadContext::Suspended)
306        return;
307
308    DPRINTF(Quiesce,"Suspended Processor awoke\n");
309    thread->activate();
310}
311#endif // FULL_SYSTEM
312
313void
314BaseSimpleCPU::checkForInterrupts()
315{
316#if FULL_SYSTEM
317    if (checkInterrupts(tc)) {
318        Fault interrupt = interrupts->getInterrupt(tc);
319
320        if (interrupt != NoFault) {
321            fetchOffset = 0;
322            interrupts->updateIntrInfo(tc);
323            interrupt->invoke(tc);
324            predecoder.reset();
325        }
326    }
327#endif
328}
329
330
331void
332BaseSimpleCPU::setupFetchRequest(Request *req)
333{
334    Addr instAddr = thread->instAddr();
335
336    // set up memory request for instruction fetch
337    DPRINTF(Fetch, "Fetch: PC:%08p\n", instAddr);
338
339    Addr fetchPC = (instAddr & PCMask) + fetchOffset;
340    req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instAddr);
341}
342
343
344void
345BaseSimpleCPU::preExecute()
346{
347    // maintain $r0 semantics
348    thread->setIntReg(ZeroReg, 0);
349#if THE_ISA == ALPHA_ISA
350    thread->setFloatReg(ZeroReg, 0.0);
351#endif // ALPHA_ISA
352
353    // check for instruction-count-based events
354    comInstEventQueue[0]->serviceEvents(numInst);
355    system->instEventQueue.serviceEvents(system->totalNumInsts);
356
357    // decode the instruction
358    inst = gtoh(inst);
359
360    TheISA::PCState pcState = thread->pcState();
361
362    if (isRomMicroPC(pcState.microPC())) {
363        stayAtPC = false;
364        curStaticInst = microcodeRom.fetchMicroop(pcState.microPC(),
365                                                  curMacroStaticInst);
366    } else if (!curMacroStaticInst) {
367        //We're not in the middle of a macro instruction
368        StaticInstPtr instPtr = NULL;
369
370        //Predecode, ie bundle up an ExtMachInst
371        //This should go away once the constructor can be set up properly
372        predecoder.setTC(thread->getTC());
373        //If more fetch data is needed, pass it in.
374        Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset;
375        //if(predecoder.needMoreBytes())
376            predecoder.moreBytes(pcState, fetchPC, inst);
377        //else
378        //    predecoder.process();
379
380        //If an instruction is ready, decode it. Otherwise, we'll have to
381        //fetch beyond the MachInst at the current pc.
382        if (predecoder.extMachInstReady()) {
383            stayAtPC = false;
384            ExtMachInst machInst = predecoder.getExtMachInst(pcState);
385            thread->pcState(pcState);
386            instPtr = StaticInst::decode(machInst, pcState.instAddr());
387        } else {
388            stayAtPC = true;
389            fetchOffset += sizeof(MachInst);
390        }
391
392        //If we decoded an instruction and it's microcoded, start pulling
393        //out micro ops
394        if (instPtr && instPtr->isMacroop()) {
395            curMacroStaticInst = instPtr;
396            curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC());
397        } else {
398            curStaticInst = instPtr;
399        }
400    } else {
401        //Read the next micro op from the macro op
402        curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC());
403    }
404
405    //If we decoded an instruction this "tick", record information about it.
406    if(curStaticInst)
407    {
408#if TRACING_ON
409        traceData = tracer->getInstRecord(curTick(), tc,
410                curStaticInst, thread->pcState(), curMacroStaticInst);
411
412        DPRINTF(Decode,"Decode: Decoded %s instruction: 0x%x\n",
413                curStaticInst->getName(), curStaticInst->machInst);
414#endif // TRACING_ON
415    }
416}
417
418void
419BaseSimpleCPU::postExecute()
420{
421    assert(curStaticInst);
422
423    TheISA::PCState pc = tc->pcState();
424    Addr instAddr = pc.instAddr();
425#if FULL_SYSTEM
426    if (thread->profile) {
427        bool usermode = TheISA::inUserMode(tc);
428        thread->profilePC = usermode ? 1 : instAddr;
429        ProfileNode *node = thread->profile->consume(tc, curStaticInst);
430        if (node)
431            thread->profileNode = node;
432    }
433#endif
434
435    if (curStaticInst->isMemRef()) {
436        numMemRefs++;
437    }
438
439    if (curStaticInst->isLoad()) {
440        ++numLoad;
441        comLoadEventQueue[0]->serviceEvents(numLoad);
442    }
443
444    if (CPA::available()) {
445        CPA::cpa()->swAutoBegin(tc, pc.nextInstAddr());
446    }
447
448    /* Power model statistics */
449    //integer alu accesses
450    if (curStaticInst->isInteger()){
451        numIntAluAccesses++;
452        numIntInsts++;
453    }
454
455    //float alu accesses
456    if (curStaticInst->isFloating()){
457        numFpAluAccesses++;
458        numFpInsts++;
459    }
460
461    //number of function calls/returns to get window accesses
462    if (curStaticInst->isCall() || curStaticInst->isReturn()){
463        numCallsReturns++;
464    }
465
466    //the number of branch predictions that will be made
467    if (curStaticInst->isCondCtrl()){
468        numCondCtrlInsts++;
469    }
470
471    //result bus acceses
472    if (curStaticInst->isLoad()){
473        numLoadInsts++;
474    }
475
476    if (curStaticInst->isStore()){
477        numStoreInsts++;
478    }
479    /* End power model statistics */
480
481    traceFunctions(instAddr);
482
483    if (traceData) {
484        traceData->dump();
485        delete traceData;
486        traceData = NULL;
487    }
488}
489
490
491void
492BaseSimpleCPU::advancePC(Fault fault)
493{
494    //Since we're moving to a new pc, zero out the offset
495    fetchOffset = 0;
496    if (fault != NoFault) {
497        curMacroStaticInst = StaticInst::nullStaticInstPtr;
498        fault->invoke(tc, curStaticInst);
499        predecoder.reset();
500    } else {
501        if (curStaticInst) {
502            if (curStaticInst->isLastMicroop())
503                curMacroStaticInst = StaticInst::nullStaticInstPtr;
504            TheISA::PCState pcState = thread->pcState();
505            TheISA::advancePC(pcState, curStaticInst);
506            thread->pcState(pcState);
507        }
508    }
509}
510
511/*Fault
512BaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr)
513{
514    // translate to physical address
515    Fault fault = NoFault;
516    int CacheID = Op & 0x3; // Lower 3 bits identify Cache
517    int CacheOP = Op >> 2; // Upper 3 bits identify Cache Operation
518    if(CacheID > 1)
519      {
520        warn("CacheOps not implemented for secondary/tertiary caches\n");
521      }
522    else
523      {
524        switch(CacheOP)
525          { // Fill Packet Type
526          case 0: warn("Invalidate Cache Op\n");
527            break;
528          case 1: warn("Index Load Tag Cache Op\n");
529            break;
530          case 2: warn("Index Store Tag Cache Op\n");
531            break;
532          case 4: warn("Hit Invalidate Cache Op\n");
533            break;
534          case 5: warn("Fill/Hit Writeback Invalidate Cache Op\n");
535            break;
536          case 6: warn("Hit Writeback\n");
537            break;
538          case 7: warn("Fetch & Lock Cache Op\n");
539            break;
540          default: warn("Unimplemented Cache Op\n");
541          }
542      }
543    return fault;
544}*/
545