base.cc revision 5108:3b59ba14a7f3 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#include "arch/utility.hh"
32#include "arch/faults.hh"
33#include "base/cprintf.hh"
34#include "base/inifile.hh"
35#include "base/loader/symtab.hh"
36#include "base/misc.hh"
37#include "base/pollevent.hh"
38#include "base/range.hh"
39#include "base/stats/events.hh"
40#include "base/trace.hh"
41#include "cpu/base.hh"
42#include "cpu/exetrace.hh"
43#include "cpu/profile.hh"
44#include "cpu/simple/base.hh"
45#include "cpu/simple_thread.hh"
46#include "cpu/smt.hh"
47#include "cpu/static_inst.hh"
48#include "cpu/thread_context.hh"
49#include "mem/packet.hh"
50#include "sim/byteswap.hh"
51#include "sim/debug.hh"
52#include "sim/host.hh"
53#include "sim/sim_events.hh"
54#include "sim/sim_object.hh"
55#include "sim/stats.hh"
56#include "sim/system.hh"
57
58#if FULL_SYSTEM
59#include "arch/kernel_stats.hh"
60#include "arch/stacktrace.hh"
61#include "arch/tlb.hh"
62#include "arch/vtophys.hh"
63#include "base/remote_gdb.hh"
64#else // !FULL_SYSTEM
65#include "mem/mem_object.hh"
66#endif // FULL_SYSTEM
67
68using namespace std;
69using namespace TheISA;
70
71BaseSimpleCPU::BaseSimpleCPU(Params *p)
72    : BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL)
73{
74#if FULL_SYSTEM
75    thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
76#else
77    thread = new SimpleThread(this, /* thread_num */ 0, p->process,
78            p->itb, p->dtb, /* asid */ 0);
79#endif // !FULL_SYSTEM
80
81    thread->setStatus(ThreadContext::Unallocated);
82
83    tc = thread->getTC();
84
85    numInst = 0;
86    startNumInst = 0;
87    numLoad = 0;
88    startNumLoad = 0;
89    lastIcacheStall = 0;
90    lastDcacheStall = 0;
91
92    threadContexts.push_back(tc);
93
94    fetchOffset = 0;
95    stayAtPC = false;
96}
97
98BaseSimpleCPU::~BaseSimpleCPU()
99{
100}
101
102void
103BaseSimpleCPU::deallocateContext(int thread_num)
104{
105    // for now, these are equivalent
106    suspendContext(thread_num);
107}
108
109
110void
111BaseSimpleCPU::haltContext(int thread_num)
112{
113    // for now, these are equivalent
114    suspendContext(thread_num);
115}
116
117
118void
119BaseSimpleCPU::regStats()
120{
121    using namespace Stats;
122
123    BaseCPU::regStats();
124
125    numInsts
126        .name(name() + ".num_insts")
127        .desc("Number of instructions executed")
128        ;
129
130    numMemRefs
131        .name(name() + ".num_refs")
132        .desc("Number of memory references")
133        ;
134
135    notIdleFraction
136        .name(name() + ".not_idle_fraction")
137        .desc("Percentage of non-idle cycles")
138        ;
139
140    idleFraction
141        .name(name() + ".idle_fraction")
142        .desc("Percentage of idle cycles")
143        ;
144
145    icacheStallCycles
146        .name(name() + ".icache_stall_cycles")
147        .desc("ICache total stall cycles")
148        .prereq(icacheStallCycles)
149        ;
150
151    dcacheStallCycles
152        .name(name() + ".dcache_stall_cycles")
153        .desc("DCache total stall cycles")
154        .prereq(dcacheStallCycles)
155        ;
156
157    icacheRetryCycles
158        .name(name() + ".icache_retry_cycles")
159        .desc("ICache total retry cycles")
160        .prereq(icacheRetryCycles)
161        ;
162
163    dcacheRetryCycles
164        .name(name() + ".dcache_retry_cycles")
165        .desc("DCache total retry cycles")
166        .prereq(dcacheRetryCycles)
167        ;
168
169    idleFraction = constant(1.0) - notIdleFraction;
170}
171
172void
173BaseSimpleCPU::resetStats()
174{
175//    startNumInst = numInst;
176    // notIdleFraction = (_status != Idle);
177}
178
179void
180BaseSimpleCPU::serialize(ostream &os)
181{
182    BaseCPU::serialize(os);
183//    SERIALIZE_SCALAR(inst);
184    nameOut(os, csprintf("%s.xc.0", name()));
185    thread->serialize(os);
186}
187
188void
189BaseSimpleCPU::unserialize(Checkpoint *cp, const string &section)
190{
191    BaseCPU::unserialize(cp, section);
192//    UNSERIALIZE_SCALAR(inst);
193    thread->unserialize(cp, csprintf("%s.xc.0", section));
194}
195
196void
197change_thread_state(int thread_number, int activate, int priority)
198{
199}
200
201Fault
202BaseSimpleCPU::copySrcTranslate(Addr src)
203{
204#if 0
205    static bool no_warn = true;
206    int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
207    // Only support block sizes of 64 atm.
208    assert(blk_size == 64);
209    int offset = src & (blk_size - 1);
210
211    // Make sure block doesn't span page
212    if (no_warn &&
213        (src & PageMask) != ((src + blk_size) & PageMask) &&
214        (src >> 40) != 0xfffffc) {
215        warn("Copied block source spans pages %x.", src);
216        no_warn = false;
217    }
218
219    memReq->reset(src & ~(blk_size - 1), blk_size);
220
221    // translate to physical address
222    Fault fault = thread->translateDataReadReq(req);
223
224    if (fault == NoFault) {
225        thread->copySrcAddr = src;
226        thread->copySrcPhysAddr = memReq->paddr + offset;
227    } else {
228        assert(!fault->isAlignmentFault());
229
230        thread->copySrcAddr = 0;
231        thread->copySrcPhysAddr = 0;
232    }
233    return fault;
234#else
235    return NoFault;
236#endif
237}
238
239Fault
240BaseSimpleCPU::copy(Addr dest)
241{
242#if 0
243    static bool no_warn = true;
244    int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
245    // Only support block sizes of 64 atm.
246    assert(blk_size == 64);
247    uint8_t data[blk_size];
248    //assert(thread->copySrcAddr);
249    int offset = dest & (blk_size - 1);
250
251    // Make sure block doesn't span page
252    if (no_warn &&
253        (dest & PageMask) != ((dest + blk_size) & PageMask) &&
254        (dest >> 40) != 0xfffffc) {
255        no_warn = false;
256        warn("Copied block destination spans pages %x. ", dest);
257    }
258
259    memReq->reset(dest & ~(blk_size -1), blk_size);
260    // translate to physical address
261    Fault fault = thread->translateDataWriteReq(req);
262
263    if (fault == NoFault) {
264        Addr dest_addr = memReq->paddr + offset;
265        // Need to read straight from memory since we have more than 8 bytes.
266        memReq->paddr = thread->copySrcPhysAddr;
267        thread->mem->read(memReq, data);
268        memReq->paddr = dest_addr;
269        thread->mem->write(memReq, data);
270        if (dcacheInterface) {
271            memReq->cmd = Copy;
272            memReq->completionEvent = NULL;
273            memReq->paddr = thread->copySrcPhysAddr;
274            memReq->dest = dest_addr;
275            memReq->size = 64;
276            memReq->time = curTick;
277            memReq->flags &= ~INST_READ;
278            dcacheInterface->access(memReq);
279        }
280    }
281    else
282        assert(!fault->isAlignmentFault());
283
284    return fault;
285#else
286    panic("copy not implemented");
287    return NoFault;
288#endif
289}
290
291#if FULL_SYSTEM
292Addr
293BaseSimpleCPU::dbg_vtophys(Addr addr)
294{
295    return vtophys(tc, addr);
296}
297#endif // FULL_SYSTEM
298
299#if FULL_SYSTEM
300void
301BaseSimpleCPU::post_interrupt(int int_num, int index)
302{
303    BaseCPU::post_interrupt(int_num, index);
304
305    if (thread->status() == ThreadContext::Suspended) {
306                DPRINTF(Quiesce,"Suspended Processor awoke\n");
307        thread->activate();
308    }
309}
310#endif // FULL_SYSTEM
311
312void
313BaseSimpleCPU::checkForInterrupts()
314{
315#if FULL_SYSTEM
316    if (check_interrupts(tc)) {
317        Fault interrupt = interrupts.getInterrupt(tc);
318
319        if (interrupt != NoFault) {
320            interrupts.updateIntrInfo(tc);
321            interrupt->invoke(tc);
322        }
323    }
324#endif
325}
326
327
328Fault
329BaseSimpleCPU::setupFetchRequest(Request *req)
330{
331    Addr threadPC = thread->readPC();
332
333    // set up memory request for instruction fetch
334#if ISA_HAS_DELAY_SLOT
335    DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",threadPC,
336            thread->readNextPC(),thread->readNextNPC());
337#else
338    DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p\n",threadPC,
339            thread->readNextPC());
340#endif
341
342    Addr fetchPC = (threadPC & PCMask) + fetchOffset;
343    req->setVirt(0, fetchPC, sizeof(MachInst), 0, threadPC);
344
345    Fault fault = thread->translateInstReq(req);
346
347    return fault;
348}
349
350
351void
352BaseSimpleCPU::preExecute()
353{
354    // maintain $r0 semantics
355    thread->setIntReg(ZeroReg, 0);
356#if THE_ISA == ALPHA_ISA
357    thread->setFloatReg(ZeroReg, 0.0);
358#endif // ALPHA_ISA
359
360    // check for instruction-count-based events
361    comInstEventQueue[0]->serviceEvents(numInst);
362
363    // decode the instruction
364    inst = gtoh(inst);
365
366    //If we're not in the middle of a macro instruction
367    if (!curMacroStaticInst) {
368
369        StaticInstPtr instPtr = NULL;
370
371        //Predecode, ie bundle up an ExtMachInst
372        //This should go away once the constructor can be set up properly
373        predecoder.setTC(thread->getTC());
374        //If more fetch data is needed, pass it in.
375        Addr fetchPC = (thread->readPC() & PCMask) + fetchOffset;
376        //if(predecoder.needMoreBytes())
377            predecoder.moreBytes(thread->readPC(), fetchPC, inst);
378        //else
379        //    predecoder.process();
380
381        //If an instruction is ready, decode it. Otherwise, we'll have to
382        //fetch beyond the MachInst at the current pc.
383        if (predecoder.extMachInstReady()) {
384#if THE_ISA == X86_ISA
385            thread->setNextPC(thread->readPC() + predecoder.getInstSize());
386#endif // X86_ISA
387            stayAtPC = false;
388            instPtr = StaticInst::decode(predecoder.getExtMachInst(),
389                                         thread->readPC());
390        } else {
391            stayAtPC = true;
392            fetchOffset += sizeof(MachInst);
393        }
394
395        //If we decoded an instruction and it's microcoded, start pulling
396        //out micro ops
397        if (instPtr && instPtr->isMacroop()) {
398            curMacroStaticInst = instPtr;
399            curStaticInst = curMacroStaticInst->
400                fetchMicroop(thread->readMicroPC());
401        } else {
402            curStaticInst = instPtr;
403        }
404    } else {
405        //Read the next micro op from the macro op
406        curStaticInst = curMacroStaticInst->
407            fetchMicroop(thread->readMicroPC());
408    }
409
410    //If we decoded an instruction this "tick", record information about it.
411    if(curStaticInst)
412    {
413#if TRACING_ON
414        traceData = tracer->getInstRecord(curTick, tc, curStaticInst,
415                                         thread->readPC());
416
417        DPRINTF(Decode,"Decode: Decoded %s instruction: 0x%x\n",
418                curStaticInst->getName(), curStaticInst->machInst);
419#endif // TRACING_ON
420
421#if FULL_SYSTEM
422        thread->setInst(inst);
423#endif // FULL_SYSTEM
424    }
425}
426
427void
428BaseSimpleCPU::postExecute()
429{
430#if FULL_SYSTEM
431    if (thread->profile && curStaticInst) {
432        bool usermode = TheISA::inUserMode(tc);
433        thread->profilePC = usermode ? 1 : thread->readPC();
434        ProfileNode *node = thread->profile->consume(tc, curStaticInst);
435        if (node)
436            thread->profileNode = node;
437    }
438#endif
439
440    if (curStaticInst->isMemRef()) {
441        numMemRefs++;
442    }
443
444    if (curStaticInst->isLoad()) {
445        ++numLoad;
446        comLoadEventQueue[0]->serviceEvents(numLoad);
447    }
448
449    traceFunctions(thread->readPC());
450
451    if (traceData) {
452        traceData->dump();
453        delete traceData;
454        traceData = NULL;
455    }
456}
457
458
459void
460BaseSimpleCPU::advancePC(Fault fault)
461{
462    //Since we're moving to a new pc, zero out the offset
463    fetchOffset = 0;
464    if (fault != NoFault) {
465        curMacroStaticInst = StaticInst::nullStaticInstPtr;
466        fault->invoke(tc);
467        thread->setMicroPC(0);
468        thread->setNextMicroPC(1);
469    } else {
470        //If we're at the last micro op for this instruction
471        if (curStaticInst && curStaticInst->isLastMicroop()) {
472            //We should be working with a macro op
473            assert(curMacroStaticInst);
474            //Close out this macro op, and clean up the
475            //microcode state
476            curMacroStaticInst = StaticInst::nullStaticInstPtr;
477            thread->setMicroPC(0);
478            thread->setNextMicroPC(1);
479        }
480        //If we're still in a macro op
481        if (curMacroStaticInst) {
482            //Advance the micro pc
483            thread->setMicroPC(thread->readNextMicroPC());
484            //Advance the "next" micro pc. Note that there are no delay
485            //slots, and micro ops are "word" addressed.
486            thread->setNextMicroPC(thread->readNextMicroPC() + 1);
487        } else {
488            // go to the next instruction
489            thread->setPC(thread->readNextPC());
490            thread->setNextPC(thread->readNextNPC());
491            thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
492            assert(thread->readNextPC() != thread->readNextNPC());
493        }
494    }
495
496    Addr oldpc;
497    do {
498        oldpc = thread->readPC();
499        system->pcEventQueue.service(tc);
500    } while (oldpc != thread->readPC());
501}
502
503