base.cc revision 2632:1bb2f91485ea 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include "arch/utility.hh"
30#include "base/cprintf.hh"
31#include "base/inifile.hh"
32#include "base/loader/symtab.hh"
33#include "base/misc.hh"
34#include "base/pollevent.hh"
35#include "base/range.hh"
36#include "base/stats/events.hh"
37#include "base/trace.hh"
38#include "cpu/base.hh"
39#include "cpu/cpu_exec_context.hh"
40#include "cpu/exec_context.hh"
41#include "cpu/exetrace.hh"
42#include "cpu/profile.hh"
43#include "cpu/sampler/sampler.hh"
44#include "cpu/simple/base.hh"
45#include "cpu/smt.hh"
46#include "cpu/static_inst.hh"
47#include "kern/kernel_stats.hh"
48#include "mem/packet_impl.hh"
49#include "sim/byteswap.hh"
50#include "sim/builder.hh"
51#include "sim/debug.hh"
52#include "sim/host.hh"
53#include "sim/sim_events.hh"
54#include "sim/sim_object.hh"
55#include "sim/stats.hh"
56
57#if FULL_SYSTEM
58#include "base/remote_gdb.hh"
59#include "sim/system.hh"
60#include "arch/tlb.hh"
61#include "arch/stacktrace.hh"
62#include "arch/vtophys.hh"
63#else // !FULL_SYSTEM
64#include "mem/mem_object.hh"
65#endif // FULL_SYSTEM
66
67using namespace std;
68using namespace TheISA;
69
70BaseSimpleCPU::BaseSimpleCPU(Params *p)
71    : BaseCPU(p), mem(p->mem), cpuXC(NULL)
72{
73#if FULL_SYSTEM
74    cpuXC = new CPUExecContext(this, 0, p->system, p->itb, p->dtb);
75#else
76    cpuXC = new CPUExecContext(this, /* thread_num */ 0, p->process,
77            /* asid */ 0, mem);
78#endif // !FULL_SYSTEM
79
80    xcProxy = cpuXC->getProxy();
81
82    numInst = 0;
83    startNumInst = 0;
84    numLoad = 0;
85    startNumLoad = 0;
86    lastIcacheStall = 0;
87    lastDcacheStall = 0;
88
89    execContexts.push_back(xcProxy);
90}
91
92BaseSimpleCPU::~BaseSimpleCPU()
93{
94}
95
96void
97BaseSimpleCPU::deallocateContext(int thread_num)
98{
99    // for now, these are equivalent
100    suspendContext(thread_num);
101}
102
103
104void
105BaseSimpleCPU::haltContext(int thread_num)
106{
107    // for now, these are equivalent
108    suspendContext(thread_num);
109}
110
111
112void
113BaseSimpleCPU::regStats()
114{
115    using namespace Stats;
116
117    BaseCPU::regStats();
118
119    numInsts
120        .name(name() + ".num_insts")
121        .desc("Number of instructions executed")
122        ;
123
124    numMemRefs
125        .name(name() + ".num_refs")
126        .desc("Number of memory references")
127        ;
128
129    notIdleFraction
130        .name(name() + ".not_idle_fraction")
131        .desc("Percentage of non-idle cycles")
132        ;
133
134    idleFraction
135        .name(name() + ".idle_fraction")
136        .desc("Percentage of idle cycles")
137        ;
138
139    icacheStallCycles
140        .name(name() + ".icache_stall_cycles")
141        .desc("ICache total stall cycles")
142        .prereq(icacheStallCycles)
143        ;
144
145    dcacheStallCycles
146        .name(name() + ".dcache_stall_cycles")
147        .desc("DCache total stall cycles")
148        .prereq(dcacheStallCycles)
149        ;
150
151    icacheRetryCycles
152        .name(name() + ".icache_retry_cycles")
153        .desc("ICache total retry cycles")
154        .prereq(icacheRetryCycles)
155        ;
156
157    dcacheRetryCycles
158        .name(name() + ".dcache_retry_cycles")
159        .desc("DCache total retry cycles")
160        .prereq(dcacheRetryCycles)
161        ;
162
163    idleFraction = constant(1.0) - notIdleFraction;
164}
165
166void
167BaseSimpleCPU::resetStats()
168{
169    startNumInst = numInst;
170    // notIdleFraction = (_status != Idle);
171}
172
173void
174BaseSimpleCPU::serialize(ostream &os)
175{
176    BaseCPU::serialize(os);
177    SERIALIZE_SCALAR(inst);
178    nameOut(os, csprintf("%s.xc", name()));
179    cpuXC->serialize(os);
180}
181
182void
183BaseSimpleCPU::unserialize(Checkpoint *cp, const string &section)
184{
185    BaseCPU::unserialize(cp, section);
186    UNSERIALIZE_SCALAR(inst);
187    cpuXC->unserialize(cp, csprintf("%s.xc", section));
188}
189
190void
191change_thread_state(int thread_number, int activate, int priority)
192{
193}
194
195Fault
196BaseSimpleCPU::copySrcTranslate(Addr src)
197{
198#if 0
199    static bool no_warn = true;
200    int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
201    // Only support block sizes of 64 atm.
202    assert(blk_size == 64);
203    int offset = src & (blk_size - 1);
204
205    // Make sure block doesn't span page
206    if (no_warn &&
207        (src & PageMask) != ((src + blk_size) & PageMask) &&
208        (src >> 40) != 0xfffffc) {
209        warn("Copied block source spans pages %x.", src);
210        no_warn = false;
211    }
212
213    memReq->reset(src & ~(blk_size - 1), blk_size);
214
215    // translate to physical address
216    Fault fault = cpuXC->translateDataReadReq(req);
217
218    if (fault == NoFault) {
219        cpuXC->copySrcAddr = src;
220        cpuXC->copySrcPhysAddr = memReq->paddr + offset;
221    } else {
222        assert(!fault->isAlignmentFault());
223
224        cpuXC->copySrcAddr = 0;
225        cpuXC->copySrcPhysAddr = 0;
226    }
227    return fault;
228#else
229    return NoFault;
230#endif
231}
232
233Fault
234BaseSimpleCPU::copy(Addr dest)
235{
236#if 0
237    static bool no_warn = true;
238    int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
239    // Only support block sizes of 64 atm.
240    assert(blk_size == 64);
241    uint8_t data[blk_size];
242    //assert(cpuXC->copySrcAddr);
243    int offset = dest & (blk_size - 1);
244
245    // Make sure block doesn't span page
246    if (no_warn &&
247        (dest & PageMask) != ((dest + blk_size) & PageMask) &&
248        (dest >> 40) != 0xfffffc) {
249        no_warn = false;
250        warn("Copied block destination spans pages %x. ", dest);
251    }
252
253    memReq->reset(dest & ~(blk_size -1), blk_size);
254    // translate to physical address
255    Fault fault = cpuXC->translateDataWriteReq(req);
256
257    if (fault == NoFault) {
258        Addr dest_addr = memReq->paddr + offset;
259        // Need to read straight from memory since we have more than 8 bytes.
260        memReq->paddr = cpuXC->copySrcPhysAddr;
261        cpuXC->mem->read(memReq, data);
262        memReq->paddr = dest_addr;
263        cpuXC->mem->write(memReq, data);
264        if (dcacheInterface) {
265            memReq->cmd = Copy;
266            memReq->completionEvent = NULL;
267            memReq->paddr = cpuXC->copySrcPhysAddr;
268            memReq->dest = dest_addr;
269            memReq->size = 64;
270            memReq->time = curTick;
271            memReq->flags &= ~INST_READ;
272            dcacheInterface->access(memReq);
273        }
274    }
275    else
276        assert(!fault->isAlignmentFault());
277
278    return fault;
279#else
280    panic("copy not implemented");
281    return NoFault;
282#endif
283}
284
285#if FULL_SYSTEM
286Addr
287BaseSimpleCPU::dbg_vtophys(Addr addr)
288{
289    return vtophys(xcProxy, addr);
290}
291#endif // FULL_SYSTEM
292
293#if FULL_SYSTEM
294void
295BaseSimpleCPU::post_interrupt(int int_num, int index)
296{
297    BaseCPU::post_interrupt(int_num, index);
298
299    if (cpuXC->status() == ExecContext::Suspended) {
300                DPRINTF(IPI,"Suspended Processor awoke\n");
301        cpuXC->activate();
302    }
303}
304#endif // FULL_SYSTEM
305
306void
307BaseSimpleCPU::checkForInterrupts()
308{
309#if FULL_SYSTEM
310    if (checkInterrupts && check_interrupts() && !cpuXC->inPalMode()) {
311        int ipl = 0;
312        int summary = 0;
313        checkInterrupts = false;
314
315        if (cpuXC->readMiscReg(IPR_SIRR)) {
316            for (int i = INTLEVEL_SOFTWARE_MIN;
317                 i < INTLEVEL_SOFTWARE_MAX; i++) {
318                if (cpuXC->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
319                    // See table 4-19 of 21164 hardware reference
320                    ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
321                    summary |= (ULL(1) << i);
322                }
323            }
324        }
325
326        uint64_t interrupts = cpuXC->cpu->intr_status();
327        for (int i = INTLEVEL_EXTERNAL_MIN;
328            i < INTLEVEL_EXTERNAL_MAX; i++) {
329            if (interrupts & (ULL(1) << i)) {
330                // See table 4-19 of 21164 hardware reference
331                ipl = i;
332                summary |= (ULL(1) << i);
333            }
334        }
335
336        if (cpuXC->readMiscReg(IPR_ASTRR))
337            panic("asynchronous traps not implemented\n");
338
339        if (ipl && ipl > cpuXC->readMiscReg(IPR_IPLR)) {
340            cpuXC->setMiscReg(IPR_ISR, summary);
341            cpuXC->setMiscReg(IPR_INTID, ipl);
342
343            Fault(new InterruptFault)->invoke(xcProxy);
344
345            DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
346                    cpuXC->readMiscReg(IPR_IPLR), ipl, summary);
347        }
348    }
349#endif
350}
351
352
353Fault
354BaseSimpleCPU::setupFetchPacket(Packet *ifetch_pkt)
355{
356    // Try to fetch an instruction
357
358    // set up memory request for instruction fetch
359
360    DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",cpuXC->readPC(),
361            cpuXC->readNextPC(),cpuXC->readNextNPC());
362
363    Request *ifetch_req = ifetch_pkt->req;
364    ifetch_req->setVaddr(cpuXC->readPC() & ~3);
365    ifetch_req->setTime(curTick);
366#if FULL_SYSTEM
367    ifetch_req->setFlags((cpuXC->readPC() & 1) ? PHYSICAL : 0);
368#else
369    ifetch_req->setFlags(0);
370#endif
371
372    Fault fault = cpuXC->translateInstReq(ifetch_req);
373
374    if (fault == NoFault) {
375        ifetch_pkt->addr = ifetch_req->getPaddr();
376    }
377
378    return fault;
379}
380
381
382void
383BaseSimpleCPU::preExecute()
384{
385    // maintain $r0 semantics
386    cpuXC->setIntReg(ZeroReg, 0);
387#if THE_ISA == ALPHA_ISA
388    cpuXC->setFloatReg(ZeroReg, 0.0);
389#endif // ALPHA_ISA
390
391    // keep an instruction count
392    numInst++;
393    numInsts++;
394
395    cpuXC->func_exe_inst++;
396
397    // check for instruction-count-based events
398    comInstEventQueue[0]->serviceEvents(numInst);
399
400    // decode the instruction
401    inst = gtoh(inst);
402    curStaticInst = StaticInst::decode(makeExtMI(inst, cpuXC->readPC()));
403
404    traceData = Trace::getInstRecord(curTick, xcProxy, this, curStaticInst,
405                                     cpuXC->readPC());
406
407    DPRINTF(Decode,"Decode: Decoded %s instruction (opcode: 0x%x): 0x%x\n",
408            curStaticInst->getName(), curStaticInst->getOpcode(),
409            curStaticInst->machInst);
410
411#if FULL_SYSTEM
412    cpuXC->setInst(inst);
413#endif // FULL_SYSTEM
414}
415
416void
417BaseSimpleCPU::postExecute()
418{
419#if FULL_SYSTEM
420    if (system->kernelBinning->fnbin) {
421        assert(kernelStats);
422        system->kernelBinning->execute(xcProxy, inst);
423    }
424
425    if (cpuXC->profile) {
426        bool usermode =
427            (cpuXC->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
428        cpuXC->profilePC = usermode ? 1 : cpuXC->readPC();
429        ProfileNode *node = cpuXC->profile->consume(xcProxy, inst);
430        if (node)
431            cpuXC->profileNode = node;
432    }
433#endif
434
435    if (curStaticInst->isMemRef()) {
436        numMemRefs++;
437    }
438
439    if (curStaticInst->isLoad()) {
440        ++numLoad;
441        comLoadEventQueue[0]->serviceEvents(numLoad);
442    }
443
444    traceFunctions(cpuXC->readPC());
445}
446
447
448void
449BaseSimpleCPU::advancePC(Fault fault)
450{
451    if (fault != NoFault) {
452#if FULL_SYSTEM
453        fault->invoke(xcProxy);
454#else // !FULL_SYSTEM
455        fatal("fault (%s) detected @ PC %08p", fault->name(), cpuXC->readPC());
456#endif // FULL_SYSTEM
457    }
458    else {
459        // go to the next instruction
460        cpuXC->setPC(cpuXC->readNextPC());
461#if THE_ISA == ALPHA_ISA
462        cpuXC->setNextPC(cpuXC->readNextPC() + sizeof(MachInst));
463#else
464        cpuXC->setNextPC(cpuXC->readNextNPC());
465        cpuXC->setNextNPC(cpuXC->readNextNPC() + sizeof(MachInst));
466#endif
467
468    }
469
470#if FULL_SYSTEM
471    Addr oldpc;
472    do {
473        oldpc = cpuXC->readPC();
474        system->pcEventQueue.service(xcProxy);
475    } while (oldpc != cpuXC->readPC());
476#endif
477}
478
479