base.cc revision 10537:47fe87b0cf97 
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2002-2005 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 */
43
44#include "arch/kernel_stats.hh"
45#include "arch/stacktrace.hh"
46#include "arch/tlb.hh"
47#include "arch/utility.hh"
48#include "arch/vtophys.hh"
49#include "base/loader/symtab.hh"
50#include "base/cp_annotate.hh"
51#include "base/cprintf.hh"
52#include "base/inifile.hh"
53#include "base/misc.hh"
54#include "base/pollevent.hh"
55#include "base/trace.hh"
56#include "base/types.hh"
57#include "config/the_isa.hh"
58#include "cpu/simple/base.hh"
59#include "cpu/base.hh"
60#include "cpu/checker/cpu.hh"
61#include "cpu/checker/thread_context.hh"
62#include "cpu/exetrace.hh"
63#include "cpu/pred/bpred_unit.hh"
64#include "cpu/profile.hh"
65#include "cpu/simple_thread.hh"
66#include "cpu/smt.hh"
67#include "cpu/static_inst.hh"
68#include "cpu/thread_context.hh"
69#include "debug/Decode.hh"
70#include "debug/Fetch.hh"
71#include "debug/Quiesce.hh"
72#include "mem/mem_object.hh"
73#include "mem/packet.hh"
74#include "mem/request.hh"
75#include "params/BaseSimpleCPU.hh"
76#include "sim/byteswap.hh"
77#include "sim/debug.hh"
78#include "sim/faults.hh"
79#include "sim/full_system.hh"
80#include "sim/sim_events.hh"
81#include "sim/sim_object.hh"
82#include "sim/stats.hh"
83#include "sim/system.hh"
84
85using namespace std;
86using namespace TheISA;
87
88BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
89    : BaseCPU(p),
90      branchPred(p->branchPred),
91      traceData(NULL), thread(NULL), _status(Idle), interval_stats(false),
92      inst()
93{
94    if (FullSystem)
95        thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb,
96                                  p->isa[0]);
97    else
98        thread = new SimpleThread(this, /* thread_num */ 0, p->system,
99                                  p->workload[0], p->itb, p->dtb, p->isa[0]);
100
101    thread->setStatus(ThreadContext::Halted);
102
103    tc = thread->getTC();
104
105    if (p->checker) {
106        BaseCPU *temp_checker = p->checker;
107        checker = dynamic_cast<CheckerCPU *>(temp_checker);
108        checker->setSystem(p->system);
109        // Manipulate thread context
110        ThreadContext *cpu_tc = tc;
111        tc = new CheckerThreadContext<ThreadContext>(cpu_tc, this->checker);
112    } else {
113        checker = NULL;
114    }
115
116    numInst = 0;
117    startNumInst = 0;
118    numOp = 0;
119    startNumOp = 0;
120    numLoad = 0;
121    startNumLoad = 0;
122    lastIcacheStall = 0;
123    lastDcacheStall = 0;
124
125    threadContexts.push_back(tc);
126
127
128    fetchOffset = 0;
129    stayAtPC = false;
130}
131
132BaseSimpleCPU::~BaseSimpleCPU()
133{
134}
135
136void
137BaseSimpleCPU::haltContext(ThreadID thread_num)
138{
139    // for now, these are equivalent
140    suspendContext(thread_num);
141}
142
143
144void
145BaseSimpleCPU::regStats()
146{
147    using namespace Stats;
148
149    BaseCPU::regStats();
150
151    numInsts
152        .name(name() + ".committedInsts")
153        .desc("Number of instructions committed")
154        ;
155
156    numOps
157        .name(name() + ".committedOps")
158        .desc("Number of ops (including micro ops) committed")
159        ;
160
161    numIntAluAccesses
162        .name(name() + ".num_int_alu_accesses")
163        .desc("Number of integer alu accesses")
164        ;
165
166    numFpAluAccesses
167        .name(name() + ".num_fp_alu_accesses")
168        .desc("Number of float alu accesses")
169        ;
170
171    numCallsReturns
172        .name(name() + ".num_func_calls")
173        .desc("number of times a function call or return occured")
174        ;
175
176    numCondCtrlInsts
177        .name(name() + ".num_conditional_control_insts")
178        .desc("number of instructions that are conditional controls")
179        ;
180
181    numIntInsts
182        .name(name() + ".num_int_insts")
183        .desc("number of integer instructions")
184        ;
185
186    numFpInsts
187        .name(name() + ".num_fp_insts")
188        .desc("number of float instructions")
189        ;
190
191    numIntRegReads
192        .name(name() + ".num_int_register_reads")
193        .desc("number of times the integer registers were read")
194        ;
195
196    numIntRegWrites
197        .name(name() + ".num_int_register_writes")
198        .desc("number of times the integer registers were written")
199        ;
200
201    numFpRegReads
202        .name(name() + ".num_fp_register_reads")
203        .desc("number of times the floating registers were read")
204        ;
205
206    numFpRegWrites
207        .name(name() + ".num_fp_register_writes")
208        .desc("number of times the floating registers were written")
209        ;
210
211    numCCRegReads
212        .name(name() + ".num_cc_register_reads")
213        .desc("number of times the CC registers were read")
214        .flags(nozero)
215        ;
216
217    numCCRegWrites
218        .name(name() + ".num_cc_register_writes")
219        .desc("number of times the CC registers were written")
220        .flags(nozero)
221        ;
222
223    numMemRefs
224        .name(name()+".num_mem_refs")
225        .desc("number of memory refs")
226        ;
227
228    numStoreInsts
229        .name(name() + ".num_store_insts")
230        .desc("Number of store instructions")
231        ;
232
233    numLoadInsts
234        .name(name() + ".num_load_insts")
235        .desc("Number of load instructions")
236        ;
237
238    notIdleFraction
239        .name(name() + ".not_idle_fraction")
240        .desc("Percentage of non-idle cycles")
241        ;
242
243    idleFraction
244        .name(name() + ".idle_fraction")
245        .desc("Percentage of idle cycles")
246        ;
247
248    numBusyCycles
249        .name(name() + ".num_busy_cycles")
250        .desc("Number of busy cycles")
251        ;
252
253    numIdleCycles
254        .name(name()+".num_idle_cycles")
255        .desc("Number of idle cycles")
256        ;
257
258    icacheStallCycles
259        .name(name() + ".icache_stall_cycles")
260        .desc("ICache total stall cycles")
261        .prereq(icacheStallCycles)
262        ;
263
264    dcacheStallCycles
265        .name(name() + ".dcache_stall_cycles")
266        .desc("DCache total stall cycles")
267        .prereq(dcacheStallCycles)
268        ;
269
270    statExecutedInstType
271        .init(Enums::Num_OpClass)
272        .name(name() + ".op_class")
273        .desc("Class of executed instruction")
274        .flags(total | pdf | dist)
275        ;
276    for (unsigned i = 0; i < Num_OpClasses; ++i) {
277        statExecutedInstType.subname(i, Enums::OpClassStrings[i]);
278    }
279
280    idleFraction = constant(1.0) - notIdleFraction;
281    numIdleCycles = idleFraction * numCycles;
282    numBusyCycles = (notIdleFraction)*numCycles;
283
284    numBranches
285        .name(name() + ".Branches")
286        .desc("Number of branches fetched")
287        .prereq(numBranches);
288
289    numPredictedBranches
290        .name(name() + ".predictedBranches")
291        .desc("Number of branches predicted as taken")
292        .prereq(numPredictedBranches);
293
294    numBranchMispred
295        .name(name() + ".BranchMispred")
296        .desc("Number of branch mispredictions")
297        .prereq(numBranchMispred);
298}
299
300void
301BaseSimpleCPU::resetStats()
302{
303//    startNumInst = numInst;
304     notIdleFraction = (_status != Idle);
305}
306
307void
308BaseSimpleCPU::serializeThread(ostream &os, ThreadID tid)
309{
310    assert(_status == Idle || _status == Running);
311    assert(tid == 0);
312
313    thread->serialize(os);
314}
315
316void
317BaseSimpleCPU::unserializeThread(Checkpoint *cp, const string &section,
318                                 ThreadID tid)
319{
320    if (tid != 0)
321        fatal("Trying to load more than one thread into a SimpleCPU\n");
322    thread->unserialize(cp, section);
323}
324
325void
326change_thread_state(ThreadID tid, int activate, int priority)
327{
328}
329
330Addr
331BaseSimpleCPU::dbg_vtophys(Addr addr)
332{
333    return vtophys(tc, addr);
334}
335
336void
337BaseSimpleCPU::wakeup()
338{
339    getAddrMonitor()->gotWakeup = true;
340
341    if (thread->status() != ThreadContext::Suspended)
342        return;
343
344    DPRINTF(Quiesce,"Suspended Processor awoke\n");
345    thread->activate();
346}
347
348void
349BaseSimpleCPU::checkForInterrupts()
350{
351    if (checkInterrupts(tc)) {
352        Fault interrupt = interrupts->getInterrupt(tc);
353
354        if (interrupt != NoFault) {
355            fetchOffset = 0;
356            interrupts->updateIntrInfo(tc);
357            interrupt->invoke(tc);
358            thread->decoder.reset();
359        }
360    }
361}
362
363
364void
365BaseSimpleCPU::setupFetchRequest(Request *req)
366{
367    Addr instAddr = thread->instAddr();
368
369    // set up memory request for instruction fetch
370    DPRINTF(Fetch, "Fetch: PC:%08p\n", instAddr);
371
372    Addr fetchPC = (instAddr & PCMask) + fetchOffset;
373    req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instMasterId(),
374            instAddr);
375}
376
377
378void
379BaseSimpleCPU::preExecute()
380{
381    // maintain $r0 semantics
382    thread->setIntReg(ZeroReg, 0);
383#if THE_ISA == ALPHA_ISA
384    thread->setFloatReg(ZeroReg, 0.0);
385#endif // ALPHA_ISA
386
387    // check for instruction-count-based events
388    comInstEventQueue[0]->serviceEvents(numInst);
389    system->instEventQueue.serviceEvents(system->totalNumInsts);
390
391    // decode the instruction
392    inst = gtoh(inst);
393
394    TheISA::PCState pcState = thread->pcState();
395
396    if (isRomMicroPC(pcState.microPC())) {
397        stayAtPC = false;
398        curStaticInst = microcodeRom.fetchMicroop(pcState.microPC(),
399                                                  curMacroStaticInst);
400    } else if (!curMacroStaticInst) {
401        //We're not in the middle of a macro instruction
402        StaticInstPtr instPtr = NULL;
403
404        TheISA::Decoder *decoder = &(thread->decoder);
405
406        //Predecode, ie bundle up an ExtMachInst
407        //If more fetch data is needed, pass it in.
408        Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset;
409        //if(decoder->needMoreBytes())
410            decoder->moreBytes(pcState, fetchPC, inst);
411        //else
412        //    decoder->process();
413
414        //Decode an instruction if one is ready. Otherwise, we'll have to
415        //fetch beyond the MachInst at the current pc.
416        instPtr = decoder->decode(pcState);
417        if (instPtr) {
418            stayAtPC = false;
419            thread->pcState(pcState);
420        } else {
421            stayAtPC = true;
422            fetchOffset += sizeof(MachInst);
423        }
424
425        //If we decoded an instruction and it's microcoded, start pulling
426        //out micro ops
427        if (instPtr && instPtr->isMacroop()) {
428            curMacroStaticInst = instPtr;
429            curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC());
430        } else {
431            curStaticInst = instPtr;
432        }
433    } else {
434        //Read the next micro op from the macro op
435        curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC());
436    }
437
438    //If we decoded an instruction this "tick", record information about it.
439    if (curStaticInst) {
440#if TRACING_ON
441        traceData = tracer->getInstRecord(curTick(), tc,
442                curStaticInst, thread->pcState(), curMacroStaticInst);
443
444        DPRINTF(Decode,"Decode: Decoded %s instruction: %#x\n",
445                curStaticInst->getName(), curStaticInst->machInst);
446#endif // TRACING_ON
447    }
448
449    if (branchPred && curStaticInst && curStaticInst->isControl()) {
450        // Use a fake sequence number since we only have one
451        // instruction in flight at the same time.
452        const InstSeqNum cur_sn(0);
453        const ThreadID tid(0);
454        pred_pc = thread->pcState();
455        const bool predict_taken(
456            branchPred->predict(curStaticInst, cur_sn, pred_pc, tid));
457
458        if (predict_taken)
459            ++numPredictedBranches;
460    }
461}
462
463void
464BaseSimpleCPU::postExecute()
465{
466    assert(curStaticInst);
467
468    TheISA::PCState pc = tc->pcState();
469    Addr instAddr = pc.instAddr();
470    if (FullSystem && thread->profile) {
471        bool usermode = TheISA::inUserMode(tc);
472        thread->profilePC = usermode ? 1 : instAddr;
473        ProfileNode *node = thread->profile->consume(tc, curStaticInst);
474        if (node)
475            thread->profileNode = node;
476    }
477
478    if (curStaticInst->isMemRef()) {
479        numMemRefs++;
480    }
481
482    if (curStaticInst->isLoad()) {
483        ++numLoad;
484        comLoadEventQueue[0]->serviceEvents(numLoad);
485    }
486
487    if (CPA::available()) {
488        CPA::cpa()->swAutoBegin(tc, pc.nextInstAddr());
489    }
490
491    if (curStaticInst->isControl()) {
492        ++numBranches;
493    }
494
495    /* Power model statistics */
496    //integer alu accesses
497    if (curStaticInst->isInteger()){
498        numIntAluAccesses++;
499        numIntInsts++;
500    }
501
502    //float alu accesses
503    if (curStaticInst->isFloating()){
504        numFpAluAccesses++;
505        numFpInsts++;
506    }
507
508    //number of function calls/returns to get window accesses
509    if (curStaticInst->isCall() || curStaticInst->isReturn()){
510        numCallsReturns++;
511    }
512
513    //the number of branch predictions that will be made
514    if (curStaticInst->isCondCtrl()){
515        numCondCtrlInsts++;
516    }
517
518    //result bus acceses
519    if (curStaticInst->isLoad()){
520        numLoadInsts++;
521    }
522
523    if (curStaticInst->isStore()){
524        numStoreInsts++;
525    }
526    /* End power model statistics */
527
528    statExecutedInstType[curStaticInst->opClass()]++;
529
530    if (FullSystem)
531        traceFunctions(instAddr);
532
533    if (traceData) {
534        traceData->dump();
535        delete traceData;
536        traceData = NULL;
537    }
538
539    // Call CPU instruction commit probes
540    probeInstCommit(curStaticInst);
541}
542
543void
544BaseSimpleCPU::advancePC(const Fault &fault)
545{
546    const bool branching(thread->pcState().branching());
547
548    //Since we're moving to a new pc, zero out the offset
549    fetchOffset = 0;
550    if (fault != NoFault) {
551        curMacroStaticInst = StaticInst::nullStaticInstPtr;
552        fault->invoke(tc, curStaticInst);
553        thread->decoder.reset();
554    } else {
555        if (curStaticInst) {
556            if (curStaticInst->isLastMicroop())
557                curMacroStaticInst = StaticInst::nullStaticInstPtr;
558            TheISA::PCState pcState = thread->pcState();
559            TheISA::advancePC(pcState, curStaticInst);
560            thread->pcState(pcState);
561        }
562    }
563
564    if (branchPred && curStaticInst && curStaticInst->isControl()) {
565        // Use a fake sequence number since we only have one
566        // instruction in flight at the same time.
567        const InstSeqNum cur_sn(0);
568        const ThreadID tid(0);
569
570        if (pred_pc == thread->pcState()) {
571            // Correctly predicted branch
572            branchPred->update(cur_sn, tid);
573        } else {
574            // Mis-predicted branch
575            branchPred->squash(cur_sn, pcState(),
576                               branching, tid);
577            ++numBranchMispred;
578        }
579    }
580}
581
582void
583BaseSimpleCPU::startup()
584{
585    BaseCPU::startup();
586    thread->startup();
587}
588