base.cc revision 10464:2a0fe8bca031 
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2002-2005 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 */
43
44#include "arch/kernel_stats.hh"
45#include "arch/stacktrace.hh"
46#include "arch/tlb.hh"
47#include "arch/utility.hh"
48#include "arch/vtophys.hh"
49#include "base/loader/symtab.hh"
50#include "base/cp_annotate.hh"
51#include "base/cprintf.hh"
52#include "base/inifile.hh"
53#include "base/misc.hh"
54#include "base/pollevent.hh"
55#include "base/trace.hh"
56#include "base/types.hh"
57#include "config/the_isa.hh"
58#include "cpu/simple/base.hh"
59#include "cpu/base.hh"
60#include "cpu/checker/cpu.hh"
61#include "cpu/checker/thread_context.hh"
62#include "cpu/exetrace.hh"
63#include "cpu/pred/bpred_unit.hh"
64#include "cpu/profile.hh"
65#include "cpu/simple_thread.hh"
66#include "cpu/smt.hh"
67#include "cpu/static_inst.hh"
68#include "cpu/thread_context.hh"
69#include "debug/Decode.hh"
70#include "debug/Fetch.hh"
71#include "debug/Quiesce.hh"
72#include "mem/mem_object.hh"
73#include "mem/packet.hh"
74#include "mem/request.hh"
75#include "params/BaseSimpleCPU.hh"
76#include "sim/byteswap.hh"
77#include "sim/debug.hh"
78#include "sim/faults.hh"
79#include "sim/full_system.hh"
80#include "sim/sim_events.hh"
81#include "sim/sim_object.hh"
82#include "sim/stats.hh"
83#include "sim/system.hh"
84
85using namespace std;
86using namespace TheISA;
87
88BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
89    : BaseCPU(p),
90      branchPred(p->branchPred),
91      traceData(NULL), thread(NULL)
92{
93    if (FullSystem)
94        thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb,
95                                  p->isa[0]);
96    else
97        thread = new SimpleThread(this, /* thread_num */ 0, p->system,
98                                  p->workload[0], p->itb, p->dtb, p->isa[0]);
99
100    thread->setStatus(ThreadContext::Halted);
101
102    tc = thread->getTC();
103
104    if (p->checker) {
105        BaseCPU *temp_checker = p->checker;
106        checker = dynamic_cast<CheckerCPU *>(temp_checker);
107        checker->setSystem(p->system);
108        // Manipulate thread context
109        ThreadContext *cpu_tc = tc;
110        tc = new CheckerThreadContext<ThreadContext>(cpu_tc, this->checker);
111    } else {
112        checker = NULL;
113    }
114
115    numInst = 0;
116    startNumInst = 0;
117    numOp = 0;
118    startNumOp = 0;
119    numLoad = 0;
120    startNumLoad = 0;
121    lastIcacheStall = 0;
122    lastDcacheStall = 0;
123
124    threadContexts.push_back(tc);
125
126
127    fetchOffset = 0;
128    stayAtPC = false;
129}
130
131BaseSimpleCPU::~BaseSimpleCPU()
132{
133}
134
135void
136BaseSimpleCPU::haltContext(ThreadID thread_num)
137{
138    // for now, these are equivalent
139    suspendContext(thread_num);
140}
141
142
143void
144BaseSimpleCPU::regStats()
145{
146    using namespace Stats;
147
148    BaseCPU::regStats();
149
150    numInsts
151        .name(name() + ".committedInsts")
152        .desc("Number of instructions committed")
153        ;
154
155    numOps
156        .name(name() + ".committedOps")
157        .desc("Number of ops (including micro ops) committed")
158        ;
159
160    numIntAluAccesses
161        .name(name() + ".num_int_alu_accesses")
162        .desc("Number of integer alu accesses")
163        ;
164
165    numFpAluAccesses
166        .name(name() + ".num_fp_alu_accesses")
167        .desc("Number of float alu accesses")
168        ;
169
170    numCallsReturns
171        .name(name() + ".num_func_calls")
172        .desc("number of times a function call or return occured")
173        ;
174
175    numCondCtrlInsts
176        .name(name() + ".num_conditional_control_insts")
177        .desc("number of instructions that are conditional controls")
178        ;
179
180    numIntInsts
181        .name(name() + ".num_int_insts")
182        .desc("number of integer instructions")
183        ;
184
185    numFpInsts
186        .name(name() + ".num_fp_insts")
187        .desc("number of float instructions")
188        ;
189
190    numIntRegReads
191        .name(name() + ".num_int_register_reads")
192        .desc("number of times the integer registers were read")
193        ;
194
195    numIntRegWrites
196        .name(name() + ".num_int_register_writes")
197        .desc("number of times the integer registers were written")
198        ;
199
200    numFpRegReads
201        .name(name() + ".num_fp_register_reads")
202        .desc("number of times the floating registers were read")
203        ;
204
205    numFpRegWrites
206        .name(name() + ".num_fp_register_writes")
207        .desc("number of times the floating registers were written")
208        ;
209
210    numCCRegReads
211        .name(name() + ".num_cc_register_reads")
212        .desc("number of times the CC registers were read")
213        .flags(nozero)
214        ;
215
216    numCCRegWrites
217        .name(name() + ".num_cc_register_writes")
218        .desc("number of times the CC registers were written")
219        .flags(nozero)
220        ;
221
222    numMemRefs
223        .name(name()+".num_mem_refs")
224        .desc("number of memory refs")
225        ;
226
227    numStoreInsts
228        .name(name() + ".num_store_insts")
229        .desc("Number of store instructions")
230        ;
231
232    numLoadInsts
233        .name(name() + ".num_load_insts")
234        .desc("Number of load instructions")
235        ;
236
237    notIdleFraction
238        .name(name() + ".not_idle_fraction")
239        .desc("Percentage of non-idle cycles")
240        ;
241
242    idleFraction
243        .name(name() + ".idle_fraction")
244        .desc("Percentage of idle cycles")
245        ;
246
247    numBusyCycles
248        .name(name() + ".num_busy_cycles")
249        .desc("Number of busy cycles")
250        ;
251
252    numIdleCycles
253        .name(name()+".num_idle_cycles")
254        .desc("Number of idle cycles")
255        ;
256
257    icacheStallCycles
258        .name(name() + ".icache_stall_cycles")
259        .desc("ICache total stall cycles")
260        .prereq(icacheStallCycles)
261        ;
262
263    dcacheStallCycles
264        .name(name() + ".dcache_stall_cycles")
265        .desc("DCache total stall cycles")
266        .prereq(dcacheStallCycles)
267        ;
268
269    icacheRetryCycles
270        .name(name() + ".icache_retry_cycles")
271        .desc("ICache total retry cycles")
272        .prereq(icacheRetryCycles)
273        ;
274
275    dcacheRetryCycles
276        .name(name() + ".dcache_retry_cycles")
277        .desc("DCache total retry cycles")
278        .prereq(dcacheRetryCycles)
279        ;
280
281    statExecutedInstType
282        .init(Enums::Num_OpClass)
283        .name(name() + ".op_class")
284        .desc("Class of executed instruction")
285        .flags(total | pdf | dist)
286        ;
287    for (unsigned i = 0; i < Num_OpClasses; ++i) {
288        statExecutedInstType.subname(i, Enums::OpClassStrings[i]);
289    }
290
291    idleFraction = constant(1.0) - notIdleFraction;
292    numIdleCycles = idleFraction * numCycles;
293    numBusyCycles = (notIdleFraction)*numCycles;
294
295    numBranches
296        .name(name() + ".Branches")
297        .desc("Number of branches fetched")
298        .prereq(numBranches);
299
300    numPredictedBranches
301        .name(name() + ".predictedBranches")
302        .desc("Number of branches predicted as taken")
303        .prereq(numPredictedBranches);
304
305    numBranchMispred
306        .name(name() + ".BranchMispred")
307        .desc("Number of branch mispredictions")
308        .prereq(numBranchMispred);
309}
310
311void
312BaseSimpleCPU::resetStats()
313{
314//    startNumInst = numInst;
315     notIdleFraction = (_status != Idle);
316}
317
318void
319BaseSimpleCPU::serializeThread(ostream &os, ThreadID tid)
320{
321    assert(_status == Idle || _status == Running);
322    assert(tid == 0);
323
324    thread->serialize(os);
325}
326
327void
328BaseSimpleCPU::unserializeThread(Checkpoint *cp, const string &section,
329                                 ThreadID tid)
330{
331    if (tid != 0)
332        fatal("Trying to load more than one thread into a SimpleCPU\n");
333    thread->unserialize(cp, section);
334}
335
336void
337change_thread_state(ThreadID tid, int activate, int priority)
338{
339}
340
341Addr
342BaseSimpleCPU::dbg_vtophys(Addr addr)
343{
344    return vtophys(tc, addr);
345}
346
347void
348BaseSimpleCPU::wakeup()
349{
350    if (thread->status() != ThreadContext::Suspended)
351        return;
352
353    DPRINTF(Quiesce,"Suspended Processor awoke\n");
354    thread->activate();
355}
356
357void
358BaseSimpleCPU::checkForInterrupts()
359{
360    if (checkInterrupts(tc)) {
361        Fault interrupt = interrupts->getInterrupt(tc);
362
363        if (interrupt != NoFault) {
364            fetchOffset = 0;
365            interrupts->updateIntrInfo(tc);
366            interrupt->invoke(tc);
367            thread->decoder.reset();
368        }
369    }
370}
371
372
373void
374BaseSimpleCPU::setupFetchRequest(Request *req)
375{
376    Addr instAddr = thread->instAddr();
377
378    // set up memory request for instruction fetch
379    DPRINTF(Fetch, "Fetch: PC:%08p\n", instAddr);
380
381    Addr fetchPC = (instAddr & PCMask) + fetchOffset;
382    req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instMasterId(),
383            instAddr);
384}
385
386
387void
388BaseSimpleCPU::preExecute()
389{
390    // maintain $r0 semantics
391    thread->setIntReg(ZeroReg, 0);
392#if THE_ISA == ALPHA_ISA
393    thread->setFloatReg(ZeroReg, 0.0);
394#endif // ALPHA_ISA
395
396    // check for instruction-count-based events
397    comInstEventQueue[0]->serviceEvents(numInst);
398    system->instEventQueue.serviceEvents(system->totalNumInsts);
399
400    // decode the instruction
401    inst = gtoh(inst);
402
403    TheISA::PCState pcState = thread->pcState();
404
405    if (isRomMicroPC(pcState.microPC())) {
406        stayAtPC = false;
407        curStaticInst = microcodeRom.fetchMicroop(pcState.microPC(),
408                                                  curMacroStaticInst);
409    } else if (!curMacroStaticInst) {
410        //We're not in the middle of a macro instruction
411        StaticInstPtr instPtr = NULL;
412
413        TheISA::Decoder *decoder = &(thread->decoder);
414
415        //Predecode, ie bundle up an ExtMachInst
416        //If more fetch data is needed, pass it in.
417        Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset;
418        //if(decoder->needMoreBytes())
419            decoder->moreBytes(pcState, fetchPC, inst);
420        //else
421        //    decoder->process();
422
423        //Decode an instruction if one is ready. Otherwise, we'll have to
424        //fetch beyond the MachInst at the current pc.
425        instPtr = decoder->decode(pcState);
426        if (instPtr) {
427            stayAtPC = false;
428            thread->pcState(pcState);
429        } else {
430            stayAtPC = true;
431            fetchOffset += sizeof(MachInst);
432        }
433
434        //If we decoded an instruction and it's microcoded, start pulling
435        //out micro ops
436        if (instPtr && instPtr->isMacroop()) {
437            curMacroStaticInst = instPtr;
438            curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC());
439        } else {
440            curStaticInst = instPtr;
441        }
442    } else {
443        //Read the next micro op from the macro op
444        curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC());
445    }
446
447    //If we decoded an instruction this "tick", record information about it.
448    if (curStaticInst) {
449#if TRACING_ON
450        traceData = tracer->getInstRecord(curTick(), tc,
451                curStaticInst, thread->pcState(), curMacroStaticInst);
452
453        DPRINTF(Decode,"Decode: Decoded %s instruction: %#x\n",
454                curStaticInst->getName(), curStaticInst->machInst);
455#endif // TRACING_ON
456    }
457
458    if (branchPred && curStaticInst && curStaticInst->isControl()) {
459        // Use a fake sequence number since we only have one
460        // instruction in flight at the same time.
461        const InstSeqNum cur_sn(0);
462        const ThreadID tid(0);
463        pred_pc = thread->pcState();
464        const bool predict_taken(
465            branchPred->predict(curStaticInst, cur_sn, pred_pc, tid));
466
467        if (predict_taken)
468            ++numPredictedBranches;
469    }
470}
471
472void
473BaseSimpleCPU::postExecute()
474{
475    assert(curStaticInst);
476
477    TheISA::PCState pc = tc->pcState();
478    Addr instAddr = pc.instAddr();
479    if (FullSystem && thread->profile) {
480        bool usermode = TheISA::inUserMode(tc);
481        thread->profilePC = usermode ? 1 : instAddr;
482        ProfileNode *node = thread->profile->consume(tc, curStaticInst);
483        if (node)
484            thread->profileNode = node;
485    }
486
487    if (curStaticInst->isMemRef()) {
488        numMemRefs++;
489    }
490
491    if (curStaticInst->isLoad()) {
492        ++numLoad;
493        comLoadEventQueue[0]->serviceEvents(numLoad);
494    }
495
496    if (CPA::available()) {
497        CPA::cpa()->swAutoBegin(tc, pc.nextInstAddr());
498    }
499
500    if (curStaticInst->isControl()) {
501        ++numBranches;
502    }
503
504    /* Power model statistics */
505    //integer alu accesses
506    if (curStaticInst->isInteger()){
507        numIntAluAccesses++;
508        numIntInsts++;
509    }
510
511    //float alu accesses
512    if (curStaticInst->isFloating()){
513        numFpAluAccesses++;
514        numFpInsts++;
515    }
516
517    //number of function calls/returns to get window accesses
518    if (curStaticInst->isCall() || curStaticInst->isReturn()){
519        numCallsReturns++;
520    }
521
522    //the number of branch predictions that will be made
523    if (curStaticInst->isCondCtrl()){
524        numCondCtrlInsts++;
525    }
526
527    //result bus acceses
528    if (curStaticInst->isLoad()){
529        numLoadInsts++;
530    }
531
532    if (curStaticInst->isStore()){
533        numStoreInsts++;
534    }
535    /* End power model statistics */
536
537    statExecutedInstType[curStaticInst->opClass()]++;
538
539    if (FullSystem)
540        traceFunctions(instAddr);
541
542    if (traceData) {
543        traceData->dump();
544        delete traceData;
545        traceData = NULL;
546    }
547
548    // Call CPU instruction commit probes
549    probeInstCommit(curStaticInst);
550}
551
552void
553BaseSimpleCPU::advancePC(const Fault &fault)
554{
555    const bool branching(thread->pcState().branching());
556
557    //Since we're moving to a new pc, zero out the offset
558    fetchOffset = 0;
559    if (fault != NoFault) {
560        curMacroStaticInst = StaticInst::nullStaticInstPtr;
561        fault->invoke(tc, curStaticInst);
562        thread->decoder.reset();
563    } else {
564        if (curStaticInst) {
565            if (curStaticInst->isLastMicroop())
566                curMacroStaticInst = StaticInst::nullStaticInstPtr;
567            TheISA::PCState pcState = thread->pcState();
568            TheISA::advancePC(pcState, curStaticInst);
569            thread->pcState(pcState);
570        }
571    }
572
573    if (branchPred && curStaticInst && curStaticInst->isControl()) {
574        // Use a fake sequence number since we only have one
575        // instruction in flight at the same time.
576        const InstSeqNum cur_sn(0);
577        const ThreadID tid(0);
578
579        if (pred_pc == thread->pcState()) {
580            // Correctly predicted branch
581            branchPred->update(cur_sn, tid);
582        } else {
583            // Mis-predicted branch
584            branchPred->squash(cur_sn, pcState(),
585                               branching, tid);
586            ++numBranchMispred;
587        }
588    }
589}
590
591void
592BaseSimpleCPU::startup()
593{
594    BaseCPU::startup();
595    thread->startup();
596}
597