base.cc revision 10061:3b0d0c988ed6 
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2002-2005 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 */
43
44#include "arch/kernel_stats.hh"
45#include "arch/stacktrace.hh"
46#include "arch/tlb.hh"
47#include "arch/utility.hh"
48#include "arch/vtophys.hh"
49#include "base/loader/symtab.hh"
50#include "base/cp_annotate.hh"
51#include "base/cprintf.hh"
52#include "base/inifile.hh"
53#include "base/misc.hh"
54#include "base/pollevent.hh"
55#include "base/trace.hh"
56#include "base/types.hh"
57#include "config/the_isa.hh"
58#include "cpu/simple/base.hh"
59#include "cpu/base.hh"
60#include "cpu/checker/cpu.hh"
61#include "cpu/checker/thread_context.hh"
62#include "cpu/exetrace.hh"
63#include "cpu/pred/bpred_unit.hh"
64#include "cpu/profile.hh"
65#include "cpu/simple_thread.hh"
66#include "cpu/smt.hh"
67#include "cpu/static_inst.hh"
68#include "cpu/thread_context.hh"
69#include "debug/Decode.hh"
70#include "debug/Fetch.hh"
71#include "debug/Quiesce.hh"
72#include "mem/mem_object.hh"
73#include "mem/packet.hh"
74#include "mem/request.hh"
75#include "params/BaseSimpleCPU.hh"
76#include "sim/byteswap.hh"
77#include "sim/debug.hh"
78#include "sim/faults.hh"
79#include "sim/full_system.hh"
80#include "sim/sim_events.hh"
81#include "sim/sim_object.hh"
82#include "sim/stats.hh"
83#include "sim/system.hh"
84
85using namespace std;
86using namespace TheISA;
87
88BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
89    : BaseCPU(p),
90      branchPred(p->branchPred),
91      traceData(NULL), thread(NULL)
92{
93    if (FullSystem)
94        thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb,
95                                  p->isa[0]);
96    else
97        thread = new SimpleThread(this, /* thread_num */ 0, p->system,
98                                  p->workload[0], p->itb, p->dtb, p->isa[0]);
99
100    thread->setStatus(ThreadContext::Halted);
101
102    tc = thread->getTC();
103
104    if (p->checker) {
105        BaseCPU *temp_checker = p->checker;
106        checker = dynamic_cast<CheckerCPU *>(temp_checker);
107        checker->setSystem(p->system);
108        // Manipulate thread context
109        ThreadContext *cpu_tc = tc;
110        tc = new CheckerThreadContext<ThreadContext>(cpu_tc, this->checker);
111    } else {
112        checker = NULL;
113    }
114
115    numInst = 0;
116    startNumInst = 0;
117    numOp = 0;
118    startNumOp = 0;
119    numLoad = 0;
120    startNumLoad = 0;
121    lastIcacheStall = 0;
122    lastDcacheStall = 0;
123
124    threadContexts.push_back(tc);
125
126
127    fetchOffset = 0;
128    stayAtPC = false;
129}
130
131BaseSimpleCPU::~BaseSimpleCPU()
132{
133}
134
135void
136BaseSimpleCPU::deallocateContext(ThreadID thread_num)
137{
138    // for now, these are equivalent
139    suspendContext(thread_num);
140}
141
142
143void
144BaseSimpleCPU::haltContext(ThreadID thread_num)
145{
146    // for now, these are equivalent
147    suspendContext(thread_num);
148}
149
150
151void
152BaseSimpleCPU::regStats()
153{
154    using namespace Stats;
155
156    BaseCPU::regStats();
157
158    numInsts
159        .name(name() + ".committedInsts")
160        .desc("Number of instructions committed")
161        ;
162
163    numOps
164        .name(name() + ".committedOps")
165        .desc("Number of ops (including micro ops) committed")
166        ;
167
168    numIntAluAccesses
169        .name(name() + ".num_int_alu_accesses")
170        .desc("Number of integer alu accesses")
171        ;
172
173    numFpAluAccesses
174        .name(name() + ".num_fp_alu_accesses")
175        .desc("Number of float alu accesses")
176        ;
177
178    numCallsReturns
179        .name(name() + ".num_func_calls")
180        .desc("number of times a function call or return occured")
181        ;
182
183    numCondCtrlInsts
184        .name(name() + ".num_conditional_control_insts")
185        .desc("number of instructions that are conditional controls")
186        ;
187
188    numIntInsts
189        .name(name() + ".num_int_insts")
190        .desc("number of integer instructions")
191        ;
192
193    numFpInsts
194        .name(name() + ".num_fp_insts")
195        .desc("number of float instructions")
196        ;
197
198    numIntRegReads
199        .name(name() + ".num_int_register_reads")
200        .desc("number of times the integer registers were read")
201        ;
202
203    numIntRegWrites
204        .name(name() + ".num_int_register_writes")
205        .desc("number of times the integer registers were written")
206        ;
207
208    numFpRegReads
209        .name(name() + ".num_fp_register_reads")
210        .desc("number of times the floating registers were read")
211        ;
212
213    numFpRegWrites
214        .name(name() + ".num_fp_register_writes")
215        .desc("number of times the floating registers were written")
216        ;
217
218    numCCRegReads
219        .name(name() + ".num_cc_register_reads")
220        .desc("number of times the CC registers were read")
221        .flags(nozero)
222        ;
223
224    numCCRegWrites
225        .name(name() + ".num_cc_register_writes")
226        .desc("number of times the CC registers were written")
227        .flags(nozero)
228        ;
229
230    numMemRefs
231        .name(name()+".num_mem_refs")
232        .desc("number of memory refs")
233        ;
234
235    numStoreInsts
236        .name(name() + ".num_store_insts")
237        .desc("Number of store instructions")
238        ;
239
240    numLoadInsts
241        .name(name() + ".num_load_insts")
242        .desc("Number of load instructions")
243        ;
244
245    notIdleFraction
246        .name(name() + ".not_idle_fraction")
247        .desc("Percentage of non-idle cycles")
248        ;
249
250    idleFraction
251        .name(name() + ".idle_fraction")
252        .desc("Percentage of idle cycles")
253        ;
254
255    numBusyCycles
256        .name(name() + ".num_busy_cycles")
257        .desc("Number of busy cycles")
258        ;
259
260    numIdleCycles
261        .name(name()+".num_idle_cycles")
262        .desc("Number of idle cycles")
263        ;
264
265    icacheStallCycles
266        .name(name() + ".icache_stall_cycles")
267        .desc("ICache total stall cycles")
268        .prereq(icacheStallCycles)
269        ;
270
271    dcacheStallCycles
272        .name(name() + ".dcache_stall_cycles")
273        .desc("DCache total stall cycles")
274        .prereq(dcacheStallCycles)
275        ;
276
277    icacheRetryCycles
278        .name(name() + ".icache_retry_cycles")
279        .desc("ICache total retry cycles")
280        .prereq(icacheRetryCycles)
281        ;
282
283    dcacheRetryCycles
284        .name(name() + ".dcache_retry_cycles")
285        .desc("DCache total retry cycles")
286        .prereq(dcacheRetryCycles)
287        ;
288
289    idleFraction = constant(1.0) - notIdleFraction;
290    numIdleCycles = idleFraction * numCycles;
291    numBusyCycles = (notIdleFraction)*numCycles;
292
293    numBranches
294        .name(name() + ".Branches")
295        .desc("Number of branches fetched")
296        .prereq(numBranches);
297
298    numPredictedBranches
299        .name(name() + ".predictedBranches")
300        .desc("Number of branches predicted as taken")
301        .prereq(numPredictedBranches);
302
303    numBranchMispred
304        .name(name() + ".BranchMispred")
305        .desc("Number of branch mispredictions")
306        .prereq(numBranchMispred);
307}
308
309void
310BaseSimpleCPU::resetStats()
311{
312//    startNumInst = numInst;
313     notIdleFraction = (_status != Idle);
314}
315
316void
317BaseSimpleCPU::serializeThread(ostream &os, ThreadID tid)
318{
319    assert(_status == Idle || _status == Running);
320    assert(tid == 0);
321
322    thread->serialize(os);
323}
324
325void
326BaseSimpleCPU::unserializeThread(Checkpoint *cp, const string &section,
327                                 ThreadID tid)
328{
329    if (tid != 0)
330        fatal("Trying to load more than one thread into a SimpleCPU\n");
331    thread->unserialize(cp, section);
332}
333
334void
335change_thread_state(ThreadID tid, int activate, int priority)
336{
337}
338
339Addr
340BaseSimpleCPU::dbg_vtophys(Addr addr)
341{
342    return vtophys(tc, addr);
343}
344
345void
346BaseSimpleCPU::wakeup()
347{
348    if (thread->status() != ThreadContext::Suspended)
349        return;
350
351    DPRINTF(Quiesce,"Suspended Processor awoke\n");
352    thread->activate();
353}
354
355void
356BaseSimpleCPU::checkForInterrupts()
357{
358    if (checkInterrupts(tc)) {
359        Fault interrupt = interrupts->getInterrupt(tc);
360
361        if (interrupt != NoFault) {
362            fetchOffset = 0;
363            interrupts->updateIntrInfo(tc);
364            interrupt->invoke(tc);
365            thread->decoder.reset();
366        }
367    }
368}
369
370
371void
372BaseSimpleCPU::setupFetchRequest(Request *req)
373{
374    Addr instAddr = thread->instAddr();
375
376    // set up memory request for instruction fetch
377    DPRINTF(Fetch, "Fetch: PC:%08p\n", instAddr);
378
379    Addr fetchPC = (instAddr & PCMask) + fetchOffset;
380    req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instMasterId(),
381            instAddr);
382}
383
384
385void
386BaseSimpleCPU::preExecute()
387{
388    // maintain $r0 semantics
389    thread->setIntReg(ZeroReg, 0);
390#if THE_ISA == ALPHA_ISA
391    thread->setFloatReg(ZeroReg, 0.0);
392#endif // ALPHA_ISA
393
394    // check for instruction-count-based events
395    comInstEventQueue[0]->serviceEvents(numInst);
396    system->instEventQueue.serviceEvents(system->totalNumInsts);
397
398    // decode the instruction
399    inst = gtoh(inst);
400
401    TheISA::PCState pcState = thread->pcState();
402
403    if (isRomMicroPC(pcState.microPC())) {
404        stayAtPC = false;
405        curStaticInst = microcodeRom.fetchMicroop(pcState.microPC(),
406                                                  curMacroStaticInst);
407    } else if (!curMacroStaticInst) {
408        //We're not in the middle of a macro instruction
409        StaticInstPtr instPtr = NULL;
410
411        TheISA::Decoder *decoder = &(thread->decoder);
412
413        //Predecode, ie bundle up an ExtMachInst
414        //If more fetch data is needed, pass it in.
415        Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset;
416        //if(decoder->needMoreBytes())
417            decoder->moreBytes(pcState, fetchPC, inst);
418        //else
419        //    decoder->process();
420
421        //Decode an instruction if one is ready. Otherwise, we'll have to
422        //fetch beyond the MachInst at the current pc.
423        instPtr = decoder->decode(pcState);
424        if (instPtr) {
425            stayAtPC = false;
426            thread->pcState(pcState);
427        } else {
428            stayAtPC = true;
429            fetchOffset += sizeof(MachInst);
430        }
431
432        //If we decoded an instruction and it's microcoded, start pulling
433        //out micro ops
434        if (instPtr && instPtr->isMacroop()) {
435            curMacroStaticInst = instPtr;
436            curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC());
437        } else {
438            curStaticInst = instPtr;
439        }
440    } else {
441        //Read the next micro op from the macro op
442        curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC());
443    }
444
445    //If we decoded an instruction this "tick", record information about it.
446    if (curStaticInst) {
447#if TRACING_ON
448        traceData = tracer->getInstRecord(curTick(), tc,
449                curStaticInst, thread->pcState(), curMacroStaticInst);
450
451        DPRINTF(Decode,"Decode: Decoded %s instruction: %#x\n",
452                curStaticInst->getName(), curStaticInst->machInst);
453#endif // TRACING_ON
454    }
455
456    if (branchPred && curStaticInst && curStaticInst->isControl()) {
457        // Use a fake sequence number since we only have one
458        // instruction in flight at the same time.
459        const InstSeqNum cur_sn(0);
460        const ThreadID tid(0);
461        pred_pc = thread->pcState();
462        const bool predict_taken(
463            branchPred->predict(curStaticInst, cur_sn, pred_pc, tid));
464
465        if (predict_taken)
466            ++numPredictedBranches;
467    }
468}
469
470void
471BaseSimpleCPU::postExecute()
472{
473    assert(curStaticInst);
474
475    TheISA::PCState pc = tc->pcState();
476    Addr instAddr = pc.instAddr();
477    if (FullSystem && thread->profile) {
478        bool usermode = TheISA::inUserMode(tc);
479        thread->profilePC = usermode ? 1 : instAddr;
480        ProfileNode *node = thread->profile->consume(tc, curStaticInst);
481        if (node)
482            thread->profileNode = node;
483    }
484
485    if (curStaticInst->isMemRef()) {
486        numMemRefs++;
487    }
488
489    if (curStaticInst->isLoad()) {
490        ++numLoad;
491        comLoadEventQueue[0]->serviceEvents(numLoad);
492    }
493
494    if (CPA::available()) {
495        CPA::cpa()->swAutoBegin(tc, pc.nextInstAddr());
496    }
497
498    if (curStaticInst->isControl()) {
499        ++numBranches;
500    }
501
502    /* Power model statistics */
503    //integer alu accesses
504    if (curStaticInst->isInteger()){
505        numIntAluAccesses++;
506        numIntInsts++;
507    }
508
509    //float alu accesses
510    if (curStaticInst->isFloating()){
511        numFpAluAccesses++;
512        numFpInsts++;
513    }
514
515    //number of function calls/returns to get window accesses
516    if (curStaticInst->isCall() || curStaticInst->isReturn()){
517        numCallsReturns++;
518    }
519
520    //the number of branch predictions that will be made
521    if (curStaticInst->isCondCtrl()){
522        numCondCtrlInsts++;
523    }
524
525    //result bus acceses
526    if (curStaticInst->isLoad()){
527        numLoadInsts++;
528    }
529
530    if (curStaticInst->isStore()){
531        numStoreInsts++;
532    }
533    /* End power model statistics */
534
535    if (FullSystem)
536        traceFunctions(instAddr);
537
538    if (traceData) {
539        traceData->dump();
540        delete traceData;
541        traceData = NULL;
542    }
543}
544
545void
546BaseSimpleCPU::advancePC(Fault fault)
547{
548    const bool branching(thread->pcState().branching());
549
550    //Since we're moving to a new pc, zero out the offset
551    fetchOffset = 0;
552    if (fault != NoFault) {
553        curMacroStaticInst = StaticInst::nullStaticInstPtr;
554        fault->invoke(tc, curStaticInst);
555        thread->decoder.reset();
556    } else {
557        if (curStaticInst) {
558            if (curStaticInst->isLastMicroop())
559                curMacroStaticInst = StaticInst::nullStaticInstPtr;
560            TheISA::PCState pcState = thread->pcState();
561            TheISA::advancePC(pcState, curStaticInst);
562            thread->pcState(pcState);
563        }
564    }
565
566    if (branchPred && curStaticInst && curStaticInst->isControl()) {
567        // Use a fake sequence number since we only have one
568        // instruction in flight at the same time.
569        const InstSeqNum cur_sn(0);
570        const ThreadID tid(0);
571
572        if (pred_pc == thread->pcState()) {
573            // Correctly predicted branch
574            branchPred->update(cur_sn, tid);
575        } else {
576            // Mis-predicted branch
577            branchPred->squash(cur_sn, pcState(),
578                               branching, tid);
579            ++numBranchMispred;
580        }
581    }
582}
583
584void
585BaseSimpleCPU::startup()
586{
587    BaseCPU::startup();
588    thread->startup();
589}
590