base.cc revision 9983
12SN/A/* 29448SAndreas.Sandberg@ARM.com * Copyright (c) 2010-2012 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47338SAli.Saidi@ARM.com * All rights reserved 57338SAli.Saidi@ARM.com * 67338SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 77338SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 87338SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 97338SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 107338SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 117338SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 127338SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 137338SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 147338SAli.Saidi@ARM.com * 151762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422SN/A */ 432SN/A 448779Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 458779Sgblack@eecs.umich.edu#include "arch/stacktrace.hh" 468779Sgblack@eecs.umich.edu#include "arch/tlb.hh" 472439SN/A#include "arch/utility.hh" 488779Sgblack@eecs.umich.edu#include "arch/vtophys.hh" 498229Snate@binkert.org#include "base/loader/symtab.hh" 506216Snate@binkert.org#include "base/cp_annotate.hh" 51146SN/A#include "base/cprintf.hh" 52146SN/A#include "base/inifile.hh" 53146SN/A#include "base/misc.hh" 54146SN/A#include "base/pollevent.hh" 55146SN/A#include "base/trace.hh" 566216Snate@binkert.org#include "base/types.hh" 576658Snate@binkert.org#include "config/the_isa.hh" 588229Snate@binkert.org#include "cpu/simple/base.hh" 591717SN/A#include "cpu/base.hh" 608887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 618887Sgeoffrey.blake@arm.com#include "cpu/checker/thread_context.hh" 62146SN/A#include "cpu/exetrace.hh" 631977SN/A#include "cpu/profile.hh" 642683Sktlim@umich.edu#include "cpu/simple_thread.hh" 651717SN/A#include "cpu/smt.hh" 66146SN/A#include "cpu/static_inst.hh" 672683Sktlim@umich.edu#include "cpu/thread_context.hh" 688232Snate@binkert.org#include "debug/Decode.hh" 698232Snate@binkert.org#include "debug/Fetch.hh" 708232Snate@binkert.org#include "debug/Quiesce.hh" 718779Sgblack@eecs.umich.edu#include "mem/mem_object.hh" 723348Sbinkertn@umich.edu#include "mem/packet.hh" 736105Ssteve.reinhardt@amd.com#include "mem/request.hh" 746216Snate@binkert.org#include "params/BaseSimpleCPU.hh" 752036SN/A#include "sim/byteswap.hh" 76146SN/A#include "sim/debug.hh" 778817Sgblack@eecs.umich.edu#include "sim/faults.hh" 788793Sgblack@eecs.umich.edu#include "sim/full_system.hh" 7956SN/A#include "sim/sim_events.hh" 8056SN/A#include "sim/sim_object.hh" 81695SN/A#include "sim/stats.hh" 822901Ssaidi@eecs.umich.edu#include "sim/system.hh" 832SN/A 842SN/Ausing namespace std; 852449SN/Ausing namespace TheISA; 861355SN/A 875529Snate@binkert.orgBaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p) 889023Sgblack@eecs.umich.edu : BaseCPU(p), traceData(NULL), thread(NULL) 89224SN/A{ 908793Sgblack@eecs.umich.edu if (FullSystem) 919384SAndreas.Sandberg@arm.com thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb, 929384SAndreas.Sandberg@arm.com p->isa[0]); 938793Sgblack@eecs.umich.edu else 948820Sgblack@eecs.umich.edu thread = new SimpleThread(this, /* thread_num */ 0, p->system, 959384SAndreas.Sandberg@arm.com p->workload[0], p->itb, p->dtb, p->isa[0]); 962SN/A 976029Ssteve.reinhardt@amd.com thread->setStatus(ThreadContext::Halted); 982672Sktlim@umich.edu 992683Sktlim@umich.edu tc = thread->getTC(); 1002SN/A 1018733Sgeoffrey.blake@arm.com if (p->checker) { 1028733Sgeoffrey.blake@arm.com BaseCPU *temp_checker = p->checker; 1038733Sgeoffrey.blake@arm.com checker = dynamic_cast<CheckerCPU *>(temp_checker); 1048733Sgeoffrey.blake@arm.com checker->setSystem(p->system); 1058733Sgeoffrey.blake@arm.com // Manipulate thread context 1068733Sgeoffrey.blake@arm.com ThreadContext *cpu_tc = tc; 1078733Sgeoffrey.blake@arm.com tc = new CheckerThreadContext<ThreadContext>(cpu_tc, this->checker); 1088733Sgeoffrey.blake@arm.com } else { 1098733Sgeoffrey.blake@arm.com checker = NULL; 1108733Sgeoffrey.blake@arm.com } 1118733Sgeoffrey.blake@arm.com 1122SN/A numInst = 0; 113334SN/A startNumInst = 0; 1148834Satgutier@umich.edu numOp = 0; 1158834Satgutier@umich.edu startNumOp = 0; 116140SN/A numLoad = 0; 117334SN/A startNumLoad = 0; 1182SN/A lastIcacheStall = 0; 1192SN/A lastDcacheStall = 0; 1202SN/A 1212680Sktlim@umich.edu threadContexts.push_back(tc); 1224377Sgblack@eecs.umich.edu 1235169Ssaidi@eecs.umich.edu 1244377Sgblack@eecs.umich.edu fetchOffset = 0; 1254377Sgblack@eecs.umich.edu stayAtPC = false; 1262SN/A} 1272SN/A 1282623SN/ABaseSimpleCPU::~BaseSimpleCPU() 1292SN/A{ 1302SN/A} 1312SN/A 132180SN/Avoid 1338737Skoansin.tan@gmail.comBaseSimpleCPU::deallocateContext(ThreadID thread_num) 134393SN/A{ 135393SN/A // for now, these are equivalent 136393SN/A suspendContext(thread_num); 137393SN/A} 138384SN/A 139384SN/A 140393SN/Avoid 1418737Skoansin.tan@gmail.comBaseSimpleCPU::haltContext(ThreadID thread_num) 142393SN/A{ 143393SN/A // for now, these are equivalent 144393SN/A suspendContext(thread_num); 145393SN/A} 146384SN/A 147189SN/A 148189SN/Avoid 1492623SN/ABaseSimpleCPU::regStats() 1502SN/A{ 151729SN/A using namespace Stats; 152334SN/A 1532SN/A BaseCPU::regStats(); 1542SN/A 1552SN/A numInsts 1568834Satgutier@umich.edu .name(name() + ".committedInsts") 1578834Satgutier@umich.edu .desc("Number of instructions committed") 1588834Satgutier@umich.edu ; 1598834Satgutier@umich.edu 1608834Satgutier@umich.edu numOps 1618834Satgutier@umich.edu .name(name() + ".committedOps") 1628834Satgutier@umich.edu .desc("Number of ops (including micro ops) committed") 1632SN/A ; 1642SN/A 1657897Shestness@cs.utexas.edu numIntAluAccesses 1667897Shestness@cs.utexas.edu .name(name() + ".num_int_alu_accesses") 1677897Shestness@cs.utexas.edu .desc("Number of integer alu accesses") 1687897Shestness@cs.utexas.edu ; 1697897Shestness@cs.utexas.edu 1707897Shestness@cs.utexas.edu numFpAluAccesses 1717897Shestness@cs.utexas.edu .name(name() + ".num_fp_alu_accesses") 1727897Shestness@cs.utexas.edu .desc("Number of float alu accesses") 1737897Shestness@cs.utexas.edu ; 1747897Shestness@cs.utexas.edu 1757897Shestness@cs.utexas.edu numCallsReturns 1767897Shestness@cs.utexas.edu .name(name() + ".num_func_calls") 1777897Shestness@cs.utexas.edu .desc("number of times a function call or return occured") 1787897Shestness@cs.utexas.edu ; 1797897Shestness@cs.utexas.edu 1807897Shestness@cs.utexas.edu numCondCtrlInsts 1817897Shestness@cs.utexas.edu .name(name() + ".num_conditional_control_insts") 1827897Shestness@cs.utexas.edu .desc("number of instructions that are conditional controls") 1837897Shestness@cs.utexas.edu ; 1847897Shestness@cs.utexas.edu 1857897Shestness@cs.utexas.edu numIntInsts 1867897Shestness@cs.utexas.edu .name(name() + ".num_int_insts") 1877897Shestness@cs.utexas.edu .desc("number of integer instructions") 1887897Shestness@cs.utexas.edu ; 1897897Shestness@cs.utexas.edu 1907897Shestness@cs.utexas.edu numFpInsts 1917897Shestness@cs.utexas.edu .name(name() + ".num_fp_insts") 1927897Shestness@cs.utexas.edu .desc("number of float instructions") 1937897Shestness@cs.utexas.edu ; 1947897Shestness@cs.utexas.edu 1957897Shestness@cs.utexas.edu numIntRegReads 1967897Shestness@cs.utexas.edu .name(name() + ".num_int_register_reads") 1977897Shestness@cs.utexas.edu .desc("number of times the integer registers were read") 1987897Shestness@cs.utexas.edu ; 1997897Shestness@cs.utexas.edu 2007897Shestness@cs.utexas.edu numIntRegWrites 2017897Shestness@cs.utexas.edu .name(name() + ".num_int_register_writes") 2027897Shestness@cs.utexas.edu .desc("number of times the integer registers were written") 2037897Shestness@cs.utexas.edu ; 2047897Shestness@cs.utexas.edu 2057897Shestness@cs.utexas.edu numFpRegReads 2067897Shestness@cs.utexas.edu .name(name() + ".num_fp_register_reads") 2077897Shestness@cs.utexas.edu .desc("number of times the floating registers were read") 2087897Shestness@cs.utexas.edu ; 2097897Shestness@cs.utexas.edu 2107897Shestness@cs.utexas.edu numFpRegWrites 2117897Shestness@cs.utexas.edu .name(name() + ".num_fp_register_writes") 2127897Shestness@cs.utexas.edu .desc("number of times the floating registers were written") 2137897Shestness@cs.utexas.edu ; 2147897Shestness@cs.utexas.edu 2159920Syasuko.eckert@amd.com numCCRegReads 2169920Syasuko.eckert@amd.com .name(name() + ".num_cc_register_reads") 2179920Syasuko.eckert@amd.com .desc("number of times the CC registers were read") 2189920Syasuko.eckert@amd.com .flags(nozero) 2199920Syasuko.eckert@amd.com ; 2209920Syasuko.eckert@amd.com 2219920Syasuko.eckert@amd.com numCCRegWrites 2229920Syasuko.eckert@amd.com .name(name() + ".num_cc_register_writes") 2239920Syasuko.eckert@amd.com .desc("number of times the CC registers were written") 2249920Syasuko.eckert@amd.com .flags(nozero) 2259920Syasuko.eckert@amd.com ; 2269920Syasuko.eckert@amd.com 2272SN/A numMemRefs 2287897Shestness@cs.utexas.edu .name(name()+".num_mem_refs") 2297897Shestness@cs.utexas.edu .desc("number of memory refs") 2307897Shestness@cs.utexas.edu ; 2317897Shestness@cs.utexas.edu 2327897Shestness@cs.utexas.edu numStoreInsts 2337897Shestness@cs.utexas.edu .name(name() + ".num_store_insts") 2347897Shestness@cs.utexas.edu .desc("Number of store instructions") 2357897Shestness@cs.utexas.edu ; 2367897Shestness@cs.utexas.edu 2377897Shestness@cs.utexas.edu numLoadInsts 2387897Shestness@cs.utexas.edu .name(name() + ".num_load_insts") 2397897Shestness@cs.utexas.edu .desc("Number of load instructions") 2402SN/A ; 2412SN/A 2421001SN/A notIdleFraction 2431001SN/A .name(name() + ".not_idle_fraction") 2441001SN/A .desc("Percentage of non-idle cycles") 2451001SN/A ; 2461001SN/A 2472SN/A idleFraction 2482SN/A .name(name() + ".idle_fraction") 2492SN/A .desc("Percentage of idle cycles") 2502SN/A ; 2512SN/A 2527897Shestness@cs.utexas.edu numBusyCycles 2537897Shestness@cs.utexas.edu .name(name() + ".num_busy_cycles") 2547897Shestness@cs.utexas.edu .desc("Number of busy cycles") 2557897Shestness@cs.utexas.edu ; 2567897Shestness@cs.utexas.edu 2577897Shestness@cs.utexas.edu numIdleCycles 2587897Shestness@cs.utexas.edu .name(name()+".num_idle_cycles") 2597897Shestness@cs.utexas.edu .desc("Number of idle cycles") 2607897Shestness@cs.utexas.edu ; 2617897Shestness@cs.utexas.edu 2622SN/A icacheStallCycles 2632SN/A .name(name() + ".icache_stall_cycles") 2642SN/A .desc("ICache total stall cycles") 2652SN/A .prereq(icacheStallCycles) 2662SN/A ; 2672SN/A 2682SN/A dcacheStallCycles 2692SN/A .name(name() + ".dcache_stall_cycles") 2702SN/A .desc("DCache total stall cycles") 2712SN/A .prereq(dcacheStallCycles) 2722SN/A ; 2732SN/A 2742390SN/A icacheRetryCycles 2752390SN/A .name(name() + ".icache_retry_cycles") 2762390SN/A .desc("ICache total retry cycles") 2772390SN/A .prereq(icacheRetryCycles) 2782390SN/A ; 2792390SN/A 2802390SN/A dcacheRetryCycles 2812390SN/A .name(name() + ".dcache_retry_cycles") 2822390SN/A .desc("DCache total retry cycles") 2832390SN/A .prereq(dcacheRetryCycles) 2842390SN/A ; 2852390SN/A 286385SN/A idleFraction = constant(1.0) - notIdleFraction; 2877897Shestness@cs.utexas.edu numIdleCycles = idleFraction * numCycles; 2887897Shestness@cs.utexas.edu numBusyCycles = (notIdleFraction)*numCycles; 2892SN/A} 2902SN/A 2912SN/Avoid 2922623SN/ABaseSimpleCPU::resetStats() 293334SN/A{ 2942361SN/A// startNumInst = numInst; 2955496Ssaidi@eecs.umich.edu notIdleFraction = (_status != Idle); 296334SN/A} 297334SN/A 298334SN/Avoid 2999448SAndreas.Sandberg@ARM.comBaseSimpleCPU::serializeThread(ostream &os, ThreadID tid) 3002SN/A{ 3019448SAndreas.Sandberg@ARM.com assert(_status == Idle || _status == Running); 3029448SAndreas.Sandberg@ARM.com assert(tid == 0); 3039448SAndreas.Sandberg@ARM.com 3042683Sktlim@umich.edu thread->serialize(os); 3052SN/A} 3062SN/A 3072SN/Avoid 3089448SAndreas.Sandberg@ARM.comBaseSimpleCPU::unserializeThread(Checkpoint *cp, const string §ion, 3099448SAndreas.Sandberg@ARM.com ThreadID tid) 3102SN/A{ 3119448SAndreas.Sandberg@ARM.com if (tid != 0) 3129448SAndreas.Sandberg@ARM.com fatal("Trying to load more than one thread into a SimpleCPU\n"); 3139448SAndreas.Sandberg@ARM.com thread->unserialize(cp, section); 3142SN/A} 3152SN/A 3162SN/Avoid 3176221Snate@binkert.orgchange_thread_state(ThreadID tid, int activate, int priority) 3182SN/A{ 3192SN/A} 3202SN/A 3212SN/AAddr 3222623SN/ABaseSimpleCPU::dbg_vtophys(Addr addr) 3232SN/A{ 3242680Sktlim@umich.edu return vtophys(tc, addr); 3252SN/A} 3262SN/A 3272SN/Avoid 3285807Snate@binkert.orgBaseSimpleCPU::wakeup() 3292SN/A{ 3305807Snate@binkert.org if (thread->status() != ThreadContext::Suspended) 3315807Snate@binkert.org return; 3322SN/A 3335807Snate@binkert.org DPRINTF(Quiesce,"Suspended Processor awoke\n"); 3345807Snate@binkert.org thread->activate(); 3352SN/A} 3362SN/A 3372SN/Avoid 3382623SN/ABaseSimpleCPU::checkForInterrupts() 3392SN/A{ 3405704Snate@binkert.org if (checkInterrupts(tc)) { 3415647Sgblack@eecs.umich.edu Fault interrupt = interrupts->getInterrupt(tc); 3422SN/A 3433520Sgblack@eecs.umich.edu if (interrupt != NoFault) { 3447338SAli.Saidi@ARM.com fetchOffset = 0; 3455647Sgblack@eecs.umich.edu interrupts->updateIntrInfo(tc); 3463520Sgblack@eecs.umich.edu interrupt->invoke(tc); 3479023Sgblack@eecs.umich.edu thread->decoder.reset(); 3482SN/A } 3492SN/A } 3502623SN/A} 3512SN/A 3522623SN/A 3535894Sgblack@eecs.umich.eduvoid 3542662Sstever@eecs.umich.eduBaseSimpleCPU::setupFetchRequest(Request *req) 3552623SN/A{ 3567720Sgblack@eecs.umich.edu Addr instAddr = thread->instAddr(); 3574495Sacolyte@umich.edu 3582623SN/A // set up memory request for instruction fetch 3597720Sgblack@eecs.umich.edu DPRINTF(Fetch, "Fetch: PC:%08p\n", instAddr); 3602623SN/A 3617720Sgblack@eecs.umich.edu Addr fetchPC = (instAddr & PCMask) + fetchOffset; 3628832SAli.Saidi@ARM.com req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instMasterId(), 3638832SAli.Saidi@ARM.com instAddr); 3642623SN/A} 3652623SN/A 3662623SN/A 3672623SN/Avoid 3682623SN/ABaseSimpleCPU::preExecute() 3692623SN/A{ 3702SN/A // maintain $r0 semantics 3712683Sktlim@umich.edu thread->setIntReg(ZeroReg, 0); 3722427SN/A#if THE_ISA == ALPHA_ISA 3732683Sktlim@umich.edu thread->setFloatReg(ZeroReg, 0.0); 3742427SN/A#endif // ALPHA_ISA 3752SN/A 3762623SN/A // check for instruction-count-based events 3772623SN/A comInstEventQueue[0]->serviceEvents(numInst); 3787897Shestness@cs.utexas.edu system->instEventQueue.serviceEvents(system->totalNumInsts); 3792SN/A 3802623SN/A // decode the instruction 3812623SN/A inst = gtoh(inst); 3824377Sgblack@eecs.umich.edu 3837720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 3844377Sgblack@eecs.umich.edu 3857720Sgblack@eecs.umich.edu if (isRomMicroPC(pcState.microPC())) { 3865665Sgblack@eecs.umich.edu stayAtPC = false; 3877720Sgblack@eecs.umich.edu curStaticInst = microcodeRom.fetchMicroop(pcState.microPC(), 3887720Sgblack@eecs.umich.edu curMacroStaticInst); 3895665Sgblack@eecs.umich.edu } else if (!curMacroStaticInst) { 3905665Sgblack@eecs.umich.edu //We're not in the middle of a macro instruction 3914181Sgblack@eecs.umich.edu StaticInstPtr instPtr = NULL; 3924181Sgblack@eecs.umich.edu 3939023Sgblack@eecs.umich.edu TheISA::Decoder *decoder = &(thread->decoder); 3949023Sgblack@eecs.umich.edu 3954181Sgblack@eecs.umich.edu //Predecode, ie bundle up an ExtMachInst 3964182Sgblack@eecs.umich.edu //If more fetch data is needed, pass it in. 3977720Sgblack@eecs.umich.edu Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset; 3989023Sgblack@eecs.umich.edu //if(decoder->needMoreBytes()) 3999023Sgblack@eecs.umich.edu decoder->moreBytes(pcState, fetchPC, inst); 4004593Sgblack@eecs.umich.edu //else 4019023Sgblack@eecs.umich.edu // decoder->process(); 4024377Sgblack@eecs.umich.edu 4039023Sgblack@eecs.umich.edu //Decode an instruction if one is ready. Otherwise, we'll have to 4044377Sgblack@eecs.umich.edu //fetch beyond the MachInst at the current pc. 4059023Sgblack@eecs.umich.edu instPtr = decoder->decode(pcState); 4069023Sgblack@eecs.umich.edu if (instPtr) { 4074377Sgblack@eecs.umich.edu stayAtPC = false; 4087720Sgblack@eecs.umich.edu thread->pcState(pcState); 4094377Sgblack@eecs.umich.edu } else { 4104377Sgblack@eecs.umich.edu stayAtPC = true; 4114377Sgblack@eecs.umich.edu fetchOffset += sizeof(MachInst); 4124377Sgblack@eecs.umich.edu } 4134181Sgblack@eecs.umich.edu 4144181Sgblack@eecs.umich.edu //If we decoded an instruction and it's microcoded, start pulling 4154181Sgblack@eecs.umich.edu //out micro ops 4164539Sgblack@eecs.umich.edu if (instPtr && instPtr->isMacroop()) { 4173276Sgblack@eecs.umich.edu curMacroStaticInst = instPtr; 4187720Sgblack@eecs.umich.edu curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC()); 4193280Sgblack@eecs.umich.edu } else { 4203280Sgblack@eecs.umich.edu curStaticInst = instPtr; 4213276Sgblack@eecs.umich.edu } 4223276Sgblack@eecs.umich.edu } else { 4233276Sgblack@eecs.umich.edu //Read the next micro op from the macro op 4247720Sgblack@eecs.umich.edu curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC()); 4253276Sgblack@eecs.umich.edu } 4263276Sgblack@eecs.umich.edu 4274181Sgblack@eecs.umich.edu //If we decoded an instruction this "tick", record information about it. 4288955Sgblack@eecs.umich.edu if (curStaticInst) { 4294522Ssaidi@eecs.umich.edu#if TRACING_ON 4307823Ssteve.reinhardt@amd.com traceData = tracer->getInstRecord(curTick(), tc, 4317720Sgblack@eecs.umich.edu curStaticInst, thread->pcState(), curMacroStaticInst); 4322470SN/A 4338955Sgblack@eecs.umich.edu DPRINTF(Decode,"Decode: Decoded %s instruction: %#x\n", 4344181Sgblack@eecs.umich.edu curStaticInst->getName(), curStaticInst->machInst); 4354522Ssaidi@eecs.umich.edu#endif // TRACING_ON 4364181Sgblack@eecs.umich.edu } 4372623SN/A} 4382623SN/A 4392623SN/Avoid 4402623SN/ABaseSimpleCPU::postExecute() 4412623SN/A{ 4427720Sgblack@eecs.umich.edu assert(curStaticInst); 4437720Sgblack@eecs.umich.edu 4447720Sgblack@eecs.umich.edu TheISA::PCState pc = tc->pcState(); 4457720Sgblack@eecs.umich.edu Addr instAddr = pc.instAddr(); 4468780Sgblack@eecs.umich.edu if (FullSystem && thread->profile) { 4473577Sgblack@eecs.umich.edu bool usermode = TheISA::inUserMode(tc); 4487720Sgblack@eecs.umich.edu thread->profilePC = usermode ? 1 : instAddr; 4495086Sgblack@eecs.umich.edu ProfileNode *node = thread->profile->consume(tc, curStaticInst); 4502623SN/A if (node) 4512683Sktlim@umich.edu thread->profileNode = node; 4522623SN/A } 4532SN/A 4542623SN/A if (curStaticInst->isMemRef()) { 4552623SN/A numMemRefs++; 4562SN/A } 4572SN/A 4582623SN/A if (curStaticInst->isLoad()) { 4592623SN/A ++numLoad; 4602623SN/A comLoadEventQueue[0]->serviceEvents(numLoad); 4612623SN/A } 4622SN/A 4635953Ssaidi@eecs.umich.edu if (CPA::available()) { 4647720Sgblack@eecs.umich.edu CPA::cpa()->swAutoBegin(tc, pc.nextInstAddr()); 4655953Ssaidi@eecs.umich.edu } 4665953Ssaidi@eecs.umich.edu 4677897Shestness@cs.utexas.edu /* Power model statistics */ 4687897Shestness@cs.utexas.edu //integer alu accesses 4697897Shestness@cs.utexas.edu if (curStaticInst->isInteger()){ 4707897Shestness@cs.utexas.edu numIntAluAccesses++; 4717897Shestness@cs.utexas.edu numIntInsts++; 4727897Shestness@cs.utexas.edu } 4737897Shestness@cs.utexas.edu 4747897Shestness@cs.utexas.edu //float alu accesses 4757897Shestness@cs.utexas.edu if (curStaticInst->isFloating()){ 4767897Shestness@cs.utexas.edu numFpAluAccesses++; 4777897Shestness@cs.utexas.edu numFpInsts++; 4787897Shestness@cs.utexas.edu } 4797897Shestness@cs.utexas.edu 4807897Shestness@cs.utexas.edu //number of function calls/returns to get window accesses 4817897Shestness@cs.utexas.edu if (curStaticInst->isCall() || curStaticInst->isReturn()){ 4827897Shestness@cs.utexas.edu numCallsReturns++; 4837897Shestness@cs.utexas.edu } 4847897Shestness@cs.utexas.edu 4857897Shestness@cs.utexas.edu //the number of branch predictions that will be made 4867897Shestness@cs.utexas.edu if (curStaticInst->isCondCtrl()){ 4877897Shestness@cs.utexas.edu numCondCtrlInsts++; 4887897Shestness@cs.utexas.edu } 4897897Shestness@cs.utexas.edu 4907897Shestness@cs.utexas.edu //result bus acceses 4917897Shestness@cs.utexas.edu if (curStaticInst->isLoad()){ 4927897Shestness@cs.utexas.edu numLoadInsts++; 4937897Shestness@cs.utexas.edu } 4947897Shestness@cs.utexas.edu 4957897Shestness@cs.utexas.edu if (curStaticInst->isStore()){ 4967897Shestness@cs.utexas.edu numStoreInsts++; 4977897Shestness@cs.utexas.edu } 4987897Shestness@cs.utexas.edu /* End power model statistics */ 4997897Shestness@cs.utexas.edu 5008780Sgblack@eecs.umich.edu if (FullSystem) 5018780Sgblack@eecs.umich.edu traceFunctions(instAddr); 5022644Sstever@eecs.umich.edu 5032644Sstever@eecs.umich.edu if (traceData) { 5044046Sbinkertn@umich.edu traceData->dump(); 5054046Sbinkertn@umich.edu delete traceData; 5064046Sbinkertn@umich.edu traceData = NULL; 5072644Sstever@eecs.umich.edu } 5082623SN/A} 5092SN/A 5102SN/A 5112623SN/Avoid 5122623SN/ABaseSimpleCPU::advancePC(Fault fault) 5132623SN/A{ 5144377Sgblack@eecs.umich.edu //Since we're moving to a new pc, zero out the offset 5154377Sgblack@eecs.umich.edu fetchOffset = 0; 5162090SN/A if (fault != NoFault) { 5173905Ssaidi@eecs.umich.edu curMacroStaticInst = StaticInst::nullStaticInstPtr; 5187678Sgblack@eecs.umich.edu fault->invoke(tc, curStaticInst); 5199023Sgblack@eecs.umich.edu thread->decoder.reset(); 5204377Sgblack@eecs.umich.edu } else { 5217720Sgblack@eecs.umich.edu if (curStaticInst) { 5227720Sgblack@eecs.umich.edu if (curStaticInst->isLastMicroop()) 5237720Sgblack@eecs.umich.edu curMacroStaticInst = StaticInst::nullStaticInstPtr; 5247720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 5257720Sgblack@eecs.umich.edu TheISA::advancePC(pcState, curStaticInst); 5267720Sgblack@eecs.umich.edu thread->pcState(pcState); 5273276Sgblack@eecs.umich.edu } 5282SN/A } 5292SN/A} 5302SN/A 5319461Snilay@cs.wisc.eduvoid 5329461Snilay@cs.wisc.eduBaseSimpleCPU::startup() 5339461Snilay@cs.wisc.edu{ 5349461Snilay@cs.wisc.edu BaseCPU::startup(); 5359461Snilay@cs.wisc.edu thread->startup(); 5369461Snilay@cs.wisc.edu} 537