base.cc revision 921 
1/*
2 * Copyright (c) 2002-2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <cmath>
30#include <cstdio>
31#include <cstdlib>
32#include <iostream>
33#include <iomanip>
34#include <list>
35#include <sstream>
36#include <string>
37
38#include "base/cprintf.hh"
39#include "base/inifile.hh"
40#include "base/loader/symtab.hh"
41#include "base/misc.hh"
42#include "base/pollevent.hh"
43#include "base/range.hh"
44#include "base/trace.hh"
45#include "base/stats/events.hh"
46#include "cpu/base_cpu.hh"
47#include "cpu/exec_context.hh"
48#include "cpu/exetrace.hh"
49#include "cpu/full_cpu/smt.hh"
50#include "cpu/simple_cpu/simple_cpu.hh"
51#include "cpu/static_inst.hh"
52#include "mem/base_mem.hh"
53#include "mem/mem_interface.hh"
54#include "sim/builder.hh"
55#include "sim/debug.hh"
56#include "sim/host.hh"
57#include "sim/sim_events.hh"
58#include "sim/sim_object.hh"
59#include "sim/stats.hh"
60
61#ifdef FULL_SYSTEM
62#include "base/remote_gdb.hh"
63#include "dev/alpha_access.h"
64#include "dev/pciareg.h"
65#include "mem/functional_mem/memory_control.hh"
66#include "mem/functional_mem/physical_memory.hh"
67#include "sim/system.hh"
68#include "targetarch/alpha_memory.hh"
69#include "targetarch/vtophys.hh"
70#else // !FULL_SYSTEM
71#include "eio/eio.hh"
72#include "mem/functional_mem/functional_memory.hh"
73#endif // FULL_SYSTEM
74
75using namespace std;
76
77SimpleCPU::TickEvent::TickEvent(SimpleCPU *c)
78    : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
79{
80}
81
82void
83SimpleCPU::TickEvent::process()
84{
85    cpu->tick();
86}
87
88const char *
89SimpleCPU::TickEvent::description()
90{
91    return "SimpleCPU tick event";
92}
93
94
95SimpleCPU::CacheCompletionEvent::CacheCompletionEvent(SimpleCPU *_cpu)
96    : Event(&mainEventQueue),
97      cpu(_cpu)
98{
99}
100
101void SimpleCPU::CacheCompletionEvent::process()
102{
103    cpu->processCacheCompletion();
104}
105
106const char *
107SimpleCPU::CacheCompletionEvent::description()
108{
109    return "SimpleCPU cache completion event";
110}
111
112#ifdef FULL_SYSTEM
113SimpleCPU::SimpleCPU(const string &_name,
114                     System *_system,
115                     Counter max_insts_any_thread,
116                     Counter max_insts_all_threads,
117                     Counter max_loads_any_thread,
118                     Counter max_loads_all_threads,
119                     AlphaITB *itb, AlphaDTB *dtb,
120                     FunctionalMemory *mem,
121                     MemInterface *icache_interface,
122                     MemInterface *dcache_interface,
123                     bool _def_reg, Tick freq)
124    : BaseCPU(_name, /* number_of_threads */ 1,
125              max_insts_any_thread, max_insts_all_threads,
126              max_loads_any_thread, max_loads_all_threads,
127              _system, freq),
128#else
129SimpleCPU::SimpleCPU(const string &_name, Process *_process,
130                     Counter max_insts_any_thread,
131                     Counter max_insts_all_threads,
132                     Counter max_loads_any_thread,
133                     Counter max_loads_all_threads,
134                     MemInterface *icache_interface,
135                     MemInterface *dcache_interface,
136                     bool _def_reg)
137    : BaseCPU(_name, /* number_of_threads */ 1,
138              max_insts_any_thread, max_insts_all_threads,
139              max_loads_any_thread, max_loads_all_threads),
140#endif
141      tickEvent(this), xc(NULL), defer_registration(_def_reg),
142      cacheCompletionEvent(this)
143{
144    _status = Idle;
145#ifdef FULL_SYSTEM
146    xc = new ExecContext(this, 0, system, itb, dtb, mem);
147
148    // initialize CPU, including PC
149    TheISA::initCPU(&xc->regs);
150#else
151    xc = new ExecContext(this, /* thread_num */ 0, _process, /* asid */ 0);
152#endif // !FULL_SYSTEM
153
154    icacheInterface = icache_interface;
155    dcacheInterface = dcache_interface;
156
157    memReq = new MemReq();
158    memReq->xc = xc;
159    memReq->asid = 0;
160    memReq->data = new uint8_t[64];
161
162    numInst = 0;
163    startNumInst = 0;
164    numLoad = 0;
165    startNumLoad = 0;
166    lastIcacheStall = 0;
167    lastDcacheStall = 0;
168
169    execContexts.push_back(xc);
170}
171
172SimpleCPU::~SimpleCPU()
173{
174}
175
176void SimpleCPU::init()
177{
178    if (!defer_registration) {
179        this->registerExecContexts();
180    }
181}
182
183void
184SimpleCPU::switchOut()
185{
186    _status = SwitchedOut;
187    if (tickEvent.scheduled())
188        tickEvent.squash();
189}
190
191
192void
193SimpleCPU::takeOverFrom(BaseCPU *oldCPU)
194{
195    BaseCPU::takeOverFrom(oldCPU);
196
197    assert(!tickEvent.scheduled());
198
199    // if any of this CPU's ExecContexts are active, mark the CPU as
200    // running and schedule its tick event.
201    for (int i = 0; i < execContexts.size(); ++i) {
202        ExecContext *xc = execContexts[i];
203        if (xc->status() == ExecContext::Active && _status != Running) {
204            _status = Running;
205            tickEvent.schedule(curTick);
206        }
207    }
208
209    oldCPU->switchOut();
210}
211
212
213void
214SimpleCPU::activateContext(int thread_num, int delay)
215{
216    assert(thread_num == 0);
217    assert(xc);
218
219    assert(_status == Idle);
220    notIdleFraction++;
221    scheduleTickEvent(delay);
222    _status = Running;
223}
224
225
226void
227SimpleCPU::suspendContext(int thread_num)
228{
229    assert(thread_num == 0);
230    assert(xc);
231
232    assert(_status == Running);
233    notIdleFraction--;
234    unscheduleTickEvent();
235    _status = Idle;
236}
237
238
239void
240SimpleCPU::deallocateContext(int thread_num)
241{
242    // for now, these are equivalent
243    suspendContext(thread_num);
244}
245
246
247void
248SimpleCPU::haltContext(int thread_num)
249{
250    // for now, these are equivalent
251    suspendContext(thread_num);
252}
253
254
255void
256SimpleCPU::regStats()
257{
258    using namespace Stats;
259
260    BaseCPU::regStats();
261
262    numInsts
263        .name(name() + ".num_insts")
264        .desc("Number of instructions executed")
265        ;
266
267    numMemRefs
268        .name(name() + ".num_refs")
269        .desc("Number of memory references")
270        ;
271
272    idleFraction
273        .name(name() + ".idle_fraction")
274        .desc("Percentage of idle cycles")
275        ;
276
277    icacheStallCycles
278        .name(name() + ".icache_stall_cycles")
279        .desc("ICache total stall cycles")
280        .prereq(icacheStallCycles)
281        ;
282
283    dcacheStallCycles
284        .name(name() + ".dcache_stall_cycles")
285        .desc("DCache total stall cycles")
286        .prereq(dcacheStallCycles)
287        ;
288
289    idleFraction = constant(1.0) - notIdleFraction;
290}
291
292void
293SimpleCPU::resetStats()
294{
295    startNumInst = numInst;
296    notIdleFraction = (_status != Idle);
297}
298
299void
300SimpleCPU::serialize(ostream &os)
301{
302    BaseCPU::serialize(os);
303    SERIALIZE_ENUM(_status);
304    SERIALIZE_SCALAR(inst);
305    nameOut(os, csprintf("%s.xc", name()));
306    xc->serialize(os);
307    nameOut(os, csprintf("%s.tickEvent", name()));
308    tickEvent.serialize(os);
309    nameOut(os, csprintf("%s.cacheCompletionEvent", name()));
310    cacheCompletionEvent.serialize(os);
311}
312
313void
314SimpleCPU::unserialize(Checkpoint *cp, const string &section)
315{
316    BaseCPU::unserialize(cp, section);
317    UNSERIALIZE_ENUM(_status);
318    UNSERIALIZE_SCALAR(inst);
319    xc->unserialize(cp, csprintf("%s.xc", section));
320    tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
321    cacheCompletionEvent
322        .unserialize(cp, csprintf("%s.cacheCompletionEvent", section));
323}
324
325void
326change_thread_state(int thread_number, int activate, int priority)
327{
328}
329
330Fault
331SimpleCPU::copySrcTranslate(Addr src)
332{
333    memReq->reset(src, (dcacheInterface) ?
334                  dcacheInterface->getBlockSize()
335                  : 64);
336
337    // translate to physical address
338    Fault fault = xc->translateDataReadReq(memReq);
339
340    if (fault == No_Fault) {
341        xc->copySrcAddr = src;
342        xc->copySrcPhysAddr = memReq->paddr;
343    } else {
344        xc->copySrcAddr = 0;
345        xc->copySrcPhysAddr = 0;
346    }
347    return fault;
348}
349
350Fault
351SimpleCPU::copy(Addr dest)
352{
353    int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
354    uint8_t data[blk_size];
355    assert(xc->copySrcPhysAddr);
356    memReq->reset(dest, blk_size);
357    // translate to physical address
358    Fault fault = xc->translateDataWriteReq(memReq);
359    if (fault == No_Fault) {
360        Addr dest_addr = memReq->paddr;
361        // Need to read straight from memory since we have more than 8 bytes.
362        memReq->paddr = xc->copySrcPhysAddr;
363        xc->mem->read(memReq, data);
364        memReq->paddr = dest_addr;
365        xc->mem->write(memReq, data);
366    }
367    return fault;
368}
369
370// precise architected memory state accessor macros
371template <class T>
372Fault
373SimpleCPU::read(Addr addr, T &data, unsigned flags)
374{
375    memReq->reset(addr, sizeof(T), flags);
376
377    // translate to physical address
378    Fault fault = xc->translateDataReadReq(memReq);
379
380    // do functional access
381    if (fault == No_Fault)
382        fault = xc->read(memReq, data);
383
384    if (traceData) {
385        traceData->setAddr(addr);
386        if (fault == No_Fault)
387            traceData->setData(data);
388    }
389
390    // if we have a cache, do cache access too
391    if (fault == No_Fault && dcacheInterface) {
392        memReq->cmd = Read;
393        memReq->completionEvent = NULL;
394        memReq->time = curTick;
395        MemAccessResult result = dcacheInterface->access(memReq);
396
397        // Ugly hack to get an event scheduled *only* if the access is
398        // a miss.  We really should add first-class support for this
399        // at some point.
400        if (result != MA_HIT && dcacheInterface->doEvents()) {
401            memReq->completionEvent = &cacheCompletionEvent;
402            lastDcacheStall = curTick;
403            unscheduleTickEvent();
404            _status = DcacheMissStall;
405        }
406    }
407
408    if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
409        Stats::recordEvent("Uncached Read");
410
411    return fault;
412}
413
414#ifndef DOXYGEN_SHOULD_SKIP_THIS
415
416template
417Fault
418SimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
419
420template
421Fault
422SimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
423
424template
425Fault
426SimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
427
428template
429Fault
430SimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
431
432#endif //DOXYGEN_SHOULD_SKIP_THIS
433
434template<>
435Fault
436SimpleCPU::read(Addr addr, double &data, unsigned flags)
437{
438    return read(addr, *(uint64_t*)&data, flags);
439}
440
441template<>
442Fault
443SimpleCPU::read(Addr addr, float &data, unsigned flags)
444{
445    return read(addr, *(uint32_t*)&data, flags);
446}
447
448
449template<>
450Fault
451SimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
452{
453    return read(addr, (uint32_t&)data, flags);
454}
455
456
457template <class T>
458Fault
459SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
460{
461    if (traceData) {
462        traceData->setAddr(addr);
463        traceData->setData(data);
464    }
465
466    memReq->reset(addr, sizeof(T), flags);
467
468    // translate to physical address
469    Fault fault = xc->translateDataWriteReq(memReq);
470
471    // do functional access
472    if (fault == No_Fault)
473        fault = xc->write(memReq, data);
474
475    if (fault == No_Fault && dcacheInterface) {
476        memReq->cmd = Write;
477        memcpy(memReq->data,(uint8_t *)&data,memReq->size);
478        memReq->completionEvent = NULL;
479        memReq->time = curTick;
480        MemAccessResult result = dcacheInterface->access(memReq);
481
482        // Ugly hack to get an event scheduled *only* if the access is
483        // a miss.  We really should add first-class support for this
484        // at some point.
485        if (result != MA_HIT && dcacheInterface->doEvents()) {
486            memReq->completionEvent = &cacheCompletionEvent;
487            lastDcacheStall = curTick;
488            unscheduleTickEvent();
489            _status = DcacheMissStall;
490        }
491    }
492
493    if (res && (fault == No_Fault))
494        *res = memReq->result;
495
496    if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
497        Stats::recordEvent("Uncached Write");
498
499    return fault;
500}
501
502
503#ifndef DOXYGEN_SHOULD_SKIP_THIS
504template
505Fault
506SimpleCPU::write(uint64_t data, Addr addr, unsigned flags, uint64_t *res);
507
508template
509Fault
510SimpleCPU::write(uint32_t data, Addr addr, unsigned flags, uint64_t *res);
511
512template
513Fault
514SimpleCPU::write(uint16_t data, Addr addr, unsigned flags, uint64_t *res);
515
516template
517Fault
518SimpleCPU::write(uint8_t data, Addr addr, unsigned flags, uint64_t *res);
519
520#endif //DOXYGEN_SHOULD_SKIP_THIS
521
522template<>
523Fault
524SimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
525{
526    return write(*(uint64_t*)&data, addr, flags, res);
527}
528
529template<>
530Fault
531SimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
532{
533    return write(*(uint32_t*)&data, addr, flags, res);
534}
535
536
537template<>
538Fault
539SimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
540{
541    return write((uint32_t)data, addr, flags, res);
542}
543
544
545#ifdef FULL_SYSTEM
546Addr
547SimpleCPU::dbg_vtophys(Addr addr)
548{
549    return vtophys(xc, addr);
550}
551#endif // FULL_SYSTEM
552
553Tick save_cycle = 0;
554
555
556void
557SimpleCPU::processCacheCompletion()
558{
559    switch (status()) {
560      case IcacheMissStall:
561        icacheStallCycles += curTick - lastIcacheStall;
562        _status = IcacheMissComplete;
563        scheduleTickEvent(1);
564        break;
565      case DcacheMissStall:
566        dcacheStallCycles += curTick - lastDcacheStall;
567        _status = Running;
568        scheduleTickEvent(1);
569        break;
570      case SwitchedOut:
571        // If this CPU has been switched out due to sampling/warm-up,
572        // ignore any further status changes (e.g., due to cache
573        // misses outstanding at the time of the switch).
574        return;
575      default:
576        panic("SimpleCPU::processCacheCompletion: bad state");
577        break;
578    }
579}
580
581#ifdef FULL_SYSTEM
582void
583SimpleCPU::post_interrupt(int int_num, int index)
584{
585    BaseCPU::post_interrupt(int_num, index);
586
587    if (xc->status() == ExecContext::Suspended) {
588                DPRINTF(IPI,"Suspended Processor awoke\n");
589        xc->activate();
590    }
591}
592#endif // FULL_SYSTEM
593
594/* start simulation, program loaded, processor precise state initialized */
595void
596SimpleCPU::tick()
597{
598    numCycles++;
599
600    traceData = NULL;
601
602    Fault fault = No_Fault;
603
604#ifdef FULL_SYSTEM
605    if (AlphaISA::check_interrupts &&
606        xc->cpu->check_interrupts() &&
607        !PC_PAL(xc->regs.pc) &&
608        status() != IcacheMissComplete) {
609        int ipl = 0;
610        int summary = 0;
611        AlphaISA::check_interrupts = 0;
612        IntReg *ipr = xc->regs.ipr;
613
614        if (xc->regs.ipr[TheISA::IPR_SIRR]) {
615            for (int i = TheISA::INTLEVEL_SOFTWARE_MIN;
616                 i < TheISA::INTLEVEL_SOFTWARE_MAX; i++) {
617                if (ipr[TheISA::IPR_SIRR] & (ULL(1) << i)) {
618                    // See table 4-19 of 21164 hardware reference
619                    ipl = (i - TheISA::INTLEVEL_SOFTWARE_MIN) + 1;
620                    summary |= (ULL(1) << i);
621                }
622            }
623        }
624
625        uint64_t interrupts = xc->cpu->intr_status();
626        for (int i = TheISA::INTLEVEL_EXTERNAL_MIN;
627            i < TheISA::INTLEVEL_EXTERNAL_MAX; i++) {
628            if (interrupts & (ULL(1) << i)) {
629                // See table 4-19 of 21164 hardware reference
630                ipl = i;
631                summary |= (ULL(1) << i);
632            }
633        }
634
635        if (ipr[TheISA::IPR_ASTRR])
636            panic("asynchronous traps not implemented\n");
637
638        if (ipl && ipl > xc->regs.ipr[TheISA::IPR_IPLR]) {
639            ipr[TheISA::IPR_ISR] = summary;
640            ipr[TheISA::IPR_INTID] = ipl;
641            xc->ev5_trap(Interrupt_Fault);
642
643            DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
644                    ipr[TheISA::IPR_IPLR], ipl, summary);
645        }
646    }
647#endif
648
649    // maintain $r0 semantics
650    xc->regs.intRegFile[ZeroReg] = 0;
651#ifdef TARGET_ALPHA
652    xc->regs.floatRegFile.d[ZeroReg] = 0.0;
653#endif // TARGET_ALPHA
654
655    if (status() == IcacheMissComplete) {
656        // We've already fetched an instruction and were stalled on an
657        // I-cache miss.  No need to fetch it again.
658
659        // Set status to running; tick event will get rescheduled if
660        // necessary at end of tick() function.
661        _status = Running;
662    }
663    else {
664        // Try to fetch an instruction
665
666        // set up memory request for instruction fetch
667#ifdef FULL_SYSTEM
668#define IFETCH_FLAGS(pc)	((pc) & 1) ? PHYSICAL : 0
669#else
670#define IFETCH_FLAGS(pc)	0
671#endif
672
673        memReq->cmd = Read;
674        memReq->reset(xc->regs.pc & ~3, sizeof(uint32_t),
675                     IFETCH_FLAGS(xc->regs.pc));
676
677        fault = xc->translateInstReq(memReq);
678
679        if (fault == No_Fault)
680            fault = xc->mem->read(memReq, inst);
681
682        if (icacheInterface && fault == No_Fault) {
683            memReq->completionEvent = NULL;
684
685            memReq->time = curTick;
686            MemAccessResult result = icacheInterface->access(memReq);
687
688            // Ugly hack to get an event scheduled *only* if the access is
689            // a miss.  We really should add first-class support for this
690            // at some point.
691            if (result != MA_HIT && icacheInterface->doEvents()) {
692                memReq->completionEvent = &cacheCompletionEvent;
693                lastIcacheStall = curTick;
694                unscheduleTickEvent();
695                _status = IcacheMissStall;
696                return;
697            }
698        }
699    }
700
701    // If we've got a valid instruction (i.e., no fault on instruction
702    // fetch), then execute it.
703    if (fault == No_Fault) {
704
705        // keep an instruction count
706        numInst++;
707        numInsts++;
708
709        // check for instruction-count-based events
710        comInstEventQueue[0]->serviceEvents(numInst);
711
712        // decode the instruction
713        StaticInstPtr<TheISA> si(inst);
714
715        traceData = Trace::getInstRecord(curTick, xc, this, si,
716                                         xc->regs.pc);
717
718#ifdef FULL_SYSTEM
719        xc->setInst(inst);
720#endif // FULL_SYSTEM
721
722        xc->func_exe_inst++;
723
724        fault = si->execute(this, traceData);
725
726#ifdef FULL_SYSTEM
727        SWContext *ctx = xc->swCtx;
728        if (ctx)
729            ctx->process(xc, si.get());
730#endif
731
732        if (si->isMemRef()) {
733            numMemRefs++;
734        }
735
736        if (si->isLoad()) {
737            ++numLoad;
738            comLoadEventQueue[0]->serviceEvents(numLoad);
739        }
740
741        if (traceData)
742            traceData->finalize();
743
744    }	// if (fault == No_Fault)
745
746    if (fault != No_Fault) {
747#ifdef FULL_SYSTEM
748        xc->ev5_trap(fault);
749#else // !FULL_SYSTEM
750        fatal("fault (%d) detected @ PC 0x%08p", fault, xc->regs.pc);
751#endif // FULL_SYSTEM
752    }
753    else {
754        // go to the next instruction
755        xc->regs.pc = xc->regs.npc;
756        xc->regs.npc += sizeof(MachInst);
757    }
758
759#ifdef FULL_SYSTEM
760    Addr oldpc;
761    do {
762        oldpc = xc->regs.pc;
763        system->pcEventQueue.service(xc);
764    } while (oldpc != xc->regs.pc);
765#endif
766
767    assert(status() == Running ||
768           status() == Idle ||
769           status() == DcacheMissStall);
770
771    if (status() == Running && !tickEvent.scheduled())
772        tickEvent.schedule(curTick + 1);
773}
774
775
776////////////////////////////////////////////////////////////////////////
777//
778//  SimpleCPU Simulation Object
779//
780BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
781
782    Param<Counter> max_insts_any_thread;
783    Param<Counter> max_insts_all_threads;
784    Param<Counter> max_loads_any_thread;
785    Param<Counter> max_loads_all_threads;
786
787#ifdef FULL_SYSTEM
788    SimObjectParam<AlphaITB *> itb;
789    SimObjectParam<AlphaDTB *> dtb;
790    SimObjectParam<FunctionalMemory *> mem;
791    SimObjectParam<System *> system;
792    Param<int> mult;
793#else
794    SimObjectParam<Process *> workload;
795#endif // FULL_SYSTEM
796
797    SimObjectParam<BaseMem *> icache;
798    SimObjectParam<BaseMem *> dcache;
799
800    Param<bool> defer_registration;
801
802END_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
803
804BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
805
806    INIT_PARAM_DFLT(max_insts_any_thread,
807                    "terminate when any thread reaches this inst count",
808                    0),
809    INIT_PARAM_DFLT(max_insts_all_threads,
810                    "terminate when all threads have reached this inst count",
811                    0),
812    INIT_PARAM_DFLT(max_loads_any_thread,
813                    "terminate when any thread reaches this load count",
814                    0),
815    INIT_PARAM_DFLT(max_loads_all_threads,
816                    "terminate when all threads have reached this load count",
817                    0),
818
819#ifdef FULL_SYSTEM
820    INIT_PARAM(itb, "Instruction TLB"),
821    INIT_PARAM(dtb, "Data TLB"),
822    INIT_PARAM(mem, "memory"),
823    INIT_PARAM(system, "system object"),
824    INIT_PARAM_DFLT(mult, "system clock multiplier", 1),
825#else
826    INIT_PARAM(workload, "processes to run"),
827#endif // FULL_SYSTEM
828
829    INIT_PARAM_DFLT(icache, "L1 instruction cache object", NULL),
830    INIT_PARAM_DFLT(dcache, "L1 data cache object", NULL),
831    INIT_PARAM_DFLT(defer_registration, "defer registration with system "
832                    "(for sampling)", false)
833
834END_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
835
836
837CREATE_SIM_OBJECT(SimpleCPU)
838{
839    SimpleCPU *cpu;
840#ifdef FULL_SYSTEM
841    if (mult != 1)
842        panic("processor clock multiplier must be 1\n");
843
844    cpu = new SimpleCPU(getInstanceName(), system,
845                        max_insts_any_thread, max_insts_all_threads,
846                        max_loads_any_thread, max_loads_all_threads,
847                        itb, dtb, mem,
848                        (icache) ? icache->getInterface() : NULL,
849                        (dcache) ? dcache->getInterface() : NULL,
850                        defer_registration,
851                        ticksPerSecond * mult);
852#else
853
854    cpu = new SimpleCPU(getInstanceName(), workload,
855                        max_insts_any_thread, max_insts_all_threads,
856                        max_loads_any_thread, max_loads_all_threads,
857                        (icache) ? icache->getInterface() : NULL,
858                        (dcache) ? dcache->getInterface() : NULL,
859                        defer_registration);
860
861#endif // FULL_SYSTEM
862
863    return cpu;
864}
865
866REGISTER_SIM_OBJECT("SimpleCPU", SimpleCPU)
867
868