base.cc revision 8922
12SN/A/* 28733Sgeoffrey.blake@arm.com * Copyright (c) 2010-2011 ARM Limited 37338SAli.Saidi@ARM.com * All rights reserved 47338SAli.Saidi@ARM.com * 57338SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67338SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77338SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87338SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97338SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107338SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117338SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127338SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137338SAli.Saidi@ARM.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152SN/A * All rights reserved. 162SN/A * 172SN/A * Redistribution and use in source and binary forms, with or without 182SN/A * modification, are permitted provided that the following conditions are 192SN/A * met: redistributions of source code must retain the above copyright 202SN/A * notice, this list of conditions and the following disclaimer; 212SN/A * redistributions in binary form must reproduce the above copyright 222SN/A * notice, this list of conditions and the following disclaimer in the 232SN/A * documentation and/or other materials provided with the distribution; 242SN/A * neither the name of the copyright holders nor the names of its 252SN/A * contributors may be used to endorse or promote products derived from 262SN/A * this software without specific prior written permission. 272SN/A * 282SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 412SN/A */ 422SN/A 438779Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 448779Sgblack@eecs.umich.edu#include "arch/stacktrace.hh" 458779Sgblack@eecs.umich.edu#include "arch/tlb.hh" 462439SN/A#include "arch/utility.hh" 478779Sgblack@eecs.umich.edu#include "arch/vtophys.hh" 488229Snate@binkert.org#include "base/loader/symtab.hh" 496216Snate@binkert.org#include "base/cp_annotate.hh" 50146SN/A#include "base/cprintf.hh" 51146SN/A#include "base/inifile.hh" 52146SN/A#include "base/misc.hh" 53146SN/A#include "base/pollevent.hh" 54146SN/A#include "base/range.hh" 55146SN/A#include "base/trace.hh" 566216Snate@binkert.org#include "base/types.hh" 576658Snate@binkert.org#include "config/the_isa.hh" 588229Snate@binkert.org#include "cpu/simple/base.hh" 591717SN/A#include "cpu/base.hh" 608887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 618887Sgeoffrey.blake@arm.com#include "cpu/checker/thread_context.hh" 62146SN/A#include "cpu/exetrace.hh" 631977SN/A#include "cpu/profile.hh" 642683Sktlim@umich.edu#include "cpu/simple_thread.hh" 651717SN/A#include "cpu/smt.hh" 66146SN/A#include "cpu/static_inst.hh" 672683Sktlim@umich.edu#include "cpu/thread_context.hh" 688232Snate@binkert.org#include "debug/Decode.hh" 698232Snate@binkert.org#include "debug/Fetch.hh" 708232Snate@binkert.org#include "debug/Quiesce.hh" 718779Sgblack@eecs.umich.edu#include "mem/mem_object.hh" 723348Sbinkertn@umich.edu#include "mem/packet.hh" 736105Ssteve.reinhardt@amd.com#include "mem/request.hh" 746216Snate@binkert.org#include "params/BaseSimpleCPU.hh" 752036SN/A#include "sim/byteswap.hh" 76146SN/A#include "sim/debug.hh" 778817Sgblack@eecs.umich.edu#include "sim/faults.hh" 788793Sgblack@eecs.umich.edu#include "sim/full_system.hh" 7956SN/A#include "sim/sim_events.hh" 8056SN/A#include "sim/sim_object.hh" 81695SN/A#include "sim/stats.hh" 822901Ssaidi@eecs.umich.edu#include "sim/system.hh" 832SN/A 842SN/Ausing namespace std; 852449SN/Ausing namespace TheISA; 861355SN/A 875529Snate@binkert.orgBaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p) 884495Sacolyte@umich.edu : BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL) 89224SN/A{ 908793Sgblack@eecs.umich.edu if (FullSystem) 918793Sgblack@eecs.umich.edu thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb); 928793Sgblack@eecs.umich.edu else 938820Sgblack@eecs.umich.edu thread = new SimpleThread(this, /* thread_num */ 0, p->system, 948820Sgblack@eecs.umich.edu p->workload[0], p->itb, p->dtb); 952SN/A 966029Ssteve.reinhardt@amd.com thread->setStatus(ThreadContext::Halted); 972672Sktlim@umich.edu 982683Sktlim@umich.edu tc = thread->getTC(); 992SN/A 1008733Sgeoffrey.blake@arm.com if (p->checker) { 1018733Sgeoffrey.blake@arm.com BaseCPU *temp_checker = p->checker; 1028733Sgeoffrey.blake@arm.com checker = dynamic_cast<CheckerCPU *>(temp_checker); 1038733Sgeoffrey.blake@arm.com checker->setSystem(p->system); 1048733Sgeoffrey.blake@arm.com // Manipulate thread context 1058733Sgeoffrey.blake@arm.com ThreadContext *cpu_tc = tc; 1068733Sgeoffrey.blake@arm.com tc = new CheckerThreadContext<ThreadContext>(cpu_tc, this->checker); 1078733Sgeoffrey.blake@arm.com } else { 1088733Sgeoffrey.blake@arm.com checker = NULL; 1098733Sgeoffrey.blake@arm.com } 1108733Sgeoffrey.blake@arm.com 1112SN/A numInst = 0; 112334SN/A startNumInst = 0; 1138834Satgutier@umich.edu numOp = 0; 1148834Satgutier@umich.edu startNumOp = 0; 115140SN/A numLoad = 0; 116334SN/A startNumLoad = 0; 1172SN/A lastIcacheStall = 0; 1182SN/A lastDcacheStall = 0; 1192SN/A 1202680Sktlim@umich.edu threadContexts.push_back(tc); 1214377Sgblack@eecs.umich.edu 1225169Ssaidi@eecs.umich.edu 1234377Sgblack@eecs.umich.edu fetchOffset = 0; 1244377Sgblack@eecs.umich.edu stayAtPC = false; 1252SN/A} 1262SN/A 1272623SN/ABaseSimpleCPU::~BaseSimpleCPU() 1282SN/A{ 1292SN/A} 1302SN/A 131180SN/Avoid 1328737Skoansin.tan@gmail.comBaseSimpleCPU::deallocateContext(ThreadID thread_num) 133393SN/A{ 134393SN/A // for now, these are equivalent 135393SN/A suspendContext(thread_num); 136393SN/A} 137384SN/A 138384SN/A 139393SN/Avoid 1408737Skoansin.tan@gmail.comBaseSimpleCPU::haltContext(ThreadID thread_num) 141393SN/A{ 142393SN/A // for now, these are equivalent 143393SN/A suspendContext(thread_num); 144393SN/A} 145384SN/A 146189SN/A 147189SN/Avoid 1482623SN/ABaseSimpleCPU::regStats() 1492SN/A{ 150729SN/A using namespace Stats; 151334SN/A 1522SN/A BaseCPU::regStats(); 1532SN/A 1542SN/A numInsts 1558834Satgutier@umich.edu .name(name() + ".committedInsts") 1568834Satgutier@umich.edu .desc("Number of instructions committed") 1578834Satgutier@umich.edu ; 1588834Satgutier@umich.edu 1598834Satgutier@umich.edu numOps 1608834Satgutier@umich.edu .name(name() + ".committedOps") 1618834Satgutier@umich.edu .desc("Number of ops (including micro ops) committed") 1622SN/A ; 1632SN/A 1647897Shestness@cs.utexas.edu numIntAluAccesses 1657897Shestness@cs.utexas.edu .name(name() + ".num_int_alu_accesses") 1667897Shestness@cs.utexas.edu .desc("Number of integer alu accesses") 1677897Shestness@cs.utexas.edu ; 1687897Shestness@cs.utexas.edu 1697897Shestness@cs.utexas.edu numFpAluAccesses 1707897Shestness@cs.utexas.edu .name(name() + ".num_fp_alu_accesses") 1717897Shestness@cs.utexas.edu .desc("Number of float alu accesses") 1727897Shestness@cs.utexas.edu ; 1737897Shestness@cs.utexas.edu 1747897Shestness@cs.utexas.edu numCallsReturns 1757897Shestness@cs.utexas.edu .name(name() + ".num_func_calls") 1767897Shestness@cs.utexas.edu .desc("number of times a function call or return occured") 1777897Shestness@cs.utexas.edu ; 1787897Shestness@cs.utexas.edu 1797897Shestness@cs.utexas.edu numCondCtrlInsts 1807897Shestness@cs.utexas.edu .name(name() + ".num_conditional_control_insts") 1817897Shestness@cs.utexas.edu .desc("number of instructions that are conditional controls") 1827897Shestness@cs.utexas.edu ; 1837897Shestness@cs.utexas.edu 1847897Shestness@cs.utexas.edu numIntInsts 1857897Shestness@cs.utexas.edu .name(name() + ".num_int_insts") 1867897Shestness@cs.utexas.edu .desc("number of integer instructions") 1877897Shestness@cs.utexas.edu ; 1887897Shestness@cs.utexas.edu 1897897Shestness@cs.utexas.edu numFpInsts 1907897Shestness@cs.utexas.edu .name(name() + ".num_fp_insts") 1917897Shestness@cs.utexas.edu .desc("number of float instructions") 1927897Shestness@cs.utexas.edu ; 1937897Shestness@cs.utexas.edu 1947897Shestness@cs.utexas.edu numIntRegReads 1957897Shestness@cs.utexas.edu .name(name() + ".num_int_register_reads") 1967897Shestness@cs.utexas.edu .desc("number of times the integer registers were read") 1977897Shestness@cs.utexas.edu ; 1987897Shestness@cs.utexas.edu 1997897Shestness@cs.utexas.edu numIntRegWrites 2007897Shestness@cs.utexas.edu .name(name() + ".num_int_register_writes") 2017897Shestness@cs.utexas.edu .desc("number of times the integer registers were written") 2027897Shestness@cs.utexas.edu ; 2037897Shestness@cs.utexas.edu 2047897Shestness@cs.utexas.edu numFpRegReads 2057897Shestness@cs.utexas.edu .name(name() + ".num_fp_register_reads") 2067897Shestness@cs.utexas.edu .desc("number of times the floating registers were read") 2077897Shestness@cs.utexas.edu ; 2087897Shestness@cs.utexas.edu 2097897Shestness@cs.utexas.edu numFpRegWrites 2107897Shestness@cs.utexas.edu .name(name() + ".num_fp_register_writes") 2117897Shestness@cs.utexas.edu .desc("number of times the floating registers were written") 2127897Shestness@cs.utexas.edu ; 2137897Shestness@cs.utexas.edu 2142SN/A numMemRefs 2157897Shestness@cs.utexas.edu .name(name()+".num_mem_refs") 2167897Shestness@cs.utexas.edu .desc("number of memory refs") 2177897Shestness@cs.utexas.edu ; 2187897Shestness@cs.utexas.edu 2197897Shestness@cs.utexas.edu numStoreInsts 2207897Shestness@cs.utexas.edu .name(name() + ".num_store_insts") 2217897Shestness@cs.utexas.edu .desc("Number of store instructions") 2227897Shestness@cs.utexas.edu ; 2237897Shestness@cs.utexas.edu 2247897Shestness@cs.utexas.edu numLoadInsts 2257897Shestness@cs.utexas.edu .name(name() + ".num_load_insts") 2267897Shestness@cs.utexas.edu .desc("Number of load instructions") 2272SN/A ; 2282SN/A 2291001SN/A notIdleFraction 2301001SN/A .name(name() + ".not_idle_fraction") 2311001SN/A .desc("Percentage of non-idle cycles") 2321001SN/A ; 2331001SN/A 2342SN/A idleFraction 2352SN/A .name(name() + ".idle_fraction") 2362SN/A .desc("Percentage of idle cycles") 2372SN/A ; 2382SN/A 2397897Shestness@cs.utexas.edu numBusyCycles 2407897Shestness@cs.utexas.edu .name(name() + ".num_busy_cycles") 2417897Shestness@cs.utexas.edu .desc("Number of busy cycles") 2427897Shestness@cs.utexas.edu ; 2437897Shestness@cs.utexas.edu 2447897Shestness@cs.utexas.edu numIdleCycles 2457897Shestness@cs.utexas.edu .name(name()+".num_idle_cycles") 2467897Shestness@cs.utexas.edu .desc("Number of idle cycles") 2477897Shestness@cs.utexas.edu ; 2487897Shestness@cs.utexas.edu 2492SN/A icacheStallCycles 2502SN/A .name(name() + ".icache_stall_cycles") 2512SN/A .desc("ICache total stall cycles") 2522SN/A .prereq(icacheStallCycles) 2532SN/A ; 2542SN/A 2552SN/A dcacheStallCycles 2562SN/A .name(name() + ".dcache_stall_cycles") 2572SN/A .desc("DCache total stall cycles") 2582SN/A .prereq(dcacheStallCycles) 2592SN/A ; 2602SN/A 2612390SN/A icacheRetryCycles 2622390SN/A .name(name() + ".icache_retry_cycles") 2632390SN/A .desc("ICache total retry cycles") 2642390SN/A .prereq(icacheRetryCycles) 2652390SN/A ; 2662390SN/A 2672390SN/A dcacheRetryCycles 2682390SN/A .name(name() + ".dcache_retry_cycles") 2692390SN/A .desc("DCache total retry cycles") 2702390SN/A .prereq(dcacheRetryCycles) 2712390SN/A ; 2722390SN/A 273385SN/A idleFraction = constant(1.0) - notIdleFraction; 2747897Shestness@cs.utexas.edu numIdleCycles = idleFraction * numCycles; 2757897Shestness@cs.utexas.edu numBusyCycles = (notIdleFraction)*numCycles; 2762SN/A} 2772SN/A 2782SN/Avoid 2792623SN/ABaseSimpleCPU::resetStats() 280334SN/A{ 2812361SN/A// startNumInst = numInst; 2825496Ssaidi@eecs.umich.edu notIdleFraction = (_status != Idle); 283334SN/A} 284334SN/A 285334SN/Avoid 2862623SN/ABaseSimpleCPU::serialize(ostream &os) 2872SN/A{ 2885496Ssaidi@eecs.umich.edu SERIALIZE_ENUM(_status); 289921SN/A BaseCPU::serialize(os); 2902915Sktlim@umich.edu// SERIALIZE_SCALAR(inst); 2912915Sktlim@umich.edu nameOut(os, csprintf("%s.xc.0", name())); 2922683Sktlim@umich.edu thread->serialize(os); 2932SN/A} 2942SN/A 2952SN/Avoid 2962623SN/ABaseSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 2972SN/A{ 2985496Ssaidi@eecs.umich.edu UNSERIALIZE_ENUM(_status); 299921SN/A BaseCPU::unserialize(cp, section); 3002915Sktlim@umich.edu// UNSERIALIZE_SCALAR(inst); 3012915Sktlim@umich.edu thread->unserialize(cp, csprintf("%s.xc.0", section)); 3022SN/A} 3032SN/A 3042SN/Avoid 3056221Snate@binkert.orgchange_thread_state(ThreadID tid, int activate, int priority) 3062SN/A{ 3072SN/A} 3082SN/A 3092SN/AAddr 3102623SN/ABaseSimpleCPU::dbg_vtophys(Addr addr) 3112SN/A{ 3122680Sktlim@umich.edu return vtophys(tc, addr); 3132SN/A} 3142SN/A 3152SN/Avoid 3165807Snate@binkert.orgBaseSimpleCPU::wakeup() 3172SN/A{ 3185807Snate@binkert.org if (thread->status() != ThreadContext::Suspended) 3195807Snate@binkert.org return; 3202SN/A 3215807Snate@binkert.org DPRINTF(Quiesce,"Suspended Processor awoke\n"); 3225807Snate@binkert.org thread->activate(); 3232SN/A} 3242SN/A 3252SN/Avoid 3262623SN/ABaseSimpleCPU::checkForInterrupts() 3272SN/A{ 3285704Snate@binkert.org if (checkInterrupts(tc)) { 3295647Sgblack@eecs.umich.edu Fault interrupt = interrupts->getInterrupt(tc); 3302SN/A 3313520Sgblack@eecs.umich.edu if (interrupt != NoFault) { 3327338SAli.Saidi@ARM.com fetchOffset = 0; 3335647Sgblack@eecs.umich.edu interrupts->updateIntrInfo(tc); 3343520Sgblack@eecs.umich.edu interrupt->invoke(tc); 3357408Sgblack@eecs.umich.edu predecoder.reset(); 3362SN/A } 3372SN/A } 3382623SN/A} 3392SN/A 3402623SN/A 3415894Sgblack@eecs.umich.eduvoid 3422662Sstever@eecs.umich.eduBaseSimpleCPU::setupFetchRequest(Request *req) 3432623SN/A{ 3447720Sgblack@eecs.umich.edu Addr instAddr = thread->instAddr(); 3454495Sacolyte@umich.edu 3462623SN/A // set up memory request for instruction fetch 3477720Sgblack@eecs.umich.edu DPRINTF(Fetch, "Fetch: PC:%08p\n", instAddr); 3482623SN/A 3497720Sgblack@eecs.umich.edu Addr fetchPC = (instAddr & PCMask) + fetchOffset; 3508832SAli.Saidi@ARM.com req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instMasterId(), 3518832SAli.Saidi@ARM.com instAddr); 3522623SN/A} 3532623SN/A 3542623SN/A 3552623SN/Avoid 3562623SN/ABaseSimpleCPU::preExecute() 3572623SN/A{ 3582SN/A // maintain $r0 semantics 3592683Sktlim@umich.edu thread->setIntReg(ZeroReg, 0); 3602427SN/A#if THE_ISA == ALPHA_ISA 3612683Sktlim@umich.edu thread->setFloatReg(ZeroReg, 0.0); 3622427SN/A#endif // ALPHA_ISA 3632SN/A 3642623SN/A // check for instruction-count-based events 3652623SN/A comInstEventQueue[0]->serviceEvents(numInst); 3667897Shestness@cs.utexas.edu system->instEventQueue.serviceEvents(system->totalNumInsts); 3672SN/A 3682623SN/A // decode the instruction 3692623SN/A inst = gtoh(inst); 3704377Sgblack@eecs.umich.edu 3717720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 3724377Sgblack@eecs.umich.edu 3737720Sgblack@eecs.umich.edu if (isRomMicroPC(pcState.microPC())) { 3745665Sgblack@eecs.umich.edu stayAtPC = false; 3757720Sgblack@eecs.umich.edu curStaticInst = microcodeRom.fetchMicroop(pcState.microPC(), 3767720Sgblack@eecs.umich.edu curMacroStaticInst); 3775665Sgblack@eecs.umich.edu } else if (!curMacroStaticInst) { 3785665Sgblack@eecs.umich.edu //We're not in the middle of a macro instruction 3794181Sgblack@eecs.umich.edu StaticInstPtr instPtr = NULL; 3804181Sgblack@eecs.umich.edu 3814181Sgblack@eecs.umich.edu //Predecode, ie bundle up an ExtMachInst 3824182Sgblack@eecs.umich.edu //This should go away once the constructor can be set up properly 3834182Sgblack@eecs.umich.edu predecoder.setTC(thread->getTC()); 3844182Sgblack@eecs.umich.edu //If more fetch data is needed, pass it in. 3857720Sgblack@eecs.umich.edu Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset; 3864593Sgblack@eecs.umich.edu //if(predecoder.needMoreBytes()) 3877720Sgblack@eecs.umich.edu predecoder.moreBytes(pcState, fetchPC, inst); 3884593Sgblack@eecs.umich.edu //else 3894593Sgblack@eecs.umich.edu // predecoder.process(); 3904377Sgblack@eecs.umich.edu 3914377Sgblack@eecs.umich.edu //If an instruction is ready, decode it. Otherwise, we'll have to 3924377Sgblack@eecs.umich.edu //fetch beyond the MachInst at the current pc. 3934377Sgblack@eecs.umich.edu if (predecoder.extMachInstReady()) { 3944377Sgblack@eecs.umich.edu stayAtPC = false; 3957720Sgblack@eecs.umich.edu ExtMachInst machInst = predecoder.getExtMachInst(pcState); 3967720Sgblack@eecs.umich.edu thread->pcState(pcState); 3978541Sgblack@eecs.umich.edu instPtr = thread->decoder.decode(machInst, pcState.instAddr()); 3984377Sgblack@eecs.umich.edu } else { 3994377Sgblack@eecs.umich.edu stayAtPC = true; 4004377Sgblack@eecs.umich.edu fetchOffset += sizeof(MachInst); 4014377Sgblack@eecs.umich.edu } 4024181Sgblack@eecs.umich.edu 4034181Sgblack@eecs.umich.edu //If we decoded an instruction and it's microcoded, start pulling 4044181Sgblack@eecs.umich.edu //out micro ops 4054539Sgblack@eecs.umich.edu if (instPtr && instPtr->isMacroop()) { 4063276Sgblack@eecs.umich.edu curMacroStaticInst = instPtr; 4077720Sgblack@eecs.umich.edu curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC()); 4083280Sgblack@eecs.umich.edu } else { 4093280Sgblack@eecs.umich.edu curStaticInst = instPtr; 4103276Sgblack@eecs.umich.edu } 4113276Sgblack@eecs.umich.edu } else { 4123276Sgblack@eecs.umich.edu //Read the next micro op from the macro op 4137720Sgblack@eecs.umich.edu curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC()); 4143276Sgblack@eecs.umich.edu } 4153276Sgblack@eecs.umich.edu 4164181Sgblack@eecs.umich.edu //If we decoded an instruction this "tick", record information about it. 4174181Sgblack@eecs.umich.edu if(curStaticInst) 4184181Sgblack@eecs.umich.edu { 4194522Ssaidi@eecs.umich.edu#if TRACING_ON 4207823Ssteve.reinhardt@amd.com traceData = tracer->getInstRecord(curTick(), tc, 4217720Sgblack@eecs.umich.edu curStaticInst, thread->pcState(), curMacroStaticInst); 4222470SN/A 4234181Sgblack@eecs.umich.edu DPRINTF(Decode,"Decode: Decoded %s instruction: 0x%x\n", 4244181Sgblack@eecs.umich.edu curStaticInst->getName(), curStaticInst->machInst); 4254522Ssaidi@eecs.umich.edu#endif // TRACING_ON 4264181Sgblack@eecs.umich.edu } 4272623SN/A} 4282623SN/A 4292623SN/Avoid 4302623SN/ABaseSimpleCPU::postExecute() 4312623SN/A{ 4327720Sgblack@eecs.umich.edu assert(curStaticInst); 4337720Sgblack@eecs.umich.edu 4347720Sgblack@eecs.umich.edu TheISA::PCState pc = tc->pcState(); 4357720Sgblack@eecs.umich.edu Addr instAddr = pc.instAddr(); 4368780Sgblack@eecs.umich.edu if (FullSystem && thread->profile) { 4373577Sgblack@eecs.umich.edu bool usermode = TheISA::inUserMode(tc); 4387720Sgblack@eecs.umich.edu thread->profilePC = usermode ? 1 : instAddr; 4395086Sgblack@eecs.umich.edu ProfileNode *node = thread->profile->consume(tc, curStaticInst); 4402623SN/A if (node) 4412683Sktlim@umich.edu thread->profileNode = node; 4422623SN/A } 4432SN/A 4442623SN/A if (curStaticInst->isMemRef()) { 4452623SN/A numMemRefs++; 4462SN/A } 4472SN/A 4482623SN/A if (curStaticInst->isLoad()) { 4492623SN/A ++numLoad; 4502623SN/A comLoadEventQueue[0]->serviceEvents(numLoad); 4512623SN/A } 4522SN/A 4535953Ssaidi@eecs.umich.edu if (CPA::available()) { 4547720Sgblack@eecs.umich.edu CPA::cpa()->swAutoBegin(tc, pc.nextInstAddr()); 4555953Ssaidi@eecs.umich.edu } 4565953Ssaidi@eecs.umich.edu 4577897Shestness@cs.utexas.edu /* Power model statistics */ 4587897Shestness@cs.utexas.edu //integer alu accesses 4597897Shestness@cs.utexas.edu if (curStaticInst->isInteger()){ 4607897Shestness@cs.utexas.edu numIntAluAccesses++; 4617897Shestness@cs.utexas.edu numIntInsts++; 4627897Shestness@cs.utexas.edu } 4637897Shestness@cs.utexas.edu 4647897Shestness@cs.utexas.edu //float alu accesses 4657897Shestness@cs.utexas.edu if (curStaticInst->isFloating()){ 4667897Shestness@cs.utexas.edu numFpAluAccesses++; 4677897Shestness@cs.utexas.edu numFpInsts++; 4687897Shestness@cs.utexas.edu } 4697897Shestness@cs.utexas.edu 4707897Shestness@cs.utexas.edu //number of function calls/returns to get window accesses 4717897Shestness@cs.utexas.edu if (curStaticInst->isCall() || curStaticInst->isReturn()){ 4727897Shestness@cs.utexas.edu numCallsReturns++; 4737897Shestness@cs.utexas.edu } 4747897Shestness@cs.utexas.edu 4757897Shestness@cs.utexas.edu //the number of branch predictions that will be made 4767897Shestness@cs.utexas.edu if (curStaticInst->isCondCtrl()){ 4777897Shestness@cs.utexas.edu numCondCtrlInsts++; 4787897Shestness@cs.utexas.edu } 4797897Shestness@cs.utexas.edu 4807897Shestness@cs.utexas.edu //result bus acceses 4817897Shestness@cs.utexas.edu if (curStaticInst->isLoad()){ 4827897Shestness@cs.utexas.edu numLoadInsts++; 4837897Shestness@cs.utexas.edu } 4847897Shestness@cs.utexas.edu 4857897Shestness@cs.utexas.edu if (curStaticInst->isStore()){ 4867897Shestness@cs.utexas.edu numStoreInsts++; 4877897Shestness@cs.utexas.edu } 4887897Shestness@cs.utexas.edu /* End power model statistics */ 4897897Shestness@cs.utexas.edu 4908780Sgblack@eecs.umich.edu if (FullSystem) 4918780Sgblack@eecs.umich.edu traceFunctions(instAddr); 4922644Sstever@eecs.umich.edu 4932644Sstever@eecs.umich.edu if (traceData) { 4944046Sbinkertn@umich.edu traceData->dump(); 4954046Sbinkertn@umich.edu delete traceData; 4964046Sbinkertn@umich.edu traceData = NULL; 4972644Sstever@eecs.umich.edu } 4982623SN/A} 4992SN/A 5002SN/A 5012623SN/Avoid 5022623SN/ABaseSimpleCPU::advancePC(Fault fault) 5032623SN/A{ 5044377Sgblack@eecs.umich.edu //Since we're moving to a new pc, zero out the offset 5054377Sgblack@eecs.umich.edu fetchOffset = 0; 5062090SN/A if (fault != NoFault) { 5073905Ssaidi@eecs.umich.edu curMacroStaticInst = StaticInst::nullStaticInstPtr; 5087678Sgblack@eecs.umich.edu fault->invoke(tc, curStaticInst); 5095120Sgblack@eecs.umich.edu predecoder.reset(); 5104377Sgblack@eecs.umich.edu } else { 5117720Sgblack@eecs.umich.edu if (curStaticInst) { 5127720Sgblack@eecs.umich.edu if (curStaticInst->isLastMicroop()) 5137720Sgblack@eecs.umich.edu curMacroStaticInst = StaticInst::nullStaticInstPtr; 5147720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 5157720Sgblack@eecs.umich.edu TheISA::advancePC(pcState, curStaticInst); 5167720Sgblack@eecs.umich.edu thread->pcState(pcState); 5173276Sgblack@eecs.umich.edu } 5182SN/A } 5192SN/A} 5202SN/A 5215250Sksewell@umich.edu/*Fault 5225222Sksewell@umich.eduBaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr) 5235222Sksewell@umich.edu{ 5245222Sksewell@umich.edu // translate to physical address 5255222Sksewell@umich.edu Fault fault = NoFault; 5265222Sksewell@umich.edu int CacheID = Op & 0x3; // Lower 3 bits identify Cache 5275222Sksewell@umich.edu int CacheOP = Op >> 2; // Upper 3 bits identify Cache Operation 5285222Sksewell@umich.edu if(CacheID > 1) 5295222Sksewell@umich.edu { 5305222Sksewell@umich.edu warn("CacheOps not implemented for secondary/tertiary caches\n"); 5315222Sksewell@umich.edu } 5325222Sksewell@umich.edu else 5335222Sksewell@umich.edu { 5345222Sksewell@umich.edu switch(CacheOP) 5355222Sksewell@umich.edu { // Fill Packet Type 5365222Sksewell@umich.edu case 0: warn("Invalidate Cache Op\n"); 5375222Sksewell@umich.edu break; 5385222Sksewell@umich.edu case 1: warn("Index Load Tag Cache Op\n"); 5395222Sksewell@umich.edu break; 5405222Sksewell@umich.edu case 2: warn("Index Store Tag Cache Op\n"); 5415222Sksewell@umich.edu break; 5425222Sksewell@umich.edu case 4: warn("Hit Invalidate Cache Op\n"); 5435222Sksewell@umich.edu break; 5445222Sksewell@umich.edu case 5: warn("Fill/Hit Writeback Invalidate Cache Op\n"); 5455222Sksewell@umich.edu break; 5465222Sksewell@umich.edu case 6: warn("Hit Writeback\n"); 5475222Sksewell@umich.edu break; 5485222Sksewell@umich.edu case 7: warn("Fetch & Lock Cache Op\n"); 5495222Sksewell@umich.edu break; 5505222Sksewell@umich.edu default: warn("Unimplemented Cache Op\n"); 5515222Sksewell@umich.edu } 5525222Sksewell@umich.edu } 5535222Sksewell@umich.edu return fault; 5545250Sksewell@umich.edu}*/ 555