base.cc revision 8876
12SN/A/* 28733Sgeoffrey.blake@arm.com * Copyright (c) 2010-2011 ARM Limited 37338SAli.Saidi@ARM.com * All rights reserved 47338SAli.Saidi@ARM.com * 57338SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67338SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77338SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87338SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97338SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107338SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117338SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127338SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137338SAli.Saidi@ARM.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152SN/A * All rights reserved. 162SN/A * 172SN/A * Redistribution and use in source and binary forms, with or without 182SN/A * modification, are permitted provided that the following conditions are 192SN/A * met: redistributions of source code must retain the above copyright 202SN/A * notice, this list of conditions and the following disclaimer; 212SN/A * redistributions in binary form must reproduce the above copyright 222SN/A * notice, this list of conditions and the following disclaimer in the 232SN/A * documentation and/or other materials provided with the distribution; 242SN/A * neither the name of the copyright holders nor the names of its 252SN/A * contributors may be used to endorse or promote products derived from 262SN/A * this software without specific prior written permission. 272SN/A * 282SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 412SN/A */ 422SN/A 438779Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 448779Sgblack@eecs.umich.edu#include "arch/stacktrace.hh" 458779Sgblack@eecs.umich.edu#include "arch/tlb.hh" 462439SN/A#include "arch/utility.hh" 478779Sgblack@eecs.umich.edu#include "arch/vtophys.hh" 488229Snate@binkert.org#include "base/loader/symtab.hh" 496216Snate@binkert.org#include "base/cp_annotate.hh" 50146SN/A#include "base/cprintf.hh" 51146SN/A#include "base/inifile.hh" 52146SN/A#include "base/misc.hh" 53146SN/A#include "base/pollevent.hh" 54146SN/A#include "base/range.hh" 55146SN/A#include "base/trace.hh" 566216Snate@binkert.org#include "base/types.hh" 576658Snate@binkert.org#include "config/the_isa.hh" 588733Sgeoffrey.blake@arm.com#include "config/use_checker.hh" 598229Snate@binkert.org#include "cpu/simple/base.hh" 601717SN/A#include "cpu/base.hh" 61146SN/A#include "cpu/exetrace.hh" 621977SN/A#include "cpu/profile.hh" 632683Sktlim@umich.edu#include "cpu/simple_thread.hh" 641717SN/A#include "cpu/smt.hh" 65146SN/A#include "cpu/static_inst.hh" 662683Sktlim@umich.edu#include "cpu/thread_context.hh" 678232Snate@binkert.org#include "debug/Decode.hh" 688232Snate@binkert.org#include "debug/Fetch.hh" 698232Snate@binkert.org#include "debug/Quiesce.hh" 708779Sgblack@eecs.umich.edu#include "mem/mem_object.hh" 713348Sbinkertn@umich.edu#include "mem/packet.hh" 726105Ssteve.reinhardt@amd.com#include "mem/request.hh" 736216Snate@binkert.org#include "params/BaseSimpleCPU.hh" 742036SN/A#include "sim/byteswap.hh" 75146SN/A#include "sim/debug.hh" 768817Sgblack@eecs.umich.edu#include "sim/faults.hh" 778793Sgblack@eecs.umich.edu#include "sim/full_system.hh" 7856SN/A#include "sim/sim_events.hh" 7956SN/A#include "sim/sim_object.hh" 80695SN/A#include "sim/stats.hh" 812901Ssaidi@eecs.umich.edu#include "sim/system.hh" 822SN/A 838733Sgeoffrey.blake@arm.com#if USE_CHECKER 848733Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 858733Sgeoffrey.blake@arm.com#include "cpu/checker/thread_context.hh" 868733Sgeoffrey.blake@arm.com#endif 878733Sgeoffrey.blake@arm.com 882SN/Ausing namespace std; 892449SN/Ausing namespace TheISA; 901355SN/A 915529Snate@binkert.orgBaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p) 924495Sacolyte@umich.edu : BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL) 93224SN/A{ 948793Sgblack@eecs.umich.edu if (FullSystem) 958793Sgblack@eecs.umich.edu thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb); 968793Sgblack@eecs.umich.edu else 978820Sgblack@eecs.umich.edu thread = new SimpleThread(this, /* thread_num */ 0, p->system, 988820Sgblack@eecs.umich.edu p->workload[0], p->itb, p->dtb); 992SN/A 1006029Ssteve.reinhardt@amd.com thread->setStatus(ThreadContext::Halted); 1012672Sktlim@umich.edu 1022683Sktlim@umich.edu tc = thread->getTC(); 1032SN/A 1048733Sgeoffrey.blake@arm.com#if USE_CHECKER 1058733Sgeoffrey.blake@arm.com if (p->checker) { 1068733Sgeoffrey.blake@arm.com BaseCPU *temp_checker = p->checker; 1078733Sgeoffrey.blake@arm.com checker = dynamic_cast<CheckerCPU *>(temp_checker); 1088733Sgeoffrey.blake@arm.com checker->setSystem(p->system); 1098733Sgeoffrey.blake@arm.com // Manipulate thread context 1108733Sgeoffrey.blake@arm.com ThreadContext *cpu_tc = tc; 1118733Sgeoffrey.blake@arm.com tc = new CheckerThreadContext<ThreadContext>(cpu_tc, this->checker); 1128733Sgeoffrey.blake@arm.com } else { 1138733Sgeoffrey.blake@arm.com checker = NULL; 1148733Sgeoffrey.blake@arm.com } 1158733Sgeoffrey.blake@arm.com#endif 1168733Sgeoffrey.blake@arm.com 1172SN/A numInst = 0; 118334SN/A startNumInst = 0; 1198834Satgutier@umich.edu numOp = 0; 1208834Satgutier@umich.edu startNumOp = 0; 121140SN/A numLoad = 0; 122334SN/A startNumLoad = 0; 1232SN/A lastIcacheStall = 0; 1242SN/A lastDcacheStall = 0; 1252SN/A 1262680Sktlim@umich.edu threadContexts.push_back(tc); 1274377Sgblack@eecs.umich.edu 1285169Ssaidi@eecs.umich.edu 1294377Sgblack@eecs.umich.edu fetchOffset = 0; 1304377Sgblack@eecs.umich.edu stayAtPC = false; 1312SN/A} 1322SN/A 1332623SN/ABaseSimpleCPU::~BaseSimpleCPU() 1342SN/A{ 1352SN/A} 1362SN/A 137180SN/Avoid 1388737Skoansin.tan@gmail.comBaseSimpleCPU::deallocateContext(ThreadID thread_num) 139393SN/A{ 140393SN/A // for now, these are equivalent 141393SN/A suspendContext(thread_num); 142393SN/A} 143384SN/A 144384SN/A 145393SN/Avoid 1468737Skoansin.tan@gmail.comBaseSimpleCPU::haltContext(ThreadID thread_num) 147393SN/A{ 148393SN/A // for now, these are equivalent 149393SN/A suspendContext(thread_num); 150393SN/A} 151384SN/A 152189SN/A 153189SN/Avoid 1542623SN/ABaseSimpleCPU::regStats() 1552SN/A{ 156729SN/A using namespace Stats; 157334SN/A 1582SN/A BaseCPU::regStats(); 1592SN/A 1602SN/A numInsts 1618834Satgutier@umich.edu .name(name() + ".committedInsts") 1628834Satgutier@umich.edu .desc("Number of instructions committed") 1638834Satgutier@umich.edu ; 1648834Satgutier@umich.edu 1658834Satgutier@umich.edu numOps 1668834Satgutier@umich.edu .name(name() + ".committedOps") 1678834Satgutier@umich.edu .desc("Number of ops (including micro ops) committed") 1682SN/A ; 1692SN/A 1707897Shestness@cs.utexas.edu numIntAluAccesses 1717897Shestness@cs.utexas.edu .name(name() + ".num_int_alu_accesses") 1727897Shestness@cs.utexas.edu .desc("Number of integer alu accesses") 1737897Shestness@cs.utexas.edu ; 1747897Shestness@cs.utexas.edu 1757897Shestness@cs.utexas.edu numFpAluAccesses 1767897Shestness@cs.utexas.edu .name(name() + ".num_fp_alu_accesses") 1777897Shestness@cs.utexas.edu .desc("Number of float alu accesses") 1787897Shestness@cs.utexas.edu ; 1797897Shestness@cs.utexas.edu 1807897Shestness@cs.utexas.edu numCallsReturns 1817897Shestness@cs.utexas.edu .name(name() + ".num_func_calls") 1827897Shestness@cs.utexas.edu .desc("number of times a function call or return occured") 1837897Shestness@cs.utexas.edu ; 1847897Shestness@cs.utexas.edu 1857897Shestness@cs.utexas.edu numCondCtrlInsts 1867897Shestness@cs.utexas.edu .name(name() + ".num_conditional_control_insts") 1877897Shestness@cs.utexas.edu .desc("number of instructions that are conditional controls") 1887897Shestness@cs.utexas.edu ; 1897897Shestness@cs.utexas.edu 1907897Shestness@cs.utexas.edu numIntInsts 1917897Shestness@cs.utexas.edu .name(name() + ".num_int_insts") 1927897Shestness@cs.utexas.edu .desc("number of integer instructions") 1937897Shestness@cs.utexas.edu ; 1947897Shestness@cs.utexas.edu 1957897Shestness@cs.utexas.edu numFpInsts 1967897Shestness@cs.utexas.edu .name(name() + ".num_fp_insts") 1977897Shestness@cs.utexas.edu .desc("number of float instructions") 1987897Shestness@cs.utexas.edu ; 1997897Shestness@cs.utexas.edu 2007897Shestness@cs.utexas.edu numIntRegReads 2017897Shestness@cs.utexas.edu .name(name() + ".num_int_register_reads") 2027897Shestness@cs.utexas.edu .desc("number of times the integer registers were read") 2037897Shestness@cs.utexas.edu ; 2047897Shestness@cs.utexas.edu 2057897Shestness@cs.utexas.edu numIntRegWrites 2067897Shestness@cs.utexas.edu .name(name() + ".num_int_register_writes") 2077897Shestness@cs.utexas.edu .desc("number of times the integer registers were written") 2087897Shestness@cs.utexas.edu ; 2097897Shestness@cs.utexas.edu 2107897Shestness@cs.utexas.edu numFpRegReads 2117897Shestness@cs.utexas.edu .name(name() + ".num_fp_register_reads") 2127897Shestness@cs.utexas.edu .desc("number of times the floating registers were read") 2137897Shestness@cs.utexas.edu ; 2147897Shestness@cs.utexas.edu 2157897Shestness@cs.utexas.edu numFpRegWrites 2167897Shestness@cs.utexas.edu .name(name() + ".num_fp_register_writes") 2177897Shestness@cs.utexas.edu .desc("number of times the floating registers were written") 2187897Shestness@cs.utexas.edu ; 2197897Shestness@cs.utexas.edu 2202SN/A numMemRefs 2217897Shestness@cs.utexas.edu .name(name()+".num_mem_refs") 2227897Shestness@cs.utexas.edu .desc("number of memory refs") 2237897Shestness@cs.utexas.edu ; 2247897Shestness@cs.utexas.edu 2257897Shestness@cs.utexas.edu numStoreInsts 2267897Shestness@cs.utexas.edu .name(name() + ".num_store_insts") 2277897Shestness@cs.utexas.edu .desc("Number of store instructions") 2287897Shestness@cs.utexas.edu ; 2297897Shestness@cs.utexas.edu 2307897Shestness@cs.utexas.edu numLoadInsts 2317897Shestness@cs.utexas.edu .name(name() + ".num_load_insts") 2327897Shestness@cs.utexas.edu .desc("Number of load instructions") 2332SN/A ; 2342SN/A 2351001SN/A notIdleFraction 2361001SN/A .name(name() + ".not_idle_fraction") 2371001SN/A .desc("Percentage of non-idle cycles") 2381001SN/A ; 2391001SN/A 2402SN/A idleFraction 2412SN/A .name(name() + ".idle_fraction") 2422SN/A .desc("Percentage of idle cycles") 2432SN/A ; 2442SN/A 2457897Shestness@cs.utexas.edu numBusyCycles 2467897Shestness@cs.utexas.edu .name(name() + ".num_busy_cycles") 2477897Shestness@cs.utexas.edu .desc("Number of busy cycles") 2487897Shestness@cs.utexas.edu ; 2497897Shestness@cs.utexas.edu 2507897Shestness@cs.utexas.edu numIdleCycles 2517897Shestness@cs.utexas.edu .name(name()+".num_idle_cycles") 2527897Shestness@cs.utexas.edu .desc("Number of idle cycles") 2537897Shestness@cs.utexas.edu ; 2547897Shestness@cs.utexas.edu 2552SN/A icacheStallCycles 2562SN/A .name(name() + ".icache_stall_cycles") 2572SN/A .desc("ICache total stall cycles") 2582SN/A .prereq(icacheStallCycles) 2592SN/A ; 2602SN/A 2612SN/A dcacheStallCycles 2622SN/A .name(name() + ".dcache_stall_cycles") 2632SN/A .desc("DCache total stall cycles") 2642SN/A .prereq(dcacheStallCycles) 2652SN/A ; 2662SN/A 2672390SN/A icacheRetryCycles 2682390SN/A .name(name() + ".icache_retry_cycles") 2692390SN/A .desc("ICache total retry cycles") 2702390SN/A .prereq(icacheRetryCycles) 2712390SN/A ; 2722390SN/A 2732390SN/A dcacheRetryCycles 2742390SN/A .name(name() + ".dcache_retry_cycles") 2752390SN/A .desc("DCache total retry cycles") 2762390SN/A .prereq(dcacheRetryCycles) 2772390SN/A ; 2782390SN/A 279385SN/A idleFraction = constant(1.0) - notIdleFraction; 2807897Shestness@cs.utexas.edu numIdleCycles = idleFraction * numCycles; 2817897Shestness@cs.utexas.edu numBusyCycles = (notIdleFraction)*numCycles; 2822SN/A} 2832SN/A 2842SN/Avoid 2852623SN/ABaseSimpleCPU::resetStats() 286334SN/A{ 2872361SN/A// startNumInst = numInst; 2885496Ssaidi@eecs.umich.edu notIdleFraction = (_status != Idle); 289334SN/A} 290334SN/A 291334SN/Avoid 2922623SN/ABaseSimpleCPU::serialize(ostream &os) 2932SN/A{ 2945496Ssaidi@eecs.umich.edu SERIALIZE_ENUM(_status); 295921SN/A BaseCPU::serialize(os); 2962915Sktlim@umich.edu// SERIALIZE_SCALAR(inst); 2972915Sktlim@umich.edu nameOut(os, csprintf("%s.xc.0", name())); 2982683Sktlim@umich.edu thread->serialize(os); 2992SN/A} 3002SN/A 3012SN/Avoid 3022623SN/ABaseSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 3032SN/A{ 3045496Ssaidi@eecs.umich.edu UNSERIALIZE_ENUM(_status); 305921SN/A BaseCPU::unserialize(cp, section); 3062915Sktlim@umich.edu// UNSERIALIZE_SCALAR(inst); 3072915Sktlim@umich.edu thread->unserialize(cp, csprintf("%s.xc.0", section)); 3082SN/A} 3092SN/A 3102SN/Avoid 3116221Snate@binkert.orgchange_thread_state(ThreadID tid, int activate, int priority) 3122SN/A{ 3132SN/A} 3142SN/A 3152SN/AAddr 3162623SN/ABaseSimpleCPU::dbg_vtophys(Addr addr) 3172SN/A{ 3182680Sktlim@umich.edu return vtophys(tc, addr); 3192SN/A} 3202SN/A 3212SN/Avoid 3225807Snate@binkert.orgBaseSimpleCPU::wakeup() 3232SN/A{ 3245807Snate@binkert.org if (thread->status() != ThreadContext::Suspended) 3255807Snate@binkert.org return; 3262SN/A 3275807Snate@binkert.org DPRINTF(Quiesce,"Suspended Processor awoke\n"); 3285807Snate@binkert.org thread->activate(); 3292SN/A} 3302SN/A 3312SN/Avoid 3322623SN/ABaseSimpleCPU::checkForInterrupts() 3332SN/A{ 3345704Snate@binkert.org if (checkInterrupts(tc)) { 3355647Sgblack@eecs.umich.edu Fault interrupt = interrupts->getInterrupt(tc); 3362SN/A 3373520Sgblack@eecs.umich.edu if (interrupt != NoFault) { 3387338SAli.Saidi@ARM.com fetchOffset = 0; 3395647Sgblack@eecs.umich.edu interrupts->updateIntrInfo(tc); 3403520Sgblack@eecs.umich.edu interrupt->invoke(tc); 3417408Sgblack@eecs.umich.edu predecoder.reset(); 3422SN/A } 3432SN/A } 3442623SN/A} 3452SN/A 3462623SN/A 3475894Sgblack@eecs.umich.eduvoid 3482662Sstever@eecs.umich.eduBaseSimpleCPU::setupFetchRequest(Request *req) 3492623SN/A{ 3507720Sgblack@eecs.umich.edu Addr instAddr = thread->instAddr(); 3514495Sacolyte@umich.edu 3522623SN/A // set up memory request for instruction fetch 3537720Sgblack@eecs.umich.edu DPRINTF(Fetch, "Fetch: PC:%08p\n", instAddr); 3542623SN/A 3557720Sgblack@eecs.umich.edu Addr fetchPC = (instAddr & PCMask) + fetchOffset; 3568832SAli.Saidi@ARM.com req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instMasterId(), 3578832SAli.Saidi@ARM.com instAddr); 3582623SN/A} 3592623SN/A 3602623SN/A 3612623SN/Avoid 3622623SN/ABaseSimpleCPU::preExecute() 3632623SN/A{ 3642SN/A // maintain $r0 semantics 3652683Sktlim@umich.edu thread->setIntReg(ZeroReg, 0); 3662427SN/A#if THE_ISA == ALPHA_ISA 3672683Sktlim@umich.edu thread->setFloatReg(ZeroReg, 0.0); 3682427SN/A#endif // ALPHA_ISA 3692SN/A 3702623SN/A // check for instruction-count-based events 3712623SN/A comInstEventQueue[0]->serviceEvents(numInst); 3727897Shestness@cs.utexas.edu system->instEventQueue.serviceEvents(system->totalNumInsts); 3732SN/A 3742623SN/A // decode the instruction 3752623SN/A inst = gtoh(inst); 3764377Sgblack@eecs.umich.edu 3777720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 3784377Sgblack@eecs.umich.edu 3797720Sgblack@eecs.umich.edu if (isRomMicroPC(pcState.microPC())) { 3805665Sgblack@eecs.umich.edu stayAtPC = false; 3817720Sgblack@eecs.umich.edu curStaticInst = microcodeRom.fetchMicroop(pcState.microPC(), 3827720Sgblack@eecs.umich.edu curMacroStaticInst); 3835665Sgblack@eecs.umich.edu } else if (!curMacroStaticInst) { 3845665Sgblack@eecs.umich.edu //We're not in the middle of a macro instruction 3854181Sgblack@eecs.umich.edu StaticInstPtr instPtr = NULL; 3864181Sgblack@eecs.umich.edu 3874181Sgblack@eecs.umich.edu //Predecode, ie bundle up an ExtMachInst 3884182Sgblack@eecs.umich.edu //This should go away once the constructor can be set up properly 3894182Sgblack@eecs.umich.edu predecoder.setTC(thread->getTC()); 3904182Sgblack@eecs.umich.edu //If more fetch data is needed, pass it in. 3917720Sgblack@eecs.umich.edu Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset; 3924593Sgblack@eecs.umich.edu //if(predecoder.needMoreBytes()) 3937720Sgblack@eecs.umich.edu predecoder.moreBytes(pcState, fetchPC, inst); 3944593Sgblack@eecs.umich.edu //else 3954593Sgblack@eecs.umich.edu // predecoder.process(); 3964377Sgblack@eecs.umich.edu 3974377Sgblack@eecs.umich.edu //If an instruction is ready, decode it. Otherwise, we'll have to 3984377Sgblack@eecs.umich.edu //fetch beyond the MachInst at the current pc. 3994377Sgblack@eecs.umich.edu if (predecoder.extMachInstReady()) { 4004377Sgblack@eecs.umich.edu stayAtPC = false; 4017720Sgblack@eecs.umich.edu ExtMachInst machInst = predecoder.getExtMachInst(pcState); 4027720Sgblack@eecs.umich.edu thread->pcState(pcState); 4038541Sgblack@eecs.umich.edu instPtr = thread->decoder.decode(machInst, pcState.instAddr()); 4044377Sgblack@eecs.umich.edu } else { 4054377Sgblack@eecs.umich.edu stayAtPC = true; 4064377Sgblack@eecs.umich.edu fetchOffset += sizeof(MachInst); 4074377Sgblack@eecs.umich.edu } 4084181Sgblack@eecs.umich.edu 4094181Sgblack@eecs.umich.edu //If we decoded an instruction and it's microcoded, start pulling 4104181Sgblack@eecs.umich.edu //out micro ops 4114539Sgblack@eecs.umich.edu if (instPtr && instPtr->isMacroop()) { 4123276Sgblack@eecs.umich.edu curMacroStaticInst = instPtr; 4137720Sgblack@eecs.umich.edu curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC()); 4143280Sgblack@eecs.umich.edu } else { 4153280Sgblack@eecs.umich.edu curStaticInst = instPtr; 4163276Sgblack@eecs.umich.edu } 4173276Sgblack@eecs.umich.edu } else { 4183276Sgblack@eecs.umich.edu //Read the next micro op from the macro op 4197720Sgblack@eecs.umich.edu curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC()); 4203276Sgblack@eecs.umich.edu } 4213276Sgblack@eecs.umich.edu 4224181Sgblack@eecs.umich.edu //If we decoded an instruction this "tick", record information about it. 4234181Sgblack@eecs.umich.edu if(curStaticInst) 4244181Sgblack@eecs.umich.edu { 4254522Ssaidi@eecs.umich.edu#if TRACING_ON 4267823Ssteve.reinhardt@amd.com traceData = tracer->getInstRecord(curTick(), tc, 4277720Sgblack@eecs.umich.edu curStaticInst, thread->pcState(), curMacroStaticInst); 4282470SN/A 4294181Sgblack@eecs.umich.edu DPRINTF(Decode,"Decode: Decoded %s instruction: 0x%x\n", 4304181Sgblack@eecs.umich.edu curStaticInst->getName(), curStaticInst->machInst); 4314522Ssaidi@eecs.umich.edu#endif // TRACING_ON 4324181Sgblack@eecs.umich.edu } 4332623SN/A} 4342623SN/A 4352623SN/Avoid 4362623SN/ABaseSimpleCPU::postExecute() 4372623SN/A{ 4387720Sgblack@eecs.umich.edu assert(curStaticInst); 4397720Sgblack@eecs.umich.edu 4407720Sgblack@eecs.umich.edu TheISA::PCState pc = tc->pcState(); 4417720Sgblack@eecs.umich.edu Addr instAddr = pc.instAddr(); 4428780Sgblack@eecs.umich.edu if (FullSystem && thread->profile) { 4433577Sgblack@eecs.umich.edu bool usermode = TheISA::inUserMode(tc); 4447720Sgblack@eecs.umich.edu thread->profilePC = usermode ? 1 : instAddr; 4455086Sgblack@eecs.umich.edu ProfileNode *node = thread->profile->consume(tc, curStaticInst); 4462623SN/A if (node) 4472683Sktlim@umich.edu thread->profileNode = node; 4482623SN/A } 4492SN/A 4502623SN/A if (curStaticInst->isMemRef()) { 4512623SN/A numMemRefs++; 4522SN/A } 4532SN/A 4542623SN/A if (curStaticInst->isLoad()) { 4552623SN/A ++numLoad; 4562623SN/A comLoadEventQueue[0]->serviceEvents(numLoad); 4572623SN/A } 4582SN/A 4595953Ssaidi@eecs.umich.edu if (CPA::available()) { 4607720Sgblack@eecs.umich.edu CPA::cpa()->swAutoBegin(tc, pc.nextInstAddr()); 4615953Ssaidi@eecs.umich.edu } 4625953Ssaidi@eecs.umich.edu 4637897Shestness@cs.utexas.edu /* Power model statistics */ 4647897Shestness@cs.utexas.edu //integer alu accesses 4657897Shestness@cs.utexas.edu if (curStaticInst->isInteger()){ 4667897Shestness@cs.utexas.edu numIntAluAccesses++; 4677897Shestness@cs.utexas.edu numIntInsts++; 4687897Shestness@cs.utexas.edu } 4697897Shestness@cs.utexas.edu 4707897Shestness@cs.utexas.edu //float alu accesses 4717897Shestness@cs.utexas.edu if (curStaticInst->isFloating()){ 4727897Shestness@cs.utexas.edu numFpAluAccesses++; 4737897Shestness@cs.utexas.edu numFpInsts++; 4747897Shestness@cs.utexas.edu } 4757897Shestness@cs.utexas.edu 4767897Shestness@cs.utexas.edu //number of function calls/returns to get window accesses 4777897Shestness@cs.utexas.edu if (curStaticInst->isCall() || curStaticInst->isReturn()){ 4787897Shestness@cs.utexas.edu numCallsReturns++; 4797897Shestness@cs.utexas.edu } 4807897Shestness@cs.utexas.edu 4817897Shestness@cs.utexas.edu //the number of branch predictions that will be made 4827897Shestness@cs.utexas.edu if (curStaticInst->isCondCtrl()){ 4837897Shestness@cs.utexas.edu numCondCtrlInsts++; 4847897Shestness@cs.utexas.edu } 4857897Shestness@cs.utexas.edu 4867897Shestness@cs.utexas.edu //result bus acceses 4877897Shestness@cs.utexas.edu if (curStaticInst->isLoad()){ 4887897Shestness@cs.utexas.edu numLoadInsts++; 4897897Shestness@cs.utexas.edu } 4907897Shestness@cs.utexas.edu 4917897Shestness@cs.utexas.edu if (curStaticInst->isStore()){ 4927897Shestness@cs.utexas.edu numStoreInsts++; 4937897Shestness@cs.utexas.edu } 4947897Shestness@cs.utexas.edu /* End power model statistics */ 4957897Shestness@cs.utexas.edu 4968780Sgblack@eecs.umich.edu if (FullSystem) 4978780Sgblack@eecs.umich.edu traceFunctions(instAddr); 4982644Sstever@eecs.umich.edu 4992644Sstever@eecs.umich.edu if (traceData) { 5004046Sbinkertn@umich.edu traceData->dump(); 5014046Sbinkertn@umich.edu delete traceData; 5024046Sbinkertn@umich.edu traceData = NULL; 5032644Sstever@eecs.umich.edu } 5042623SN/A} 5052SN/A 5062SN/A 5072623SN/Avoid 5082623SN/ABaseSimpleCPU::advancePC(Fault fault) 5092623SN/A{ 5104377Sgblack@eecs.umich.edu //Since we're moving to a new pc, zero out the offset 5114377Sgblack@eecs.umich.edu fetchOffset = 0; 5122090SN/A if (fault != NoFault) { 5133905Ssaidi@eecs.umich.edu curMacroStaticInst = StaticInst::nullStaticInstPtr; 5147678Sgblack@eecs.umich.edu fault->invoke(tc, curStaticInst); 5155120Sgblack@eecs.umich.edu predecoder.reset(); 5164377Sgblack@eecs.umich.edu } else { 5177720Sgblack@eecs.umich.edu if (curStaticInst) { 5187720Sgblack@eecs.umich.edu if (curStaticInst->isLastMicroop()) 5197720Sgblack@eecs.umich.edu curMacroStaticInst = StaticInst::nullStaticInstPtr; 5207720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 5217720Sgblack@eecs.umich.edu TheISA::advancePC(pcState, curStaticInst); 5227720Sgblack@eecs.umich.edu thread->pcState(pcState); 5233276Sgblack@eecs.umich.edu } 5242SN/A } 5252SN/A} 5262SN/A 5275250Sksewell@umich.edu/*Fault 5285222Sksewell@umich.eduBaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr) 5295222Sksewell@umich.edu{ 5305222Sksewell@umich.edu // translate to physical address 5315222Sksewell@umich.edu Fault fault = NoFault; 5325222Sksewell@umich.edu int CacheID = Op & 0x3; // Lower 3 bits identify Cache 5335222Sksewell@umich.edu int CacheOP = Op >> 2; // Upper 3 bits identify Cache Operation 5345222Sksewell@umich.edu if(CacheID > 1) 5355222Sksewell@umich.edu { 5365222Sksewell@umich.edu warn("CacheOps not implemented for secondary/tertiary caches\n"); 5375222Sksewell@umich.edu } 5385222Sksewell@umich.edu else 5395222Sksewell@umich.edu { 5405222Sksewell@umich.edu switch(CacheOP) 5415222Sksewell@umich.edu { // Fill Packet Type 5425222Sksewell@umich.edu case 0: warn("Invalidate Cache Op\n"); 5435222Sksewell@umich.edu break; 5445222Sksewell@umich.edu case 1: warn("Index Load Tag Cache Op\n"); 5455222Sksewell@umich.edu break; 5465222Sksewell@umich.edu case 2: warn("Index Store Tag Cache Op\n"); 5475222Sksewell@umich.edu break; 5485222Sksewell@umich.edu case 4: warn("Hit Invalidate Cache Op\n"); 5495222Sksewell@umich.edu break; 5505222Sksewell@umich.edu case 5: warn("Fill/Hit Writeback Invalidate Cache Op\n"); 5515222Sksewell@umich.edu break; 5525222Sksewell@umich.edu case 6: warn("Hit Writeback\n"); 5535222Sksewell@umich.edu break; 5545222Sksewell@umich.edu case 7: warn("Fetch & Lock Cache Op\n"); 5555222Sksewell@umich.edu break; 5565222Sksewell@umich.edu default: warn("Unimplemented Cache Op\n"); 5575222Sksewell@umich.edu } 5585222Sksewell@umich.edu } 5595222Sksewell@umich.edu return fault; 5605250Sksewell@umich.edu}*/ 561