base.cc revision 8793
12SN/A/* 27338SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37338SAli.Saidi@ARM.com * All rights reserved 47338SAli.Saidi@ARM.com * 57338SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67338SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77338SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87338SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97338SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107338SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117338SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127338SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137338SAli.Saidi@ARM.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152SN/A * All rights reserved. 162SN/A * 172SN/A * Redistribution and use in source and binary forms, with or without 182SN/A * modification, are permitted provided that the following conditions are 192SN/A * met: redistributions of source code must retain the above copyright 202SN/A * notice, this list of conditions and the following disclaimer; 212SN/A * redistributions in binary form must reproduce the above copyright 222SN/A * notice, this list of conditions and the following disclaimer in the 232SN/A * documentation and/or other materials provided with the distribution; 242SN/A * neither the name of the copyright holders nor the names of its 252SN/A * contributors may be used to endorse or promote products derived from 262SN/A * this software without specific prior written permission. 272SN/A * 282SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 412SN/A */ 422SN/A 436216Snate@binkert.org#include "arch/faults.hh" 448779Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 458779Sgblack@eecs.umich.edu#include "arch/stacktrace.hh" 468779Sgblack@eecs.umich.edu#include "arch/tlb.hh" 472439SN/A#include "arch/utility.hh" 488779Sgblack@eecs.umich.edu#include "arch/vtophys.hh" 498229Snate@binkert.org#include "base/loader/symtab.hh" 506216Snate@binkert.org#include "base/cp_annotate.hh" 51146SN/A#include "base/cprintf.hh" 52146SN/A#include "base/inifile.hh" 53146SN/A#include "base/misc.hh" 54146SN/A#include "base/pollevent.hh" 55146SN/A#include "base/range.hh" 56146SN/A#include "base/trace.hh" 576216Snate@binkert.org#include "base/types.hh" 586658Snate@binkert.org#include "config/the_isa.hh" 598229Snate@binkert.org#include "cpu/simple/base.hh" 601717SN/A#include "cpu/base.hh" 61146SN/A#include "cpu/exetrace.hh" 621977SN/A#include "cpu/profile.hh" 632683Sktlim@umich.edu#include "cpu/simple_thread.hh" 641717SN/A#include "cpu/smt.hh" 65146SN/A#include "cpu/static_inst.hh" 662683Sktlim@umich.edu#include "cpu/thread_context.hh" 678232Snate@binkert.org#include "debug/Decode.hh" 688232Snate@binkert.org#include "debug/Fetch.hh" 698232Snate@binkert.org#include "debug/Quiesce.hh" 708779Sgblack@eecs.umich.edu#include "mem/mem_object.hh" 713348Sbinkertn@umich.edu#include "mem/packet.hh" 726105Ssteve.reinhardt@amd.com#include "mem/request.hh" 736216Snate@binkert.org#include "params/BaseSimpleCPU.hh" 742036SN/A#include "sim/byteswap.hh" 75146SN/A#include "sim/debug.hh" 768793Sgblack@eecs.umich.edu#include "sim/full_system.hh" 7756SN/A#include "sim/sim_events.hh" 7856SN/A#include "sim/sim_object.hh" 79695SN/A#include "sim/stats.hh" 802901Ssaidi@eecs.umich.edu#include "sim/system.hh" 812SN/A 822SN/Ausing namespace std; 832449SN/Ausing namespace TheISA; 841355SN/A 855529Snate@binkert.orgBaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p) 864495Sacolyte@umich.edu : BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL) 87224SN/A{ 888793Sgblack@eecs.umich.edu if (FullSystem) 898793Sgblack@eecs.umich.edu thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb); 908793Sgblack@eecs.umich.edu else 918793Sgblack@eecs.umich.edu thread = new SimpleThread(this, /* thread_num */ 0, p->workload[0], 928793Sgblack@eecs.umich.edu p->itb, p->dtb); 932SN/A 946029Ssteve.reinhardt@amd.com thread->setStatus(ThreadContext::Halted); 952672Sktlim@umich.edu 962683Sktlim@umich.edu tc = thread->getTC(); 972SN/A 982SN/A numInst = 0; 99334SN/A startNumInst = 0; 100140SN/A numLoad = 0; 101334SN/A startNumLoad = 0; 1022SN/A lastIcacheStall = 0; 1032SN/A lastDcacheStall = 0; 1042SN/A 1052680Sktlim@umich.edu threadContexts.push_back(tc); 1064377Sgblack@eecs.umich.edu 1075169Ssaidi@eecs.umich.edu 1084377Sgblack@eecs.umich.edu fetchOffset = 0; 1094377Sgblack@eecs.umich.edu stayAtPC = false; 1102SN/A} 1112SN/A 1122623SN/ABaseSimpleCPU::~BaseSimpleCPU() 1132SN/A{ 1142SN/A} 1152SN/A 116180SN/Avoid 1172623SN/ABaseSimpleCPU::deallocateContext(int thread_num) 118393SN/A{ 119393SN/A // for now, these are equivalent 120393SN/A suspendContext(thread_num); 121393SN/A} 122384SN/A 123384SN/A 124393SN/Avoid 1252623SN/ABaseSimpleCPU::haltContext(int thread_num) 126393SN/A{ 127393SN/A // for now, these are equivalent 128393SN/A suspendContext(thread_num); 129393SN/A} 130384SN/A 131189SN/A 132189SN/Avoid 1332623SN/ABaseSimpleCPU::regStats() 1342SN/A{ 135729SN/A using namespace Stats; 136334SN/A 1372SN/A BaseCPU::regStats(); 1382SN/A 1392SN/A numInsts 1402SN/A .name(name() + ".num_insts") 1412SN/A .desc("Number of instructions executed") 1422SN/A ; 1432SN/A 1447897Shestness@cs.utexas.edu numIntAluAccesses 1457897Shestness@cs.utexas.edu .name(name() + ".num_int_alu_accesses") 1467897Shestness@cs.utexas.edu .desc("Number of integer alu accesses") 1477897Shestness@cs.utexas.edu ; 1487897Shestness@cs.utexas.edu 1497897Shestness@cs.utexas.edu numFpAluAccesses 1507897Shestness@cs.utexas.edu .name(name() + ".num_fp_alu_accesses") 1517897Shestness@cs.utexas.edu .desc("Number of float alu accesses") 1527897Shestness@cs.utexas.edu ; 1537897Shestness@cs.utexas.edu 1547897Shestness@cs.utexas.edu numCallsReturns 1557897Shestness@cs.utexas.edu .name(name() + ".num_func_calls") 1567897Shestness@cs.utexas.edu .desc("number of times a function call or return occured") 1577897Shestness@cs.utexas.edu ; 1587897Shestness@cs.utexas.edu 1597897Shestness@cs.utexas.edu numCondCtrlInsts 1607897Shestness@cs.utexas.edu .name(name() + ".num_conditional_control_insts") 1617897Shestness@cs.utexas.edu .desc("number of instructions that are conditional controls") 1627897Shestness@cs.utexas.edu ; 1637897Shestness@cs.utexas.edu 1647897Shestness@cs.utexas.edu numIntInsts 1657897Shestness@cs.utexas.edu .name(name() + ".num_int_insts") 1667897Shestness@cs.utexas.edu .desc("number of integer instructions") 1677897Shestness@cs.utexas.edu ; 1687897Shestness@cs.utexas.edu 1697897Shestness@cs.utexas.edu numFpInsts 1707897Shestness@cs.utexas.edu .name(name() + ".num_fp_insts") 1717897Shestness@cs.utexas.edu .desc("number of float instructions") 1727897Shestness@cs.utexas.edu ; 1737897Shestness@cs.utexas.edu 1747897Shestness@cs.utexas.edu numIntRegReads 1757897Shestness@cs.utexas.edu .name(name() + ".num_int_register_reads") 1767897Shestness@cs.utexas.edu .desc("number of times the integer registers were read") 1777897Shestness@cs.utexas.edu ; 1787897Shestness@cs.utexas.edu 1797897Shestness@cs.utexas.edu numIntRegWrites 1807897Shestness@cs.utexas.edu .name(name() + ".num_int_register_writes") 1817897Shestness@cs.utexas.edu .desc("number of times the integer registers were written") 1827897Shestness@cs.utexas.edu ; 1837897Shestness@cs.utexas.edu 1847897Shestness@cs.utexas.edu numFpRegReads 1857897Shestness@cs.utexas.edu .name(name() + ".num_fp_register_reads") 1867897Shestness@cs.utexas.edu .desc("number of times the floating registers were read") 1877897Shestness@cs.utexas.edu ; 1887897Shestness@cs.utexas.edu 1897897Shestness@cs.utexas.edu numFpRegWrites 1907897Shestness@cs.utexas.edu .name(name() + ".num_fp_register_writes") 1917897Shestness@cs.utexas.edu .desc("number of times the floating registers were written") 1927897Shestness@cs.utexas.edu ; 1937897Shestness@cs.utexas.edu 1942SN/A numMemRefs 1957897Shestness@cs.utexas.edu .name(name()+".num_mem_refs") 1967897Shestness@cs.utexas.edu .desc("number of memory refs") 1977897Shestness@cs.utexas.edu ; 1987897Shestness@cs.utexas.edu 1997897Shestness@cs.utexas.edu numStoreInsts 2007897Shestness@cs.utexas.edu .name(name() + ".num_store_insts") 2017897Shestness@cs.utexas.edu .desc("Number of store instructions") 2027897Shestness@cs.utexas.edu ; 2037897Shestness@cs.utexas.edu 2047897Shestness@cs.utexas.edu numLoadInsts 2057897Shestness@cs.utexas.edu .name(name() + ".num_load_insts") 2067897Shestness@cs.utexas.edu .desc("Number of load instructions") 2072SN/A ; 2082SN/A 2091001SN/A notIdleFraction 2101001SN/A .name(name() + ".not_idle_fraction") 2111001SN/A .desc("Percentage of non-idle cycles") 2121001SN/A ; 2131001SN/A 2142SN/A idleFraction 2152SN/A .name(name() + ".idle_fraction") 2162SN/A .desc("Percentage of idle cycles") 2172SN/A ; 2182SN/A 2197897Shestness@cs.utexas.edu numBusyCycles 2207897Shestness@cs.utexas.edu .name(name() + ".num_busy_cycles") 2217897Shestness@cs.utexas.edu .desc("Number of busy cycles") 2227897Shestness@cs.utexas.edu ; 2237897Shestness@cs.utexas.edu 2247897Shestness@cs.utexas.edu numIdleCycles 2257897Shestness@cs.utexas.edu .name(name()+".num_idle_cycles") 2267897Shestness@cs.utexas.edu .desc("Number of idle cycles") 2277897Shestness@cs.utexas.edu ; 2287897Shestness@cs.utexas.edu 2292SN/A icacheStallCycles 2302SN/A .name(name() + ".icache_stall_cycles") 2312SN/A .desc("ICache total stall cycles") 2322SN/A .prereq(icacheStallCycles) 2332SN/A ; 2342SN/A 2352SN/A dcacheStallCycles 2362SN/A .name(name() + ".dcache_stall_cycles") 2372SN/A .desc("DCache total stall cycles") 2382SN/A .prereq(dcacheStallCycles) 2392SN/A ; 2402SN/A 2412390SN/A icacheRetryCycles 2422390SN/A .name(name() + ".icache_retry_cycles") 2432390SN/A .desc("ICache total retry cycles") 2442390SN/A .prereq(icacheRetryCycles) 2452390SN/A ; 2462390SN/A 2472390SN/A dcacheRetryCycles 2482390SN/A .name(name() + ".dcache_retry_cycles") 2492390SN/A .desc("DCache total retry cycles") 2502390SN/A .prereq(dcacheRetryCycles) 2512390SN/A ; 2522390SN/A 253385SN/A idleFraction = constant(1.0) - notIdleFraction; 2547897Shestness@cs.utexas.edu numIdleCycles = idleFraction * numCycles; 2557897Shestness@cs.utexas.edu numBusyCycles = (notIdleFraction)*numCycles; 2562SN/A} 2572SN/A 2582SN/Avoid 2592623SN/ABaseSimpleCPU::resetStats() 260334SN/A{ 2612361SN/A// startNumInst = numInst; 2625496Ssaidi@eecs.umich.edu notIdleFraction = (_status != Idle); 263334SN/A} 264334SN/A 265334SN/Avoid 2662623SN/ABaseSimpleCPU::serialize(ostream &os) 2672SN/A{ 2685496Ssaidi@eecs.umich.edu SERIALIZE_ENUM(_status); 269921SN/A BaseCPU::serialize(os); 2702915Sktlim@umich.edu// SERIALIZE_SCALAR(inst); 2712915Sktlim@umich.edu nameOut(os, csprintf("%s.xc.0", name())); 2722683Sktlim@umich.edu thread->serialize(os); 2732SN/A} 2742SN/A 2752SN/Avoid 2762623SN/ABaseSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 2772SN/A{ 2785496Ssaidi@eecs.umich.edu UNSERIALIZE_ENUM(_status); 279921SN/A BaseCPU::unserialize(cp, section); 2802915Sktlim@umich.edu// UNSERIALIZE_SCALAR(inst); 2812915Sktlim@umich.edu thread->unserialize(cp, csprintf("%s.xc.0", section)); 2822SN/A} 2832SN/A 2842SN/Avoid 2856221Snate@binkert.orgchange_thread_state(ThreadID tid, int activate, int priority) 2862SN/A{ 2872SN/A} 2882SN/A 2892SN/AAddr 2902623SN/ABaseSimpleCPU::dbg_vtophys(Addr addr) 2912SN/A{ 2922680Sktlim@umich.edu return vtophys(tc, addr); 2932SN/A} 2942SN/A 2952SN/Avoid 2965807Snate@binkert.orgBaseSimpleCPU::wakeup() 2972SN/A{ 2985807Snate@binkert.org if (thread->status() != ThreadContext::Suspended) 2995807Snate@binkert.org return; 3002SN/A 3015807Snate@binkert.org DPRINTF(Quiesce,"Suspended Processor awoke\n"); 3025807Snate@binkert.org thread->activate(); 3032SN/A} 3042SN/A 3052SN/Avoid 3062623SN/ABaseSimpleCPU::checkForInterrupts() 3072SN/A{ 3085704Snate@binkert.org if (checkInterrupts(tc)) { 3095647Sgblack@eecs.umich.edu Fault interrupt = interrupts->getInterrupt(tc); 3102SN/A 3113520Sgblack@eecs.umich.edu if (interrupt != NoFault) { 3127338SAli.Saidi@ARM.com fetchOffset = 0; 3135647Sgblack@eecs.umich.edu interrupts->updateIntrInfo(tc); 3143520Sgblack@eecs.umich.edu interrupt->invoke(tc); 3157408Sgblack@eecs.umich.edu predecoder.reset(); 3162SN/A } 3172SN/A } 3182623SN/A} 3192SN/A 3202623SN/A 3215894Sgblack@eecs.umich.eduvoid 3222662Sstever@eecs.umich.eduBaseSimpleCPU::setupFetchRequest(Request *req) 3232623SN/A{ 3247720Sgblack@eecs.umich.edu Addr instAddr = thread->instAddr(); 3254495Sacolyte@umich.edu 3262623SN/A // set up memory request for instruction fetch 3277720Sgblack@eecs.umich.edu DPRINTF(Fetch, "Fetch: PC:%08p\n", instAddr); 3282623SN/A 3297720Sgblack@eecs.umich.edu Addr fetchPC = (instAddr & PCMask) + fetchOffset; 3307720Sgblack@eecs.umich.edu req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instAddr); 3312623SN/A} 3322623SN/A 3332623SN/A 3342623SN/Avoid 3352623SN/ABaseSimpleCPU::preExecute() 3362623SN/A{ 3372SN/A // maintain $r0 semantics 3382683Sktlim@umich.edu thread->setIntReg(ZeroReg, 0); 3392427SN/A#if THE_ISA == ALPHA_ISA 3402683Sktlim@umich.edu thread->setFloatReg(ZeroReg, 0.0); 3412427SN/A#endif // ALPHA_ISA 3422SN/A 3432623SN/A // check for instruction-count-based events 3442623SN/A comInstEventQueue[0]->serviceEvents(numInst); 3457897Shestness@cs.utexas.edu system->instEventQueue.serviceEvents(system->totalNumInsts); 3462SN/A 3472623SN/A // decode the instruction 3482623SN/A inst = gtoh(inst); 3494377Sgblack@eecs.umich.edu 3507720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 3514377Sgblack@eecs.umich.edu 3527720Sgblack@eecs.umich.edu if (isRomMicroPC(pcState.microPC())) { 3535665Sgblack@eecs.umich.edu stayAtPC = false; 3547720Sgblack@eecs.umich.edu curStaticInst = microcodeRom.fetchMicroop(pcState.microPC(), 3557720Sgblack@eecs.umich.edu curMacroStaticInst); 3565665Sgblack@eecs.umich.edu } else if (!curMacroStaticInst) { 3575665Sgblack@eecs.umich.edu //We're not in the middle of a macro instruction 3584181Sgblack@eecs.umich.edu StaticInstPtr instPtr = NULL; 3594181Sgblack@eecs.umich.edu 3604181Sgblack@eecs.umich.edu //Predecode, ie bundle up an ExtMachInst 3614182Sgblack@eecs.umich.edu //This should go away once the constructor can be set up properly 3624182Sgblack@eecs.umich.edu predecoder.setTC(thread->getTC()); 3634182Sgblack@eecs.umich.edu //If more fetch data is needed, pass it in. 3647720Sgblack@eecs.umich.edu Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset; 3654593Sgblack@eecs.umich.edu //if(predecoder.needMoreBytes()) 3667720Sgblack@eecs.umich.edu predecoder.moreBytes(pcState, fetchPC, inst); 3674593Sgblack@eecs.umich.edu //else 3684593Sgblack@eecs.umich.edu // predecoder.process(); 3694377Sgblack@eecs.umich.edu 3704377Sgblack@eecs.umich.edu //If an instruction is ready, decode it. Otherwise, we'll have to 3714377Sgblack@eecs.umich.edu //fetch beyond the MachInst at the current pc. 3724377Sgblack@eecs.umich.edu if (predecoder.extMachInstReady()) { 3734377Sgblack@eecs.umich.edu stayAtPC = false; 3747720Sgblack@eecs.umich.edu ExtMachInst machInst = predecoder.getExtMachInst(pcState); 3757720Sgblack@eecs.umich.edu thread->pcState(pcState); 3768541Sgblack@eecs.umich.edu instPtr = thread->decoder.decode(machInst, pcState.instAddr()); 3774377Sgblack@eecs.umich.edu } else { 3784377Sgblack@eecs.umich.edu stayAtPC = true; 3794377Sgblack@eecs.umich.edu fetchOffset += sizeof(MachInst); 3804377Sgblack@eecs.umich.edu } 3814181Sgblack@eecs.umich.edu 3824181Sgblack@eecs.umich.edu //If we decoded an instruction and it's microcoded, start pulling 3834181Sgblack@eecs.umich.edu //out micro ops 3844539Sgblack@eecs.umich.edu if (instPtr && instPtr->isMacroop()) { 3853276Sgblack@eecs.umich.edu curMacroStaticInst = instPtr; 3867720Sgblack@eecs.umich.edu curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC()); 3873280Sgblack@eecs.umich.edu } else { 3883280Sgblack@eecs.umich.edu curStaticInst = instPtr; 3893276Sgblack@eecs.umich.edu } 3903276Sgblack@eecs.umich.edu } else { 3913276Sgblack@eecs.umich.edu //Read the next micro op from the macro op 3927720Sgblack@eecs.umich.edu curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC()); 3933276Sgblack@eecs.umich.edu } 3943276Sgblack@eecs.umich.edu 3954181Sgblack@eecs.umich.edu //If we decoded an instruction this "tick", record information about it. 3964181Sgblack@eecs.umich.edu if(curStaticInst) 3974181Sgblack@eecs.umich.edu { 3984522Ssaidi@eecs.umich.edu#if TRACING_ON 3997823Ssteve.reinhardt@amd.com traceData = tracer->getInstRecord(curTick(), tc, 4007720Sgblack@eecs.umich.edu curStaticInst, thread->pcState(), curMacroStaticInst); 4012470SN/A 4024181Sgblack@eecs.umich.edu DPRINTF(Decode,"Decode: Decoded %s instruction: 0x%x\n", 4034181Sgblack@eecs.umich.edu curStaticInst->getName(), curStaticInst->machInst); 4044522Ssaidi@eecs.umich.edu#endif // TRACING_ON 4054181Sgblack@eecs.umich.edu } 4062623SN/A} 4072623SN/A 4082623SN/Avoid 4092623SN/ABaseSimpleCPU::postExecute() 4102623SN/A{ 4117720Sgblack@eecs.umich.edu assert(curStaticInst); 4127720Sgblack@eecs.umich.edu 4137720Sgblack@eecs.umich.edu TheISA::PCState pc = tc->pcState(); 4147720Sgblack@eecs.umich.edu Addr instAddr = pc.instAddr(); 4158780Sgblack@eecs.umich.edu if (FullSystem && thread->profile) { 4163577Sgblack@eecs.umich.edu bool usermode = TheISA::inUserMode(tc); 4177720Sgblack@eecs.umich.edu thread->profilePC = usermode ? 1 : instAddr; 4185086Sgblack@eecs.umich.edu ProfileNode *node = thread->profile->consume(tc, curStaticInst); 4192623SN/A if (node) 4202683Sktlim@umich.edu thread->profileNode = node; 4212623SN/A } 4222SN/A 4232623SN/A if (curStaticInst->isMemRef()) { 4242623SN/A numMemRefs++; 4252SN/A } 4262SN/A 4272623SN/A if (curStaticInst->isLoad()) { 4282623SN/A ++numLoad; 4292623SN/A comLoadEventQueue[0]->serviceEvents(numLoad); 4302623SN/A } 4312SN/A 4325953Ssaidi@eecs.umich.edu if (CPA::available()) { 4337720Sgblack@eecs.umich.edu CPA::cpa()->swAutoBegin(tc, pc.nextInstAddr()); 4345953Ssaidi@eecs.umich.edu } 4355953Ssaidi@eecs.umich.edu 4367897Shestness@cs.utexas.edu /* Power model statistics */ 4377897Shestness@cs.utexas.edu //integer alu accesses 4387897Shestness@cs.utexas.edu if (curStaticInst->isInteger()){ 4397897Shestness@cs.utexas.edu numIntAluAccesses++; 4407897Shestness@cs.utexas.edu numIntInsts++; 4417897Shestness@cs.utexas.edu } 4427897Shestness@cs.utexas.edu 4437897Shestness@cs.utexas.edu //float alu accesses 4447897Shestness@cs.utexas.edu if (curStaticInst->isFloating()){ 4457897Shestness@cs.utexas.edu numFpAluAccesses++; 4467897Shestness@cs.utexas.edu numFpInsts++; 4477897Shestness@cs.utexas.edu } 4487897Shestness@cs.utexas.edu 4497897Shestness@cs.utexas.edu //number of function calls/returns to get window accesses 4507897Shestness@cs.utexas.edu if (curStaticInst->isCall() || curStaticInst->isReturn()){ 4517897Shestness@cs.utexas.edu numCallsReturns++; 4527897Shestness@cs.utexas.edu } 4537897Shestness@cs.utexas.edu 4547897Shestness@cs.utexas.edu //the number of branch predictions that will be made 4557897Shestness@cs.utexas.edu if (curStaticInst->isCondCtrl()){ 4567897Shestness@cs.utexas.edu numCondCtrlInsts++; 4577897Shestness@cs.utexas.edu } 4587897Shestness@cs.utexas.edu 4597897Shestness@cs.utexas.edu //result bus acceses 4607897Shestness@cs.utexas.edu if (curStaticInst->isLoad()){ 4617897Shestness@cs.utexas.edu numLoadInsts++; 4627897Shestness@cs.utexas.edu } 4637897Shestness@cs.utexas.edu 4647897Shestness@cs.utexas.edu if (curStaticInst->isStore()){ 4657897Shestness@cs.utexas.edu numStoreInsts++; 4667897Shestness@cs.utexas.edu } 4677897Shestness@cs.utexas.edu /* End power model statistics */ 4687897Shestness@cs.utexas.edu 4698780Sgblack@eecs.umich.edu if (FullSystem) 4708780Sgblack@eecs.umich.edu traceFunctions(instAddr); 4712644Sstever@eecs.umich.edu 4722644Sstever@eecs.umich.edu if (traceData) { 4734046Sbinkertn@umich.edu traceData->dump(); 4744046Sbinkertn@umich.edu delete traceData; 4754046Sbinkertn@umich.edu traceData = NULL; 4762644Sstever@eecs.umich.edu } 4772623SN/A} 4782SN/A 4792SN/A 4802623SN/Avoid 4812623SN/ABaseSimpleCPU::advancePC(Fault fault) 4822623SN/A{ 4834377Sgblack@eecs.umich.edu //Since we're moving to a new pc, zero out the offset 4844377Sgblack@eecs.umich.edu fetchOffset = 0; 4852090SN/A if (fault != NoFault) { 4863905Ssaidi@eecs.umich.edu curMacroStaticInst = StaticInst::nullStaticInstPtr; 4877678Sgblack@eecs.umich.edu fault->invoke(tc, curStaticInst); 4885120Sgblack@eecs.umich.edu predecoder.reset(); 4894377Sgblack@eecs.umich.edu } else { 4907720Sgblack@eecs.umich.edu if (curStaticInst) { 4917720Sgblack@eecs.umich.edu if (curStaticInst->isLastMicroop()) 4927720Sgblack@eecs.umich.edu curMacroStaticInst = StaticInst::nullStaticInstPtr; 4937720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 4947720Sgblack@eecs.umich.edu TheISA::advancePC(pcState, curStaticInst); 4957720Sgblack@eecs.umich.edu thread->pcState(pcState); 4963276Sgblack@eecs.umich.edu } 4972SN/A } 4982SN/A} 4992SN/A 5005250Sksewell@umich.edu/*Fault 5015222Sksewell@umich.eduBaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr) 5025222Sksewell@umich.edu{ 5035222Sksewell@umich.edu // translate to physical address 5045222Sksewell@umich.edu Fault fault = NoFault; 5055222Sksewell@umich.edu int CacheID = Op & 0x3; // Lower 3 bits identify Cache 5065222Sksewell@umich.edu int CacheOP = Op >> 2; // Upper 3 bits identify Cache Operation 5075222Sksewell@umich.edu if(CacheID > 1) 5085222Sksewell@umich.edu { 5095222Sksewell@umich.edu warn("CacheOps not implemented for secondary/tertiary caches\n"); 5105222Sksewell@umich.edu } 5115222Sksewell@umich.edu else 5125222Sksewell@umich.edu { 5135222Sksewell@umich.edu switch(CacheOP) 5145222Sksewell@umich.edu { // Fill Packet Type 5155222Sksewell@umich.edu case 0: warn("Invalidate Cache Op\n"); 5165222Sksewell@umich.edu break; 5175222Sksewell@umich.edu case 1: warn("Index Load Tag Cache Op\n"); 5185222Sksewell@umich.edu break; 5195222Sksewell@umich.edu case 2: warn("Index Store Tag Cache Op\n"); 5205222Sksewell@umich.edu break; 5215222Sksewell@umich.edu case 4: warn("Hit Invalidate Cache Op\n"); 5225222Sksewell@umich.edu break; 5235222Sksewell@umich.edu case 5: warn("Fill/Hit Writeback Invalidate Cache Op\n"); 5245222Sksewell@umich.edu break; 5255222Sksewell@umich.edu case 6: warn("Hit Writeback\n"); 5265222Sksewell@umich.edu break; 5275222Sksewell@umich.edu case 7: warn("Fetch & Lock Cache Op\n"); 5285222Sksewell@umich.edu break; 5295222Sksewell@umich.edu default: warn("Unimplemented Cache Op\n"); 5305222Sksewell@umich.edu } 5315222Sksewell@umich.edu } 5325222Sksewell@umich.edu return fault; 5335250Sksewell@umich.edu}*/ 534