base.cc revision 7823
12SN/A/* 27338SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37338SAli.Saidi@ARM.com * All rights reserved 47338SAli.Saidi@ARM.com * 57338SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67338SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77338SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87338SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97338SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107338SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117338SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127338SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137338SAli.Saidi@ARM.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152SN/A * All rights reserved. 162SN/A * 172SN/A * Redistribution and use in source and binary forms, with or without 182SN/A * modification, are permitted provided that the following conditions are 192SN/A * met: redistributions of source code must retain the above copyright 202SN/A * notice, this list of conditions and the following disclaimer; 212SN/A * redistributions in binary form must reproduce the above copyright 222SN/A * notice, this list of conditions and the following disclaimer in the 232SN/A * documentation and/or other materials provided with the distribution; 242SN/A * neither the name of the copyright holders nor the names of its 252SN/A * contributors may be used to endorse or promote products derived from 262SN/A * this software without specific prior written permission. 272SN/A * 282SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 412SN/A */ 422SN/A 436216Snate@binkert.org#include "arch/faults.hh" 442439SN/A#include "arch/utility.hh" 456216Snate@binkert.org#include "base/cp_annotate.hh" 46146SN/A#include "base/cprintf.hh" 47146SN/A#include "base/inifile.hh" 48146SN/A#include "base/loader/symtab.hh" 49146SN/A#include "base/misc.hh" 50146SN/A#include "base/pollevent.hh" 51146SN/A#include "base/range.hh" 52146SN/A#include "base/trace.hh" 536216Snate@binkert.org#include "base/types.hh" 546658Snate@binkert.org#include "config/the_isa.hh" 551717SN/A#include "cpu/base.hh" 56146SN/A#include "cpu/exetrace.hh" 571977SN/A#include "cpu/profile.hh" 582623SN/A#include "cpu/simple/base.hh" 592683Sktlim@umich.edu#include "cpu/simple_thread.hh" 601717SN/A#include "cpu/smt.hh" 61146SN/A#include "cpu/static_inst.hh" 622683Sktlim@umich.edu#include "cpu/thread_context.hh" 633348Sbinkertn@umich.edu#include "mem/packet.hh" 646105Ssteve.reinhardt@amd.com#include "mem/request.hh" 656216Snate@binkert.org#include "params/BaseSimpleCPU.hh" 662036SN/A#include "sim/byteswap.hh" 67146SN/A#include "sim/debug.hh" 6856SN/A#include "sim/sim_events.hh" 6956SN/A#include "sim/sim_object.hh" 70695SN/A#include "sim/stats.hh" 712901Ssaidi@eecs.umich.edu#include "sim/system.hh" 722SN/A 731858SN/A#if FULL_SYSTEM 743565Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 753565Sgblack@eecs.umich.edu#include "arch/stacktrace.hh" 762171SN/A#include "arch/tlb.hh" 772170SN/A#include "arch/vtophys.hh" 78146SN/A#else // !FULL_SYSTEM 792462SN/A#include "mem/mem_object.hh" 80146SN/A#endif // FULL_SYSTEM 812SN/A 822SN/Ausing namespace std; 832449SN/Ausing namespace TheISA; 841355SN/A 855529Snate@binkert.orgBaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p) 864495Sacolyte@umich.edu : BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL) 87224SN/A{ 881858SN/A#if FULL_SYSTEM 892683Sktlim@umich.edu thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb); 902420SN/A#else 915529Snate@binkert.org thread = new SimpleThread(this, /* thread_num */ 0, p->workload[0], 926331Sgblack@eecs.umich.edu p->itb, p->dtb); 932420SN/A#endif // !FULL_SYSTEM 942SN/A 956029Ssteve.reinhardt@amd.com thread->setStatus(ThreadContext::Halted); 962672Sktlim@umich.edu 972683Sktlim@umich.edu tc = thread->getTC(); 982SN/A 992SN/A numInst = 0; 100334SN/A startNumInst = 0; 101140SN/A numLoad = 0; 102334SN/A startNumLoad = 0; 1032SN/A lastIcacheStall = 0; 1042SN/A lastDcacheStall = 0; 1052SN/A 1062680Sktlim@umich.edu threadContexts.push_back(tc); 1074377Sgblack@eecs.umich.edu 1085169Ssaidi@eecs.umich.edu 1094377Sgblack@eecs.umich.edu fetchOffset = 0; 1104377Sgblack@eecs.umich.edu stayAtPC = false; 1112SN/A} 1122SN/A 1132623SN/ABaseSimpleCPU::~BaseSimpleCPU() 1142SN/A{ 1152SN/A} 1162SN/A 117180SN/Avoid 1182623SN/ABaseSimpleCPU::deallocateContext(int thread_num) 119393SN/A{ 120393SN/A // for now, these are equivalent 121393SN/A suspendContext(thread_num); 122393SN/A} 123384SN/A 124384SN/A 125393SN/Avoid 1262623SN/ABaseSimpleCPU::haltContext(int thread_num) 127393SN/A{ 128393SN/A // for now, these are equivalent 129393SN/A suspendContext(thread_num); 130393SN/A} 131384SN/A 132189SN/A 133189SN/Avoid 1342623SN/ABaseSimpleCPU::regStats() 1352SN/A{ 136729SN/A using namespace Stats; 137334SN/A 1382SN/A BaseCPU::regStats(); 1392SN/A 1402SN/A numInsts 1412SN/A .name(name() + ".num_insts") 1422SN/A .desc("Number of instructions executed") 1432SN/A ; 1442SN/A 1452SN/A numMemRefs 1462SN/A .name(name() + ".num_refs") 1472SN/A .desc("Number of memory references") 1482SN/A ; 1492SN/A 1501001SN/A notIdleFraction 1511001SN/A .name(name() + ".not_idle_fraction") 1521001SN/A .desc("Percentage of non-idle cycles") 1531001SN/A ; 1541001SN/A 1552SN/A idleFraction 1562SN/A .name(name() + ".idle_fraction") 1572SN/A .desc("Percentage of idle cycles") 1582SN/A ; 1592SN/A 1602SN/A icacheStallCycles 1612SN/A .name(name() + ".icache_stall_cycles") 1622SN/A .desc("ICache total stall cycles") 1632SN/A .prereq(icacheStallCycles) 1642SN/A ; 1652SN/A 1662SN/A dcacheStallCycles 1672SN/A .name(name() + ".dcache_stall_cycles") 1682SN/A .desc("DCache total stall cycles") 1692SN/A .prereq(dcacheStallCycles) 1702SN/A ; 1712SN/A 1722390SN/A icacheRetryCycles 1732390SN/A .name(name() + ".icache_retry_cycles") 1742390SN/A .desc("ICache total retry cycles") 1752390SN/A .prereq(icacheRetryCycles) 1762390SN/A ; 1772390SN/A 1782390SN/A dcacheRetryCycles 1792390SN/A .name(name() + ".dcache_retry_cycles") 1802390SN/A .desc("DCache total retry cycles") 1812390SN/A .prereq(dcacheRetryCycles) 1822390SN/A ; 1832390SN/A 184385SN/A idleFraction = constant(1.0) - notIdleFraction; 1852SN/A} 1862SN/A 1872SN/Avoid 1882623SN/ABaseSimpleCPU::resetStats() 189334SN/A{ 1902361SN/A// startNumInst = numInst; 1915496Ssaidi@eecs.umich.edu notIdleFraction = (_status != Idle); 192334SN/A} 193334SN/A 194334SN/Avoid 1952623SN/ABaseSimpleCPU::serialize(ostream &os) 1962SN/A{ 1975496Ssaidi@eecs.umich.edu SERIALIZE_ENUM(_status); 198921SN/A BaseCPU::serialize(os); 1992915Sktlim@umich.edu// SERIALIZE_SCALAR(inst); 2002915Sktlim@umich.edu nameOut(os, csprintf("%s.xc.0", name())); 2012683Sktlim@umich.edu thread->serialize(os); 2022SN/A} 2032SN/A 2042SN/Avoid 2052623SN/ABaseSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 2062SN/A{ 2075496Ssaidi@eecs.umich.edu UNSERIALIZE_ENUM(_status); 208921SN/A BaseCPU::unserialize(cp, section); 2092915Sktlim@umich.edu// UNSERIALIZE_SCALAR(inst); 2102915Sktlim@umich.edu thread->unserialize(cp, csprintf("%s.xc.0", section)); 2112SN/A} 2122SN/A 2132SN/Avoid 2146221Snate@binkert.orgchange_thread_state(ThreadID tid, int activate, int priority) 2152SN/A{ 2162SN/A} 2172SN/A 2181858SN/A#if FULL_SYSTEM 2192SN/AAddr 2202623SN/ABaseSimpleCPU::dbg_vtophys(Addr addr) 2212SN/A{ 2222680Sktlim@umich.edu return vtophys(tc, addr); 2232SN/A} 2242SN/A#endif // FULL_SYSTEM 2252SN/A 2261858SN/A#if FULL_SYSTEM 2272SN/Avoid 2285807Snate@binkert.orgBaseSimpleCPU::wakeup() 2292SN/A{ 2305807Snate@binkert.org if (thread->status() != ThreadContext::Suspended) 2315807Snate@binkert.org return; 2322SN/A 2335807Snate@binkert.org DPRINTF(Quiesce,"Suspended Processor awoke\n"); 2345807Snate@binkert.org thread->activate(); 2352SN/A} 2362SN/A#endif // FULL_SYSTEM 2372SN/A 2382SN/Avoid 2392623SN/ABaseSimpleCPU::checkForInterrupts() 2402SN/A{ 2411858SN/A#if FULL_SYSTEM 2425704Snate@binkert.org if (checkInterrupts(tc)) { 2435647Sgblack@eecs.umich.edu Fault interrupt = interrupts->getInterrupt(tc); 2442SN/A 2453520Sgblack@eecs.umich.edu if (interrupt != NoFault) { 2467338SAli.Saidi@ARM.com fetchOffset = 0; 2475647Sgblack@eecs.umich.edu interrupts->updateIntrInfo(tc); 2483520Sgblack@eecs.umich.edu interrupt->invoke(tc); 2497408Sgblack@eecs.umich.edu predecoder.reset(); 2502SN/A } 2512SN/A } 2522SN/A#endif 2532623SN/A} 2542SN/A 2552623SN/A 2565894Sgblack@eecs.umich.eduvoid 2572662Sstever@eecs.umich.eduBaseSimpleCPU::setupFetchRequest(Request *req) 2582623SN/A{ 2597720Sgblack@eecs.umich.edu Addr instAddr = thread->instAddr(); 2604495Sacolyte@umich.edu 2612623SN/A // set up memory request for instruction fetch 2627720Sgblack@eecs.umich.edu DPRINTF(Fetch, "Fetch: PC:%08p\n", instAddr); 2632623SN/A 2647720Sgblack@eecs.umich.edu Addr fetchPC = (instAddr & PCMask) + fetchOffset; 2657720Sgblack@eecs.umich.edu req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instAddr); 2662623SN/A} 2672623SN/A 2682623SN/A 2692623SN/Avoid 2702623SN/ABaseSimpleCPU::preExecute() 2712623SN/A{ 2722SN/A // maintain $r0 semantics 2732683Sktlim@umich.edu thread->setIntReg(ZeroReg, 0); 2742427SN/A#if THE_ISA == ALPHA_ISA 2752683Sktlim@umich.edu thread->setFloatReg(ZeroReg, 0.0); 2762427SN/A#endif // ALPHA_ISA 2772SN/A 2782623SN/A // check for instruction-count-based events 2792623SN/A comInstEventQueue[0]->serviceEvents(numInst); 2802SN/A 2812623SN/A // decode the instruction 2822623SN/A inst = gtoh(inst); 2834377Sgblack@eecs.umich.edu 2847720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 2854377Sgblack@eecs.umich.edu 2867720Sgblack@eecs.umich.edu if (isRomMicroPC(pcState.microPC())) { 2875665Sgblack@eecs.umich.edu stayAtPC = false; 2887720Sgblack@eecs.umich.edu curStaticInst = microcodeRom.fetchMicroop(pcState.microPC(), 2897720Sgblack@eecs.umich.edu curMacroStaticInst); 2905665Sgblack@eecs.umich.edu } else if (!curMacroStaticInst) { 2915665Sgblack@eecs.umich.edu //We're not in the middle of a macro instruction 2924181Sgblack@eecs.umich.edu StaticInstPtr instPtr = NULL; 2934181Sgblack@eecs.umich.edu 2944181Sgblack@eecs.umich.edu //Predecode, ie bundle up an ExtMachInst 2954182Sgblack@eecs.umich.edu //This should go away once the constructor can be set up properly 2964182Sgblack@eecs.umich.edu predecoder.setTC(thread->getTC()); 2974182Sgblack@eecs.umich.edu //If more fetch data is needed, pass it in. 2987720Sgblack@eecs.umich.edu Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset; 2994593Sgblack@eecs.umich.edu //if(predecoder.needMoreBytes()) 3007720Sgblack@eecs.umich.edu predecoder.moreBytes(pcState, fetchPC, inst); 3014593Sgblack@eecs.umich.edu //else 3024593Sgblack@eecs.umich.edu // predecoder.process(); 3034377Sgblack@eecs.umich.edu 3044377Sgblack@eecs.umich.edu //If an instruction is ready, decode it. Otherwise, we'll have to 3054377Sgblack@eecs.umich.edu //fetch beyond the MachInst at the current pc. 3064377Sgblack@eecs.umich.edu if (predecoder.extMachInstReady()) { 3074377Sgblack@eecs.umich.edu stayAtPC = false; 3087720Sgblack@eecs.umich.edu ExtMachInst machInst = predecoder.getExtMachInst(pcState); 3097720Sgblack@eecs.umich.edu thread->pcState(pcState); 3107720Sgblack@eecs.umich.edu instPtr = StaticInst::decode(machInst, pcState.instAddr()); 3114377Sgblack@eecs.umich.edu } else { 3124377Sgblack@eecs.umich.edu stayAtPC = true; 3134377Sgblack@eecs.umich.edu fetchOffset += sizeof(MachInst); 3144377Sgblack@eecs.umich.edu } 3154181Sgblack@eecs.umich.edu 3164181Sgblack@eecs.umich.edu //If we decoded an instruction and it's microcoded, start pulling 3174181Sgblack@eecs.umich.edu //out micro ops 3184539Sgblack@eecs.umich.edu if (instPtr && instPtr->isMacroop()) { 3193276Sgblack@eecs.umich.edu curMacroStaticInst = instPtr; 3207720Sgblack@eecs.umich.edu curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC()); 3213280Sgblack@eecs.umich.edu } else { 3223280Sgblack@eecs.umich.edu curStaticInst = instPtr; 3233276Sgblack@eecs.umich.edu } 3243276Sgblack@eecs.umich.edu } else { 3253276Sgblack@eecs.umich.edu //Read the next micro op from the macro op 3267720Sgblack@eecs.umich.edu curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC()); 3273276Sgblack@eecs.umich.edu } 3283276Sgblack@eecs.umich.edu 3294181Sgblack@eecs.umich.edu //If we decoded an instruction this "tick", record information about it. 3304181Sgblack@eecs.umich.edu if(curStaticInst) 3314181Sgblack@eecs.umich.edu { 3324522Ssaidi@eecs.umich.edu#if TRACING_ON 3337823Ssteve.reinhardt@amd.com traceData = tracer->getInstRecord(curTick(), tc, 3347720Sgblack@eecs.umich.edu curStaticInst, thread->pcState(), curMacroStaticInst); 3352470SN/A 3364181Sgblack@eecs.umich.edu DPRINTF(Decode,"Decode: Decoded %s instruction: 0x%x\n", 3374181Sgblack@eecs.umich.edu curStaticInst->getName(), curStaticInst->machInst); 3384522Ssaidi@eecs.umich.edu#endif // TRACING_ON 3394181Sgblack@eecs.umich.edu } 3402623SN/A} 3412623SN/A 3422623SN/Avoid 3432623SN/ABaseSimpleCPU::postExecute() 3442623SN/A{ 3457720Sgblack@eecs.umich.edu assert(curStaticInst); 3467720Sgblack@eecs.umich.edu 3477720Sgblack@eecs.umich.edu TheISA::PCState pc = tc->pcState(); 3487720Sgblack@eecs.umich.edu Addr instAddr = pc.instAddr(); 3492623SN/A#if FULL_SYSTEM 3507720Sgblack@eecs.umich.edu if (thread->profile) { 3513577Sgblack@eecs.umich.edu bool usermode = TheISA::inUserMode(tc); 3527720Sgblack@eecs.umich.edu thread->profilePC = usermode ? 1 : instAddr; 3535086Sgblack@eecs.umich.edu ProfileNode *node = thread->profile->consume(tc, curStaticInst); 3542623SN/A if (node) 3552683Sktlim@umich.edu thread->profileNode = node; 3562623SN/A } 3572420SN/A#endif 3582SN/A 3592623SN/A if (curStaticInst->isMemRef()) { 3602623SN/A numMemRefs++; 3612SN/A } 3622SN/A 3632623SN/A if (curStaticInst->isLoad()) { 3642623SN/A ++numLoad; 3652623SN/A comLoadEventQueue[0]->serviceEvents(numLoad); 3662623SN/A } 3672SN/A 3685953Ssaidi@eecs.umich.edu if (CPA::available()) { 3697720Sgblack@eecs.umich.edu CPA::cpa()->swAutoBegin(tc, pc.nextInstAddr()); 3705953Ssaidi@eecs.umich.edu } 3715953Ssaidi@eecs.umich.edu 3727720Sgblack@eecs.umich.edu traceFunctions(instAddr); 3732644Sstever@eecs.umich.edu 3742644Sstever@eecs.umich.edu if (traceData) { 3754046Sbinkertn@umich.edu traceData->dump(); 3764046Sbinkertn@umich.edu delete traceData; 3774046Sbinkertn@umich.edu traceData = NULL; 3782644Sstever@eecs.umich.edu } 3792623SN/A} 3802SN/A 3812SN/A 3822623SN/Avoid 3832623SN/ABaseSimpleCPU::advancePC(Fault fault) 3842623SN/A{ 3854377Sgblack@eecs.umich.edu //Since we're moving to a new pc, zero out the offset 3864377Sgblack@eecs.umich.edu fetchOffset = 0; 3872090SN/A if (fault != NoFault) { 3883905Ssaidi@eecs.umich.edu curMacroStaticInst = StaticInst::nullStaticInstPtr; 3897678Sgblack@eecs.umich.edu fault->invoke(tc, curStaticInst); 3905120Sgblack@eecs.umich.edu predecoder.reset(); 3914377Sgblack@eecs.umich.edu } else { 3927720Sgblack@eecs.umich.edu if (curStaticInst) { 3937720Sgblack@eecs.umich.edu if (curStaticInst->isLastMicroop()) 3947720Sgblack@eecs.umich.edu curMacroStaticInst = StaticInst::nullStaticInstPtr; 3957720Sgblack@eecs.umich.edu TheISA::PCState pcState = thread->pcState(); 3967720Sgblack@eecs.umich.edu TheISA::advancePC(pcState, curStaticInst); 3977720Sgblack@eecs.umich.edu thread->pcState(pcState); 3983276Sgblack@eecs.umich.edu } 3992SN/A } 4002SN/A} 4012SN/A 4025250Sksewell@umich.edu/*Fault 4035222Sksewell@umich.eduBaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr) 4045222Sksewell@umich.edu{ 4055222Sksewell@umich.edu // translate to physical address 4065222Sksewell@umich.edu Fault fault = NoFault; 4075222Sksewell@umich.edu int CacheID = Op & 0x3; // Lower 3 bits identify Cache 4085222Sksewell@umich.edu int CacheOP = Op >> 2; // Upper 3 bits identify Cache Operation 4095222Sksewell@umich.edu if(CacheID > 1) 4105222Sksewell@umich.edu { 4115222Sksewell@umich.edu warn("CacheOps not implemented for secondary/tertiary caches\n"); 4125222Sksewell@umich.edu } 4135222Sksewell@umich.edu else 4145222Sksewell@umich.edu { 4155222Sksewell@umich.edu switch(CacheOP) 4165222Sksewell@umich.edu { // Fill Packet Type 4175222Sksewell@umich.edu case 0: warn("Invalidate Cache Op\n"); 4185222Sksewell@umich.edu break; 4195222Sksewell@umich.edu case 1: warn("Index Load Tag Cache Op\n"); 4205222Sksewell@umich.edu break; 4215222Sksewell@umich.edu case 2: warn("Index Store Tag Cache Op\n"); 4225222Sksewell@umich.edu break; 4235222Sksewell@umich.edu case 4: warn("Hit Invalidate Cache Op\n"); 4245222Sksewell@umich.edu break; 4255222Sksewell@umich.edu case 5: warn("Fill/Hit Writeback Invalidate Cache Op\n"); 4265222Sksewell@umich.edu break; 4275222Sksewell@umich.edu case 6: warn("Hit Writeback\n"); 4285222Sksewell@umich.edu break; 4295222Sksewell@umich.edu case 7: warn("Fetch & Lock Cache Op\n"); 4305222Sksewell@umich.edu break; 4315222Sksewell@umich.edu default: warn("Unimplemented Cache Op\n"); 4325222Sksewell@umich.edu } 4335222Sksewell@umich.edu } 4345222Sksewell@umich.edu return fault; 4355250Sksewell@umich.edu}*/ 436