base.cc revision 707 
1/*
2 * Copyright (c) 2003 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <cmath>
30#include <cstdio>
31#include <cstdlib>
32#include <iostream>
33#include <iomanip>
34#include <list>
35#include <sstream>
36#include <string>
37
38#include "base/cprintf.hh"
39#include "base/inifile.hh"
40#include "base/loader/symtab.hh"
41#include "base/misc.hh"
42#include "base/pollevent.hh"
43#include "base/range.hh"
44#include "base/trace.hh"
45#include "cpu/base_cpu.hh"
46#include "cpu/exec_context.hh"
47#include "cpu/exetrace.hh"
48#include "cpu/full_cpu/smt.hh"
49#include "cpu/simple_cpu/simple_cpu.hh"
50#include "cpu/static_inst.hh"
51#include "mem/base_mem.hh"
52#include "mem/mem_interface.hh"
53#include "sim/annotation.hh"
54#include "sim/builder.hh"
55#include "sim/debug.hh"
56#include "sim/host.hh"
57#include "sim/sim_events.hh"
58#include "sim/sim_object.hh"
59#include "sim/stats.hh"
60
61#ifdef FULL_SYSTEM
62#include "base/remote_gdb.hh"
63#include "dev/alpha_access.h"
64#include "dev/pciareg.h"
65#include "mem/functional_mem/memory_control.hh"
66#include "mem/functional_mem/physical_memory.hh"
67#include "sim/system.hh"
68#include "targetarch/alpha_memory.hh"
69#include "targetarch/vtophys.hh"
70#else // !FULL_SYSTEM
71#include "eio/eio.hh"
72#include "mem/functional_mem/functional_memory.hh"
73#endif // FULL_SYSTEM
74
75using namespace std;
76
77SimpleCPU::TickEvent::TickEvent(SimpleCPU *c)
78    : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
79{
80}
81
82void
83SimpleCPU::TickEvent::process()
84{
85    cpu->tick();
86}
87
88const char *
89SimpleCPU::TickEvent::description()
90{
91    return "SimpleCPU tick event";
92}
93
94
95SimpleCPU::CacheCompletionEvent::CacheCompletionEvent(SimpleCPU *_cpu)
96    : Event(&mainEventQueue),
97      cpu(_cpu)
98{
99}
100
101void SimpleCPU::CacheCompletionEvent::process()
102{
103    cpu->processCacheCompletion();
104}
105
106const char *
107SimpleCPU::CacheCompletionEvent::description()
108{
109    return "SimpleCPU cache completion event";
110}
111
112#ifdef FULL_SYSTEM
113SimpleCPU::SimpleCPU(const string &_name,
114                     System *_system,
115                     Counter max_insts_any_thread,
116                     Counter max_insts_all_threads,
117                     Counter max_loads_any_thread,
118                     Counter max_loads_all_threads,
119                     AlphaITB *itb, AlphaDTB *dtb,
120                     FunctionalMemory *mem,
121                     MemInterface *icache_interface,
122                     MemInterface *dcache_interface,
123                     bool _def_reg, Tick freq)
124    : BaseCPU(_name, /* number_of_threads */ 1,
125              max_insts_any_thread, max_insts_all_threads,
126              max_loads_any_thread, max_loads_all_threads,
127              _system, freq),
128#else
129SimpleCPU::SimpleCPU(const string &_name, Process *_process,
130                     Counter max_insts_any_thread,
131                     Counter max_insts_all_threads,
132                     Counter max_loads_any_thread,
133                     Counter max_loads_all_threads,
134                     MemInterface *icache_interface,
135                     MemInterface *dcache_interface,
136                     bool _def_reg)
137    : BaseCPU(_name, /* number_of_threads */ 1,
138              max_insts_any_thread, max_insts_all_threads,
139              max_loads_any_thread, max_loads_all_threads),
140#endif
141      tickEvent(this), xc(NULL), defer_registration(_def_reg),
142      cacheCompletionEvent(this)
143{
144    _status = Idle;
145#ifdef FULL_SYSTEM
146    xc = new ExecContext(this, 0, system, itb, dtb, mem);
147
148    // initialize CPU, including PC
149    TheISA::initCPU(&xc->regs);
150#else
151    xc = new ExecContext(this, /* thread_num */ 0, _process, /* asid */ 0);
152#endif // !FULL_SYSTEM
153
154    icacheInterface = icache_interface;
155    dcacheInterface = dcache_interface;
156
157    memReq = new MemReq();
158    memReq->xc = xc;
159    memReq->asid = 0;
160    memReq->data = new uint8_t[64];
161
162    numInst = 0;
163    startNumInst = 0;
164    numLoad = 0;
165    startNumLoad = 0;
166    lastIcacheStall = 0;
167    lastDcacheStall = 0;
168
169    execContexts.push_back(xc);
170}
171
172SimpleCPU::~SimpleCPU()
173{
174}
175
176void SimpleCPU::init()
177{
178    if (!defer_registration) {
179        this->registerExecContexts();
180    }
181}
182
183void
184SimpleCPU::switchOut()
185{
186    _status = SwitchedOut;
187    if (tickEvent.scheduled())
188        tickEvent.squash();
189}
190
191
192void
193SimpleCPU::takeOverFrom(BaseCPU *oldCPU)
194{
195    BaseCPU::takeOverFrom(oldCPU);
196
197    assert(!tickEvent.scheduled());
198
199    // if any of this CPU's ExecContexts are active, mark the CPU as
200    // running and schedule its tick event.
201    for (int i = 0; i < execContexts.size(); ++i) {
202        ExecContext *xc = execContexts[i];
203        if (xc->status() == ExecContext::Active && _status != Running) {
204            _status = Running;
205            tickEvent.schedule(curTick);
206        }
207    }
208
209    oldCPU->switchOut();
210}
211
212
213void
214SimpleCPU::activateContext(int thread_num, int delay)
215{
216    assert(thread_num == 0);
217    assert(xc);
218
219    assert(_status == Idle);
220    notIdleFraction++;
221    scheduleTickEvent(delay);
222    _status = Running;
223}
224
225
226void
227SimpleCPU::suspendContext(int thread_num)
228{
229    assert(thread_num == 0);
230    assert(xc);
231
232    assert(_status == Running);
233    notIdleFraction--;
234    unscheduleTickEvent();
235    _status = Idle;
236}
237
238
239void
240SimpleCPU::deallocateContext(int thread_num)
241{
242    // for now, these are equivalent
243    suspendContext(thread_num);
244}
245
246
247void
248SimpleCPU::haltContext(int thread_num)
249{
250    // for now, these are equivalent
251    suspendContext(thread_num);
252}
253
254
255void
256SimpleCPU::regStats()
257{
258    using namespace Statistics;
259
260    BaseCPU::regStats();
261
262    numInsts
263        .name(name() + ".num_insts")
264        .desc("Number of instructions executed")
265        ;
266
267    numMemRefs
268        .name(name() + ".num_refs")
269        .desc("Number of memory references")
270        ;
271
272    idleFraction
273        .name(name() + ".idle_fraction")
274        .desc("Percentage of idle cycles")
275        ;
276
277    icacheStallCycles
278        .name(name() + ".icache_stall_cycles")
279        .desc("ICache total stall cycles")
280        .prereq(icacheStallCycles)
281        ;
282
283    dcacheStallCycles
284        .name(name() + ".dcache_stall_cycles")
285        .desc("DCache total stall cycles")
286        .prereq(dcacheStallCycles)
287        ;
288
289    idleFraction = constant(1.0) - notIdleFraction;
290}
291
292void
293SimpleCPU::resetStats()
294{
295    startNumInst = numInst;
296    notIdleFraction = (_status != Idle);
297}
298
299void
300SimpleCPU::serialize(ostream &os)
301{
302    SERIALIZE_ENUM(_status);
303    SERIALIZE_SCALAR(inst);
304    nameOut(os, csprintf("%s.xc", name()));
305    xc->serialize(os);
306    nameOut(os, csprintf("%s.tickEvent", name()));
307    tickEvent.serialize(os);
308    nameOut(os, csprintf("%s.cacheCompletionEvent", name()));
309    cacheCompletionEvent.serialize(os);
310}
311
312void
313SimpleCPU::unserialize(Checkpoint *cp, const string &section)
314{
315    UNSERIALIZE_ENUM(_status);
316    UNSERIALIZE_SCALAR(inst);
317    xc->unserialize(cp, csprintf("%s.xc", section));
318    tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
319    cacheCompletionEvent
320        .unserialize(cp, csprintf("%s.cacheCompletionEvent", section));
321}
322
323void
324change_thread_state(int thread_number, int activate, int priority)
325{
326}
327
328Fault
329SimpleCPU::copySrcTranslate(Addr src)
330{
331    memReq->reset(src, (dcacheInterface) ?
332                  dcacheInterface->getBlockSize()
333                  : 64);
334
335    // translate to physical address
336    Fault fault = xc->translateDataReadReq(memReq);
337
338    if (fault == No_Fault) {
339        xc->copySrcAddr = src;
340        xc->copySrcPhysAddr = memReq->paddr;
341    } else {
342        xc->copySrcAddr = 0;
343        xc->copySrcPhysAddr = 0;
344    }
345    return fault;
346}
347
348Fault
349SimpleCPU::copy(Addr dest)
350{
351    int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
352    uint8_t data[blk_size];
353    assert(xc->copySrcPhysAddr);
354    memReq->reset(dest, blk_size);
355    // translate to physical address
356    Fault fault = xc->translateDataWriteReq(memReq);
357    if (fault == No_Fault) {
358        Addr dest_addr = memReq->paddr;
359        // Need to read straight from memory since we have more than 8 bytes.
360        memReq->paddr = xc->copySrcPhysAddr;
361        xc->mem->read(memReq, data);
362        memReq->paddr = dest_addr;
363        xc->mem->write(memReq, data);
364    }
365    return fault;
366}
367
368// precise architected memory state accessor macros
369template <class T>
370Fault
371SimpleCPU::read(Addr addr, T &data, unsigned flags)
372{
373    memReq->reset(addr, sizeof(T), flags);
374
375    // translate to physical address
376    Fault fault = xc->translateDataReadReq(memReq);
377
378    // do functional access
379    if (fault == No_Fault)
380        fault = xc->read(memReq, data);
381
382    if (traceData) {
383        traceData->setAddr(addr);
384        if (fault == No_Fault)
385            traceData->setData(data);
386    }
387
388    // if we have a cache, do cache access too
389    if (fault == No_Fault && dcacheInterface) {
390        memReq->cmd = Read;
391        memReq->completionEvent = NULL;
392        memReq->time = curTick;
393        MemAccessResult result = dcacheInterface->access(memReq);
394
395        // Ugly hack to get an event scheduled *only* if the access is
396        // a miss.  We really should add first-class support for this
397        // at some point.
398        if (result != MA_HIT && dcacheInterface->doEvents()) {
399            memReq->completionEvent = &cacheCompletionEvent;
400            lastDcacheStall = curTick;
401            unscheduleTickEvent();
402            _status = DcacheMissStall;
403        }
404    }
405
406    return fault;
407}
408
409#ifndef DOXYGEN_SHOULD_SKIP_THIS
410
411template
412Fault
413SimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
414
415template
416Fault
417SimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
418
419template
420Fault
421SimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
422
423template
424Fault
425SimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
426
427#endif //DOXYGEN_SHOULD_SKIP_THIS
428
429template<>
430Fault
431SimpleCPU::read(Addr addr, double &data, unsigned flags)
432{
433    return read(addr, *(uint64_t*)&data, flags);
434}
435
436template<>
437Fault
438SimpleCPU::read(Addr addr, float &data, unsigned flags)
439{
440    return read(addr, *(uint32_t*)&data, flags);
441}
442
443
444template<>
445Fault
446SimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
447{
448    return read(addr, (uint32_t&)data, flags);
449}
450
451
452template <class T>
453Fault
454SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
455{
456    if (traceData) {
457        traceData->setAddr(addr);
458        traceData->setData(data);
459    }
460
461    memReq->reset(addr, sizeof(T), flags);
462
463    // translate to physical address
464    Fault fault = xc->translateDataWriteReq(memReq);
465
466    // do functional access
467    if (fault == No_Fault)
468        fault = xc->write(memReq, data);
469
470    if (fault == No_Fault && dcacheInterface) {
471        memReq->cmd = Write;
472        memcpy(memReq->data,(uint8_t *)&data,memReq->size);
473        memReq->completionEvent = NULL;
474        memReq->time = curTick;
475        MemAccessResult result = dcacheInterface->access(memReq);
476
477        // Ugly hack to get an event scheduled *only* if the access is
478        // a miss.  We really should add first-class support for this
479        // at some point.
480        if (result != MA_HIT && dcacheInterface->doEvents()) {
481            memReq->completionEvent = &cacheCompletionEvent;
482            lastDcacheStall = curTick;
483            unscheduleTickEvent();
484            _status = DcacheMissStall;
485        }
486    }
487
488    if (res && (fault == No_Fault))
489        *res = memReq->result;
490
491    return fault;
492}
493
494
495#ifndef DOXYGEN_SHOULD_SKIP_THIS
496template
497Fault
498SimpleCPU::write(uint64_t data, Addr addr, unsigned flags, uint64_t *res);
499
500template
501Fault
502SimpleCPU::write(uint32_t data, Addr addr, unsigned flags, uint64_t *res);
503
504template
505Fault
506SimpleCPU::write(uint16_t data, Addr addr, unsigned flags, uint64_t *res);
507
508template
509Fault
510SimpleCPU::write(uint8_t data, Addr addr, unsigned flags, uint64_t *res);
511
512#endif //DOXYGEN_SHOULD_SKIP_THIS
513
514template<>
515Fault
516SimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
517{
518    return write(*(uint64_t*)&data, addr, flags, res);
519}
520
521template<>
522Fault
523SimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
524{
525    return write(*(uint32_t*)&data, addr, flags, res);
526}
527
528
529template<>
530Fault
531SimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
532{
533    return write((uint32_t)data, addr, flags, res);
534}
535
536
537#ifdef FULL_SYSTEM
538Addr
539SimpleCPU::dbg_vtophys(Addr addr)
540{
541    return vtophys(xc, addr);
542}
543#endif // FULL_SYSTEM
544
545Tick save_cycle = 0;
546
547
548void
549SimpleCPU::processCacheCompletion()
550{
551    switch (status()) {
552      case IcacheMissStall:
553        icacheStallCycles += curTick - lastIcacheStall;
554        _status = IcacheMissComplete;
555        scheduleTickEvent(1);
556        break;
557      case DcacheMissStall:
558        dcacheStallCycles += curTick - lastDcacheStall;
559        _status = Running;
560        scheduleTickEvent(1);
561        break;
562      case SwitchedOut:
563        // If this CPU has been switched out due to sampling/warm-up,
564        // ignore any further status changes (e.g., due to cache
565        // misses outstanding at the time of the switch).
566        return;
567      default:
568        panic("SimpleCPU::processCacheCompletion: bad state");
569        break;
570    }
571}
572
573#ifdef FULL_SYSTEM
574void
575SimpleCPU::post_interrupt(int int_num, int index)
576{
577    BaseCPU::post_interrupt(int_num, index);
578
579    if (xc->status() == ExecContext::Suspended) {
580                DPRINTF(IPI,"Suspended Processor awoke\n");
581        xc->activate();
582        Annotate::Resume(xc);
583    }
584}
585#endif // FULL_SYSTEM
586
587/* start simulation, program loaded, processor precise state initialized */
588void
589SimpleCPU::tick()
590{
591    numCycles++;
592
593    traceData = NULL;
594
595    Fault fault = No_Fault;
596
597#ifdef FULL_SYSTEM
598    if (AlphaISA::check_interrupts &&
599        xc->cpu->check_interrupts() &&
600        !PC_PAL(xc->regs.pc) &&
601        status() != IcacheMissComplete) {
602        int ipl = 0;
603        int summary = 0;
604        AlphaISA::check_interrupts = 0;
605        IntReg *ipr = xc->regs.ipr;
606
607        if (xc->regs.ipr[TheISA::IPR_SIRR]) {
608            for (int i = TheISA::INTLEVEL_SOFTWARE_MIN;
609                 i < TheISA::INTLEVEL_SOFTWARE_MAX; i++) {
610                if (ipr[TheISA::IPR_SIRR] & (ULL(1) << i)) {
611                    // See table 4-19 of 21164 hardware reference
612                    ipl = (i - TheISA::INTLEVEL_SOFTWARE_MIN) + 1;
613                    summary |= (ULL(1) << i);
614                }
615            }
616        }
617
618        uint64_t interrupts = xc->cpu->intr_status();
619        for (int i = TheISA::INTLEVEL_EXTERNAL_MIN;
620            i < TheISA::INTLEVEL_EXTERNAL_MAX; i++) {
621            if (interrupts & (ULL(1) << i)) {
622                // See table 4-19 of 21164 hardware reference
623                ipl = i;
624                summary |= (ULL(1) << i);
625            }
626        }
627
628        if (ipr[TheISA::IPR_ASTRR])
629            panic("asynchronous traps not implemented\n");
630
631        if (ipl && ipl > xc->regs.ipr[TheISA::IPR_IPLR]) {
632            ipr[TheISA::IPR_ISR] = summary;
633            ipr[TheISA::IPR_INTID] = ipl;
634            xc->ev5_trap(Interrupt_Fault);
635
636            DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
637                    ipr[TheISA::IPR_IPLR], ipl, summary);
638        }
639    }
640#endif
641
642    // maintain $r0 semantics
643    xc->regs.intRegFile[ZeroReg] = 0;
644#ifdef TARGET_ALPHA
645    xc->regs.floatRegFile.d[ZeroReg] = 0.0;
646#endif // TARGET_ALPHA
647
648    if (status() == IcacheMissComplete) {
649        // We've already fetched an instruction and were stalled on an
650        // I-cache miss.  No need to fetch it again.
651
652        // Set status to running; tick event will get rescheduled if
653        // necessary at end of tick() function.
654        _status = Running;
655    }
656    else {
657        // Try to fetch an instruction
658
659        // set up memory request for instruction fetch
660#ifdef FULL_SYSTEM
661#define IFETCH_FLAGS(pc)	((pc) & 1) ? PHYSICAL : 0
662#else
663#define IFETCH_FLAGS(pc)	0
664#endif
665
666        memReq->cmd = Read;
667        memReq->reset(xc->regs.pc & ~3, sizeof(uint32_t),
668                     IFETCH_FLAGS(xc->regs.pc));
669
670        fault = xc->translateInstReq(memReq);
671
672        if (fault == No_Fault)
673            fault = xc->mem->read(memReq, inst);
674
675        if (icacheInterface && fault == No_Fault) {
676            memReq->completionEvent = NULL;
677
678            memReq->time = curTick;
679            MemAccessResult result = icacheInterface->access(memReq);
680
681            // Ugly hack to get an event scheduled *only* if the access is
682            // a miss.  We really should add first-class support for this
683            // at some point.
684            if (result != MA_HIT && icacheInterface->doEvents()) {
685                memReq->completionEvent = &cacheCompletionEvent;
686                lastIcacheStall = curTick;
687                unscheduleTickEvent();
688                _status = IcacheMissStall;
689                return;
690            }
691        }
692    }
693
694    // If we've got a valid instruction (i.e., no fault on instruction
695    // fetch), then execute it.
696    if (fault == No_Fault) {
697
698        // keep an instruction count
699        numInst++;
700        numInsts++;
701
702        // check for instruction-count-based events
703        comInstEventQueue[0]->serviceEvents(numInst);
704
705        // decode the instruction
706        StaticInstPtr<TheISA> si(inst);
707
708        traceData = Trace::getInstRecord(curTick, xc, this, si,
709                                         xc->regs.pc);
710
711#ifdef FULL_SYSTEM
712        xc->regs.opcode = (inst >> 26) & 0x3f;
713        xc->regs.ra = (inst >> 21) & 0x1f;
714#endif // FULL_SYSTEM
715
716        xc->func_exe_inst++;
717
718        fault = si->execute(this, traceData);
719
720#ifdef FULL_SYSTEM
721        SWContext *ctx = xc->swCtx;
722        if (ctx)
723            ctx->process(xc, si.get());
724#endif
725
726        if (si->isMemRef()) {
727            numMemRefs++;
728        }
729
730        if (si->isLoad()) {
731            ++numLoad;
732            comLoadEventQueue[0]->serviceEvents(numLoad);
733        }
734
735        if (traceData)
736            traceData->finalize();
737
738    }	// if (fault == No_Fault)
739
740    if (fault != No_Fault) {
741#ifdef FULL_SYSTEM
742        xc->ev5_trap(fault);
743#else // !FULL_SYSTEM
744        fatal("fault (%d) detected @ PC 0x%08p", fault, xc->regs.pc);
745#endif // FULL_SYSTEM
746    }
747    else {
748        // go to the next instruction
749        xc->regs.pc = xc->regs.npc;
750        xc->regs.npc += sizeof(MachInst);
751    }
752
753#ifdef FULL_SYSTEM
754    Addr oldpc;
755    do {
756        oldpc = xc->regs.pc;
757        system->pcEventQueue.service(xc);
758    } while (oldpc != xc->regs.pc);
759#endif
760
761    assert(status() == Running ||
762           status() == Idle ||
763           status() == DcacheMissStall);
764
765    if (status() == Running && !tickEvent.scheduled())
766        tickEvent.schedule(curTick + 1);
767}
768
769
770////////////////////////////////////////////////////////////////////////
771//
772//  SimpleCPU Simulation Object
773//
774BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
775
776    Param<Counter> max_insts_any_thread;
777    Param<Counter> max_insts_all_threads;
778    Param<Counter> max_loads_any_thread;
779    Param<Counter> max_loads_all_threads;
780
781#ifdef FULL_SYSTEM
782    SimObjectParam<AlphaITB *> itb;
783    SimObjectParam<AlphaDTB *> dtb;
784    SimObjectParam<FunctionalMemory *> mem;
785    SimObjectParam<System *> system;
786    Param<int> mult;
787#else
788    SimObjectParam<Process *> workload;
789#endif // FULL_SYSTEM
790
791    SimObjectParam<BaseMem *> icache;
792    SimObjectParam<BaseMem *> dcache;
793
794    Param<bool> defer_registration;
795
796END_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
797
798BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
799
800    INIT_PARAM_DFLT(max_insts_any_thread,
801                    "terminate when any thread reaches this inst count",
802                    0),
803    INIT_PARAM_DFLT(max_insts_all_threads,
804                    "terminate when all threads have reached this inst count",
805                    0),
806    INIT_PARAM_DFLT(max_loads_any_thread,
807                    "terminate when any thread reaches this load count",
808                    0),
809    INIT_PARAM_DFLT(max_loads_all_threads,
810                    "terminate when all threads have reached this load count",
811                    0),
812
813#ifdef FULL_SYSTEM
814    INIT_PARAM(itb, "Instruction TLB"),
815    INIT_PARAM(dtb, "Data TLB"),
816    INIT_PARAM(mem, "memory"),
817    INIT_PARAM(system, "system object"),
818    INIT_PARAM_DFLT(mult, "system clock multiplier", 1),
819#else
820    INIT_PARAM(workload, "processes to run"),
821#endif // FULL_SYSTEM
822
823    INIT_PARAM_DFLT(icache, "L1 instruction cache object", NULL),
824    INIT_PARAM_DFLT(dcache, "L1 data cache object", NULL),
825    INIT_PARAM_DFLT(defer_registration, "defer registration with system "
826                    "(for sampling)", false)
827
828END_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
829
830
831CREATE_SIM_OBJECT(SimpleCPU)
832{
833    SimpleCPU *cpu;
834#ifdef FULL_SYSTEM
835    if (mult != 1)
836        panic("processor clock multiplier must be 1\n");
837
838    cpu = new SimpleCPU(getInstanceName(), system,
839                        max_insts_any_thread, max_insts_all_threads,
840                        max_loads_any_thread, max_loads_all_threads,
841                        itb, dtb, mem,
842                        (icache) ? icache->getInterface() : NULL,
843                        (dcache) ? dcache->getInterface() : NULL,
844                        defer_registration,
845                        ticksPerSecond * mult);
846#else
847
848    cpu = new SimpleCPU(getInstanceName(), workload,
849                        max_insts_any_thread, max_insts_all_threads,
850                        max_loads_any_thread, max_loads_all_threads,
851                        (icache) ? icache->getInterface() : NULL,
852                        (dcache) ? dcache->getInterface() : NULL,
853                        defer_registration);
854
855#endif // FULL_SYSTEM
856
857    return cpu;
858}
859
860REGISTER_SIM_OBJECT("SimpleCPU", SimpleCPU)
861
862