base.cc revision 5281
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292SN/A */ 302SN/A 312439SN/A#include "arch/utility.hh" 322984Sgblack@eecs.umich.edu#include "arch/faults.hh" 33146SN/A#include "base/cprintf.hh" 34146SN/A#include "base/inifile.hh" 35146SN/A#include "base/loader/symtab.hh" 36146SN/A#include "base/misc.hh" 37146SN/A#include "base/pollevent.hh" 38146SN/A#include "base/range.hh" 391717SN/A#include "base/stats/events.hh" 40146SN/A#include "base/trace.hh" 411717SN/A#include "cpu/base.hh" 42146SN/A#include "cpu/exetrace.hh" 431977SN/A#include "cpu/profile.hh" 442623SN/A#include "cpu/simple/base.hh" 452683Sktlim@umich.edu#include "cpu/simple_thread.hh" 461717SN/A#include "cpu/smt.hh" 47146SN/A#include "cpu/static_inst.hh" 482683Sktlim@umich.edu#include "cpu/thread_context.hh" 493348Sbinkertn@umich.edu#include "mem/packet.hh" 502036SN/A#include "sim/byteswap.hh" 51146SN/A#include "sim/debug.hh" 5256SN/A#include "sim/host.hh" 5356SN/A#include "sim/sim_events.hh" 5456SN/A#include "sim/sim_object.hh" 55695SN/A#include "sim/stats.hh" 562901Ssaidi@eecs.umich.edu#include "sim/system.hh" 572SN/A 581858SN/A#if FULL_SYSTEM 593565Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 603565Sgblack@eecs.umich.edu#include "arch/stacktrace.hh" 612171SN/A#include "arch/tlb.hh" 622170SN/A#include "arch/vtophys.hh" 633562Sgblack@eecs.umich.edu#include "base/remote_gdb.hh" 64146SN/A#else // !FULL_SYSTEM 652462SN/A#include "mem/mem_object.hh" 66146SN/A#endif // FULL_SYSTEM 672SN/A 682SN/Ausing namespace std; 692449SN/Ausing namespace TheISA; 701355SN/A 712623SN/ABaseSimpleCPU::BaseSimpleCPU(Params *p) 724495Sacolyte@umich.edu : BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL) 73224SN/A{ 741858SN/A#if FULL_SYSTEM 752683Sktlim@umich.edu thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb); 762420SN/A#else 772683Sktlim@umich.edu thread = new SimpleThread(this, /* thread_num */ 0, p->process, 784997Sgblack@eecs.umich.edu p->itb, p->dtb, /* asid */ 0); 792420SN/A#endif // !FULL_SYSTEM 802SN/A 814400Srdreslin@umich.edu thread->setStatus(ThreadContext::Unallocated); 822672Sktlim@umich.edu 832683Sktlim@umich.edu tc = thread->getTC(); 842SN/A 852SN/A numInst = 0; 86334SN/A startNumInst = 0; 87140SN/A numLoad = 0; 88334SN/A startNumLoad = 0; 892SN/A lastIcacheStall = 0; 902SN/A lastDcacheStall = 0; 912SN/A 922680Sktlim@umich.edu threadContexts.push_back(tc); 934377Sgblack@eecs.umich.edu 945169Ssaidi@eecs.umich.edu cpuId = tc->readCpuId(); 955169Ssaidi@eecs.umich.edu 964377Sgblack@eecs.umich.edu fetchOffset = 0; 974377Sgblack@eecs.umich.edu stayAtPC = false; 982SN/A} 992SN/A 1002623SN/ABaseSimpleCPU::~BaseSimpleCPU() 1012SN/A{ 1022SN/A} 1032SN/A 104180SN/Avoid 1052623SN/ABaseSimpleCPU::deallocateContext(int thread_num) 106393SN/A{ 107393SN/A // for now, these are equivalent 108393SN/A suspendContext(thread_num); 109393SN/A} 110384SN/A 111384SN/A 112393SN/Avoid 1132623SN/ABaseSimpleCPU::haltContext(int thread_num) 114393SN/A{ 115393SN/A // for now, these are equivalent 116393SN/A suspendContext(thread_num); 117393SN/A} 118384SN/A 119189SN/A 120189SN/Avoid 1212623SN/ABaseSimpleCPU::regStats() 1222SN/A{ 123729SN/A using namespace Stats; 124334SN/A 1252SN/A BaseCPU::regStats(); 1262SN/A 1272SN/A numInsts 1282SN/A .name(name() + ".num_insts") 1292SN/A .desc("Number of instructions executed") 1302SN/A ; 1312SN/A 1322SN/A numMemRefs 1332SN/A .name(name() + ".num_refs") 1342SN/A .desc("Number of memory references") 1352SN/A ; 1362SN/A 1371001SN/A notIdleFraction 1381001SN/A .name(name() + ".not_idle_fraction") 1391001SN/A .desc("Percentage of non-idle cycles") 1401001SN/A ; 1411001SN/A 1422SN/A idleFraction 1432SN/A .name(name() + ".idle_fraction") 1442SN/A .desc("Percentage of idle cycles") 1452SN/A ; 1462SN/A 1472SN/A icacheStallCycles 1482SN/A .name(name() + ".icache_stall_cycles") 1492SN/A .desc("ICache total stall cycles") 1502SN/A .prereq(icacheStallCycles) 1512SN/A ; 1522SN/A 1532SN/A dcacheStallCycles 1542SN/A .name(name() + ".dcache_stall_cycles") 1552SN/A .desc("DCache total stall cycles") 1562SN/A .prereq(dcacheStallCycles) 1572SN/A ; 1582SN/A 1592390SN/A icacheRetryCycles 1602390SN/A .name(name() + ".icache_retry_cycles") 1612390SN/A .desc("ICache total retry cycles") 1622390SN/A .prereq(icacheRetryCycles) 1632390SN/A ; 1642390SN/A 1652390SN/A dcacheRetryCycles 1662390SN/A .name(name() + ".dcache_retry_cycles") 1672390SN/A .desc("DCache total retry cycles") 1682390SN/A .prereq(dcacheRetryCycles) 1692390SN/A ; 1702390SN/A 171385SN/A idleFraction = constant(1.0) - notIdleFraction; 1722SN/A} 1732SN/A 1742SN/Avoid 1752623SN/ABaseSimpleCPU::resetStats() 176334SN/A{ 1772361SN/A// startNumInst = numInst; 1782623SN/A // notIdleFraction = (_status != Idle); 179334SN/A} 180334SN/A 181334SN/Avoid 1822623SN/ABaseSimpleCPU::serialize(ostream &os) 1832SN/A{ 184921SN/A BaseCPU::serialize(os); 1852915Sktlim@umich.edu// SERIALIZE_SCALAR(inst); 1862915Sktlim@umich.edu nameOut(os, csprintf("%s.xc.0", name())); 1872683Sktlim@umich.edu thread->serialize(os); 1882SN/A} 1892SN/A 1902SN/Avoid 1912623SN/ABaseSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 1922SN/A{ 193921SN/A BaseCPU::unserialize(cp, section); 1942915Sktlim@umich.edu// UNSERIALIZE_SCALAR(inst); 1952915Sktlim@umich.edu thread->unserialize(cp, csprintf("%s.xc.0", section)); 1962SN/A} 1972SN/A 1982SN/Avoid 1992SN/Achange_thread_state(int thread_number, int activate, int priority) 2002SN/A{ 2012SN/A} 2022SN/A 203595SN/AFault 2042623SN/ABaseSimpleCPU::copySrcTranslate(Addr src) 205595SN/A{ 2062390SN/A#if 0 2071080SN/A static bool no_warn = true; 2081080SN/A int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64; 2091080SN/A // Only support block sizes of 64 atm. 2101080SN/A assert(blk_size == 64); 2111080SN/A int offset = src & (blk_size - 1); 2121080SN/A 2131080SN/A // Make sure block doesn't span page 2141121SN/A if (no_warn && 2152107SN/A (src & PageMask) != ((src + blk_size) & PageMask) && 2161089SN/A (src >> 40) != 0xfffffc) { 2171089SN/A warn("Copied block source spans pages %x.", src); 2181080SN/A no_warn = false; 2191080SN/A } 2201080SN/A 2211080SN/A memReq->reset(src & ~(blk_size - 1), blk_size); 222595SN/A 2232623SN/A // translate to physical address 2242683Sktlim@umich.edu Fault fault = thread->translateDataReadReq(req); 225595SN/A 2262090SN/A if (fault == NoFault) { 2272683Sktlim@umich.edu thread->copySrcAddr = src; 2282683Sktlim@umich.edu thread->copySrcPhysAddr = memReq->paddr + offset; 229595SN/A } else { 2302205SN/A assert(!fault->isAlignmentFault()); 2312205SN/A 2322683Sktlim@umich.edu thread->copySrcAddr = 0; 2332683Sktlim@umich.edu thread->copySrcPhysAddr = 0; 234595SN/A } 235595SN/A return fault; 2362390SN/A#else 2372423SN/A return NoFault; 2382390SN/A#endif 239595SN/A} 240595SN/A 241595SN/AFault 2422623SN/ABaseSimpleCPU::copy(Addr dest) 243595SN/A{ 2442390SN/A#if 0 2451080SN/A static bool no_warn = true; 246595SN/A int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64; 2471080SN/A // Only support block sizes of 64 atm. 2481080SN/A assert(blk_size == 64); 249595SN/A uint8_t data[blk_size]; 2502683Sktlim@umich.edu //assert(thread->copySrcAddr); 2511080SN/A int offset = dest & (blk_size - 1); 2521080SN/A 2531080SN/A // Make sure block doesn't span page 2541121SN/A if (no_warn && 2552107SN/A (dest & PageMask) != ((dest + blk_size) & PageMask) && 2561089SN/A (dest >> 40) != 0xfffffc) { 2571080SN/A no_warn = false; 2581089SN/A warn("Copied block destination spans pages %x. ", dest); 2591080SN/A } 2601080SN/A 2611080SN/A memReq->reset(dest & ~(blk_size -1), blk_size); 262595SN/A // translate to physical address 2632683Sktlim@umich.edu Fault fault = thread->translateDataWriteReq(req); 2641080SN/A 2652090SN/A if (fault == NoFault) { 2661080SN/A Addr dest_addr = memReq->paddr + offset; 267595SN/A // Need to read straight from memory since we have more than 8 bytes. 2682683Sktlim@umich.edu memReq->paddr = thread->copySrcPhysAddr; 2692683Sktlim@umich.edu thread->mem->read(memReq, data); 270595SN/A memReq->paddr = dest_addr; 2712683Sktlim@umich.edu thread->mem->write(memReq, data); 2721098SN/A if (dcacheInterface) { 2731098SN/A memReq->cmd = Copy; 2741098SN/A memReq->completionEvent = NULL; 2752683Sktlim@umich.edu memReq->paddr = thread->copySrcPhysAddr; 2761098SN/A memReq->dest = dest_addr; 2771098SN/A memReq->size = 64; 2781098SN/A memReq->time = curTick; 2792012SN/A memReq->flags &= ~INST_READ; 2801098SN/A dcacheInterface->access(memReq); 2811098SN/A } 282595SN/A } 2832205SN/A else 2842205SN/A assert(!fault->isAlignmentFault()); 2852205SN/A 286595SN/A return fault; 2872390SN/A#else 2882420SN/A panic("copy not implemented"); 2892423SN/A return NoFault; 2902390SN/A#endif 291595SN/A} 292595SN/A 2931858SN/A#if FULL_SYSTEM 2942SN/AAddr 2952623SN/ABaseSimpleCPU::dbg_vtophys(Addr addr) 2962SN/A{ 2972680Sktlim@umich.edu return vtophys(tc, addr); 2982SN/A} 2992SN/A#endif // FULL_SYSTEM 3002SN/A 3011858SN/A#if FULL_SYSTEM 3022SN/Avoid 3032623SN/ABaseSimpleCPU::post_interrupt(int int_num, int index) 3042SN/A{ 3052SN/A BaseCPU::post_interrupt(int_num, index); 3062SN/A 3072683Sktlim@umich.edu if (thread->status() == ThreadContext::Suspended) { 3084216Ssaidi@eecs.umich.edu DPRINTF(Quiesce,"Suspended Processor awoke\n"); 3092683Sktlim@umich.edu thread->activate(); 3102SN/A } 3112SN/A} 3122SN/A#endif // FULL_SYSTEM 3132SN/A 3142SN/Avoid 3152623SN/ABaseSimpleCPU::checkForInterrupts() 3162SN/A{ 3171858SN/A#if FULL_SYSTEM 3183923Shsul@eecs.umich.edu if (check_interrupts(tc)) { 3193520Sgblack@eecs.umich.edu Fault interrupt = interrupts.getInterrupt(tc); 3202SN/A 3213520Sgblack@eecs.umich.edu if (interrupt != NoFault) { 3223633Sktlim@umich.edu interrupts.updateIntrInfo(tc); 3233520Sgblack@eecs.umich.edu interrupt->invoke(tc); 3242SN/A } 3252SN/A } 3262SN/A#endif 3272623SN/A} 3282SN/A 3292623SN/A 3302623SN/AFault 3312662Sstever@eecs.umich.eduBaseSimpleCPU::setupFetchRequest(Request *req) 3322623SN/A{ 3334514Ssaidi@eecs.umich.edu Addr threadPC = thread->readPC(); 3344495Sacolyte@umich.edu 3352623SN/A // set up memory request for instruction fetch 3363093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 3374495Sacolyte@umich.edu DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",threadPC, 3383093Sksewell@umich.edu thread->readNextPC(),thread->readNextNPC()); 3393093Sksewell@umich.edu#else 3404564Sgblack@eecs.umich.edu DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p\n",threadPC, 3412741Sksewell@umich.edu thread->readNextPC()); 3422741Sksewell@umich.edu#endif 3432623SN/A 3444564Sgblack@eecs.umich.edu Addr fetchPC = (threadPC & PCMask) + fetchOffset; 3454564Sgblack@eecs.umich.edu req->setVirt(0, fetchPC, sizeof(MachInst), 0, threadPC); 3462623SN/A 3472683Sktlim@umich.edu Fault fault = thread->translateInstReq(req); 3482623SN/A 3492623SN/A return fault; 3502623SN/A} 3512623SN/A 3522623SN/A 3532623SN/Avoid 3542623SN/ABaseSimpleCPU::preExecute() 3552623SN/A{ 3562SN/A // maintain $r0 semantics 3572683Sktlim@umich.edu thread->setIntReg(ZeroReg, 0); 3582427SN/A#if THE_ISA == ALPHA_ISA 3592683Sktlim@umich.edu thread->setFloatReg(ZeroReg, 0.0); 3602427SN/A#endif // ALPHA_ISA 3612SN/A 3622623SN/A // check for instruction-count-based events 3632623SN/A comInstEventQueue[0]->serviceEvents(numInst); 3642SN/A 3652623SN/A // decode the instruction 3662623SN/A inst = gtoh(inst); 3674377Sgblack@eecs.umich.edu 3683276Sgblack@eecs.umich.edu //If we're not in the middle of a macro instruction 3693276Sgblack@eecs.umich.edu if (!curMacroStaticInst) { 3704377Sgblack@eecs.umich.edu 3714181Sgblack@eecs.umich.edu StaticInstPtr instPtr = NULL; 3724181Sgblack@eecs.umich.edu 3734181Sgblack@eecs.umich.edu //Predecode, ie bundle up an ExtMachInst 3744182Sgblack@eecs.umich.edu //This should go away once the constructor can be set up properly 3754182Sgblack@eecs.umich.edu predecoder.setTC(thread->getTC()); 3764182Sgblack@eecs.umich.edu //If more fetch data is needed, pass it in. 3774593Sgblack@eecs.umich.edu Addr fetchPC = (thread->readPC() & PCMask) + fetchOffset; 3784593Sgblack@eecs.umich.edu //if(predecoder.needMoreBytes()) 3794593Sgblack@eecs.umich.edu predecoder.moreBytes(thread->readPC(), fetchPC, inst); 3804593Sgblack@eecs.umich.edu //else 3814593Sgblack@eecs.umich.edu // predecoder.process(); 3824377Sgblack@eecs.umich.edu 3834377Sgblack@eecs.umich.edu //If an instruction is ready, decode it. Otherwise, we'll have to 3844377Sgblack@eecs.umich.edu //fetch beyond the MachInst at the current pc. 3854377Sgblack@eecs.umich.edu if (predecoder.extMachInstReady()) { 3864377Sgblack@eecs.umich.edu#if THE_ISA == X86_ISA 3874377Sgblack@eecs.umich.edu thread->setNextPC(thread->readPC() + predecoder.getInstSize()); 3884377Sgblack@eecs.umich.edu#endif // X86_ISA 3894377Sgblack@eecs.umich.edu stayAtPC = false; 3904572Sacolyte@umich.edu instPtr = StaticInst::decode(predecoder.getExtMachInst(), 3914572Sacolyte@umich.edu thread->readPC()); 3924377Sgblack@eecs.umich.edu } else { 3934377Sgblack@eecs.umich.edu stayAtPC = true; 3944377Sgblack@eecs.umich.edu fetchOffset += sizeof(MachInst); 3954377Sgblack@eecs.umich.edu } 3964181Sgblack@eecs.umich.edu 3974181Sgblack@eecs.umich.edu //If we decoded an instruction and it's microcoded, start pulling 3984181Sgblack@eecs.umich.edu //out micro ops 3994539Sgblack@eecs.umich.edu if (instPtr && instPtr->isMacroop()) { 4003276Sgblack@eecs.umich.edu curMacroStaticInst = instPtr; 4013442Sgblack@eecs.umich.edu curStaticInst = curMacroStaticInst-> 4024539Sgblack@eecs.umich.edu fetchMicroop(thread->readMicroPC()); 4033280Sgblack@eecs.umich.edu } else { 4043280Sgblack@eecs.umich.edu curStaticInst = instPtr; 4053276Sgblack@eecs.umich.edu } 4063276Sgblack@eecs.umich.edu } else { 4073276Sgblack@eecs.umich.edu //Read the next micro op from the macro op 4083442Sgblack@eecs.umich.edu curStaticInst = curMacroStaticInst-> 4094539Sgblack@eecs.umich.edu fetchMicroop(thread->readMicroPC()); 4103276Sgblack@eecs.umich.edu } 4113276Sgblack@eecs.umich.edu 4124181Sgblack@eecs.umich.edu //If we decoded an instruction this "tick", record information about it. 4134181Sgblack@eecs.umich.edu if(curStaticInst) 4144181Sgblack@eecs.umich.edu { 4154522Ssaidi@eecs.umich.edu#if TRACING_ON 4164776Sgblack@eecs.umich.edu traceData = tracer->getInstRecord(curTick, tc, curStaticInst, 4174181Sgblack@eecs.umich.edu thread->readPC()); 4182470SN/A 4194181Sgblack@eecs.umich.edu DPRINTF(Decode,"Decode: Decoded %s instruction: 0x%x\n", 4204181Sgblack@eecs.umich.edu curStaticInst->getName(), curStaticInst->machInst); 4214522Ssaidi@eecs.umich.edu#endif // TRACING_ON 4222623SN/A 4232623SN/A#if FULL_SYSTEM 4244181Sgblack@eecs.umich.edu thread->setInst(inst); 4252623SN/A#endif // FULL_SYSTEM 4264181Sgblack@eecs.umich.edu } 4272623SN/A} 4282623SN/A 4292623SN/Avoid 4302623SN/ABaseSimpleCPU::postExecute() 4312623SN/A{ 4322623SN/A#if FULL_SYSTEM 4335086Sgblack@eecs.umich.edu if (thread->profile && curStaticInst) { 4343577Sgblack@eecs.umich.edu bool usermode = TheISA::inUserMode(tc); 4352683Sktlim@umich.edu thread->profilePC = usermode ? 1 : thread->readPC(); 4365086Sgblack@eecs.umich.edu ProfileNode *node = thread->profile->consume(tc, curStaticInst); 4372623SN/A if (node) 4382683Sktlim@umich.edu thread->profileNode = node; 4392623SN/A } 4402420SN/A#endif 4412SN/A 4422623SN/A if (curStaticInst->isMemRef()) { 4432623SN/A numMemRefs++; 4442SN/A } 4452SN/A 4462623SN/A if (curStaticInst->isLoad()) { 4472623SN/A ++numLoad; 4482623SN/A comLoadEventQueue[0]->serviceEvents(numLoad); 4492623SN/A } 4502SN/A 4512683Sktlim@umich.edu traceFunctions(thread->readPC()); 4522644Sstever@eecs.umich.edu 4532644Sstever@eecs.umich.edu if (traceData) { 4544046Sbinkertn@umich.edu traceData->dump(); 4554046Sbinkertn@umich.edu delete traceData; 4564046Sbinkertn@umich.edu traceData = NULL; 4572644Sstever@eecs.umich.edu } 4582623SN/A} 4592SN/A 4602SN/A 4612623SN/Avoid 4622623SN/ABaseSimpleCPU::advancePC(Fault fault) 4632623SN/A{ 4644377Sgblack@eecs.umich.edu //Since we're moving to a new pc, zero out the offset 4654377Sgblack@eecs.umich.edu fetchOffset = 0; 4662090SN/A if (fault != NoFault) { 4673905Ssaidi@eecs.umich.edu curMacroStaticInst = StaticInst::nullStaticInstPtr; 4685120Sgblack@eecs.umich.edu predecoder.reset(); 4693929Ssaidi@eecs.umich.edu thread->setMicroPC(0); 4703929Ssaidi@eecs.umich.edu thread->setNextMicroPC(1); 4715281Sgblack@eecs.umich.edu fault->invoke(tc); 4724377Sgblack@eecs.umich.edu } else { 4733276Sgblack@eecs.umich.edu //If we're at the last micro op for this instruction 4744539Sgblack@eecs.umich.edu if (curStaticInst && curStaticInst->isLastMicroop()) { 4753276Sgblack@eecs.umich.edu //We should be working with a macro op 4763276Sgblack@eecs.umich.edu assert(curMacroStaticInst); 4773276Sgblack@eecs.umich.edu //Close out this macro op, and clean up the 4783276Sgblack@eecs.umich.edu //microcode state 4793280Sgblack@eecs.umich.edu curMacroStaticInst = StaticInst::nullStaticInstPtr; 4803276Sgblack@eecs.umich.edu thread->setMicroPC(0); 4813280Sgblack@eecs.umich.edu thread->setNextMicroPC(1); 4823276Sgblack@eecs.umich.edu } 4833276Sgblack@eecs.umich.edu //If we're still in a macro op 4843276Sgblack@eecs.umich.edu if (curMacroStaticInst) { 4853276Sgblack@eecs.umich.edu //Advance the micro pc 4863280Sgblack@eecs.umich.edu thread->setMicroPC(thread->readNextMicroPC()); 4873276Sgblack@eecs.umich.edu //Advance the "next" micro pc. Note that there are no delay 4883276Sgblack@eecs.umich.edu //slots, and micro ops are "word" addressed. 4893280Sgblack@eecs.umich.edu thread->setNextMicroPC(thread->readNextMicroPC() + 1); 4903276Sgblack@eecs.umich.edu } else { 4913276Sgblack@eecs.umich.edu // go to the next instruction 4923276Sgblack@eecs.umich.edu thread->setPC(thread->readNextPC()); 4933276Sgblack@eecs.umich.edu thread->setNextPC(thread->readNextNPC()); 4943276Sgblack@eecs.umich.edu thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst)); 4953276Sgblack@eecs.umich.edu assert(thread->readNextPC() != thread->readNextNPC()); 4963276Sgblack@eecs.umich.edu } 4972SN/A } 4982SN/A 4992SN/A Addr oldpc; 5002SN/A do { 5012683Sktlim@umich.edu oldpc = thread->readPC(); 5022680Sktlim@umich.edu system->pcEventQueue.service(tc); 5032683Sktlim@umich.edu } while (oldpc != thread->readPC()); 5042SN/A} 5052SN/A 5065250Sksewell@umich.edu/*Fault 5075222Sksewell@umich.eduBaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr) 5085222Sksewell@umich.edu{ 5095222Sksewell@umich.edu // translate to physical address 5105222Sksewell@umich.edu Fault fault = NoFault; 5115222Sksewell@umich.edu int CacheID = Op & 0x3; // Lower 3 bits identify Cache 5125222Sksewell@umich.edu int CacheOP = Op >> 2; // Upper 3 bits identify Cache Operation 5135222Sksewell@umich.edu if(CacheID > 1) 5145222Sksewell@umich.edu { 5155222Sksewell@umich.edu warn("CacheOps not implemented for secondary/tertiary caches\n"); 5165222Sksewell@umich.edu } 5175222Sksewell@umich.edu else 5185222Sksewell@umich.edu { 5195222Sksewell@umich.edu switch(CacheOP) 5205222Sksewell@umich.edu { // Fill Packet Type 5215222Sksewell@umich.edu case 0: warn("Invalidate Cache Op\n"); 5225222Sksewell@umich.edu break; 5235222Sksewell@umich.edu case 1: warn("Index Load Tag Cache Op\n"); 5245222Sksewell@umich.edu break; 5255222Sksewell@umich.edu case 2: warn("Index Store Tag Cache Op\n"); 5265222Sksewell@umich.edu break; 5275222Sksewell@umich.edu case 4: warn("Hit Invalidate Cache Op\n"); 5285222Sksewell@umich.edu break; 5295222Sksewell@umich.edu case 5: warn("Fill/Hit Writeback Invalidate Cache Op\n"); 5305222Sksewell@umich.edu break; 5315222Sksewell@umich.edu case 6: warn("Hit Writeback\n"); 5325222Sksewell@umich.edu break; 5335222Sksewell@umich.edu case 7: warn("Fetch & Lock Cache Op\n"); 5345222Sksewell@umich.edu break; 5355222Sksewell@umich.edu default: warn("Unimplemented Cache Op\n"); 5365222Sksewell@umich.edu } 5375222Sksewell@umich.edu } 5385222Sksewell@umich.edu return fault; 5395250Sksewell@umich.edu}*/ 540