base.cc revision 2663
12SN/A/*
21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
32SN/A * All rights reserved.
42SN/A *
52SN/A * Redistribution and use in source and binary forms, with or without
62SN/A * modification, are permitted provided that the following conditions are
72SN/A * met: redistributions of source code must retain the above copyright
82SN/A * notice, this list of conditions and the following disclaimer;
92SN/A * redistributions in binary form must reproduce the above copyright
102SN/A * notice, this list of conditions and the following disclaimer in the
112SN/A * documentation and/or other materials provided with the distribution;
122SN/A * neither the name of the copyright holders nor the names of its
132SN/A * contributors may be used to endorse or promote products derived from
142SN/A * this software without specific prior written permission.
152SN/A *
162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272SN/A */
282SN/A
292439SN/A#include "arch/utility.hh"
30146SN/A#include "base/cprintf.hh"
31146SN/A#include "base/inifile.hh"
32146SN/A#include "base/loader/symtab.hh"
33146SN/A#include "base/misc.hh"
34146SN/A#include "base/pollevent.hh"
35146SN/A#include "base/range.hh"
361717SN/A#include "base/stats/events.hh"
37146SN/A#include "base/trace.hh"
381717SN/A#include "cpu/base.hh"
392190SN/A#include "cpu/cpu_exec_context.hh"
40146SN/A#include "cpu/exec_context.hh"
41146SN/A#include "cpu/exetrace.hh"
421977SN/A#include "cpu/profile.hh"
431717SN/A#include "cpu/sampler/sampler.hh"
442623SN/A#include "cpu/simple/base.hh"
451717SN/A#include "cpu/smt.hh"
46146SN/A#include "cpu/static_inst.hh"
471917SN/A#include "kern/kernel_stats.hh"
482592SN/A#include "mem/packet_impl.hh"
492036SN/A#include "sim/byteswap.hh"
50146SN/A#include "sim/builder.hh"
51146SN/A#include "sim/debug.hh"
5256SN/A#include "sim/host.hh"
5356SN/A#include "sim/sim_events.hh"
5456SN/A#include "sim/sim_object.hh"
55695SN/A#include "sim/stats.hh"
562SN/A
571858SN/A#if FULL_SYSTEM
5856SN/A#include "base/remote_gdb.hh"
59146SN/A#include "sim/system.hh"
602171SN/A#include "arch/tlb.hh"
612170SN/A#include "arch/stacktrace.hh"
622170SN/A#include "arch/vtophys.hh"
63146SN/A#else // !FULL_SYSTEM
642462SN/A#include "mem/mem_object.hh"
65146SN/A#endif // FULL_SYSTEM
662SN/A
672SN/Ausing namespace std;
682449SN/Ausing namespace TheISA;
691355SN/A
702623SN/ABaseSimpleCPU::BaseSimpleCPU(Params *p)
712623SN/A    : BaseCPU(p), mem(p->mem), cpuXC(NULL)
72224SN/A{
731858SN/A#if FULL_SYSTEM
742518SN/A    cpuXC = new CPUExecContext(this, 0, p->system, p->itb, p->dtb);
752420SN/A#else
762519SN/A    cpuXC = new CPUExecContext(this, /* thread_num */ 0, p->process,
772520SN/A            /* asid */ 0, mem);
782420SN/A#endif // !FULL_SYSTEM
792SN/A
802190SN/A    xcProxy = cpuXC->getProxy();
812SN/A
822SN/A    numInst = 0;
83334SN/A    startNumInst = 0;
84140SN/A    numLoad = 0;
85334SN/A    startNumLoad = 0;
862SN/A    lastIcacheStall = 0;
872SN/A    lastDcacheStall = 0;
882SN/A
892190SN/A    execContexts.push_back(xcProxy);
902SN/A}
912SN/A
922623SN/ABaseSimpleCPU::~BaseSimpleCPU()
932SN/A{
942SN/A}
952SN/A
96180SN/Avoid
972623SN/ABaseSimpleCPU::deallocateContext(int thread_num)
98393SN/A{
99393SN/A    // for now, these are equivalent
100393SN/A    suspendContext(thread_num);
101393SN/A}
102384SN/A
103384SN/A
104393SN/Avoid
1052623SN/ABaseSimpleCPU::haltContext(int thread_num)
106393SN/A{
107393SN/A    // for now, these are equivalent
108393SN/A    suspendContext(thread_num);
109393SN/A}
110384SN/A
111189SN/A
112189SN/Avoid
1132623SN/ABaseSimpleCPU::regStats()
1142SN/A{
115729SN/A    using namespace Stats;
116334SN/A
1172SN/A    BaseCPU::regStats();
1182SN/A
1192SN/A    numInsts
1202SN/A        .name(name() + ".num_insts")
1212SN/A        .desc("Number of instructions executed")
1222SN/A        ;
1232SN/A
1242SN/A    numMemRefs
1252SN/A        .name(name() + ".num_refs")
1262SN/A        .desc("Number of memory references")
1272SN/A        ;
1282SN/A
1291001SN/A    notIdleFraction
1301001SN/A        .name(name() + ".not_idle_fraction")
1311001SN/A        .desc("Percentage of non-idle cycles")
1321001SN/A        ;
1331001SN/A
1342SN/A    idleFraction
1352SN/A        .name(name() + ".idle_fraction")
1362SN/A        .desc("Percentage of idle cycles")
1372SN/A        ;
1382SN/A
1392SN/A    icacheStallCycles
1402SN/A        .name(name() + ".icache_stall_cycles")
1412SN/A        .desc("ICache total stall cycles")
1422SN/A        .prereq(icacheStallCycles)
1432SN/A        ;
1442SN/A
1452SN/A    dcacheStallCycles
1462SN/A        .name(name() + ".dcache_stall_cycles")
1472SN/A        .desc("DCache total stall cycles")
1482SN/A        .prereq(dcacheStallCycles)
1492SN/A        ;
1502SN/A
1512390SN/A    icacheRetryCycles
1522390SN/A        .name(name() + ".icache_retry_cycles")
1532390SN/A        .desc("ICache total retry cycles")
1542390SN/A        .prereq(icacheRetryCycles)
1552390SN/A        ;
1562390SN/A
1572390SN/A    dcacheRetryCycles
1582390SN/A        .name(name() + ".dcache_retry_cycles")
1592390SN/A        .desc("DCache total retry cycles")
1602390SN/A        .prereq(dcacheRetryCycles)
1612390SN/A        ;
1622390SN/A
163385SN/A    idleFraction = constant(1.0) - notIdleFraction;
1642SN/A}
1652SN/A
1662SN/Avoid
1672623SN/ABaseSimpleCPU::resetStats()
168334SN/A{
169334SN/A    startNumInst = numInst;
1702623SN/A    // notIdleFraction = (_status != Idle);
171334SN/A}
172334SN/A
173334SN/Avoid
1742623SN/ABaseSimpleCPU::serialize(ostream &os)
1752SN/A{
176921SN/A    BaseCPU::serialize(os);
177224SN/A    SERIALIZE_SCALAR(inst);
178237SN/A    nameOut(os, csprintf("%s.xc", name()));
1792190SN/A    cpuXC->serialize(os);
1802SN/A}
1812SN/A
1822SN/Avoid
1832623SN/ABaseSimpleCPU::unserialize(Checkpoint *cp, const string &section)
1842SN/A{
185921SN/A    BaseCPU::unserialize(cp, section);
186224SN/A    UNSERIALIZE_SCALAR(inst);
1872190SN/A    cpuXC->unserialize(cp, csprintf("%s.xc", section));
1882SN/A}
1892SN/A
1902SN/Avoid
1912SN/Achange_thread_state(int thread_number, int activate, int priority)
1922SN/A{
1932SN/A}
1942SN/A
195595SN/AFault
1962623SN/ABaseSimpleCPU::copySrcTranslate(Addr src)
197595SN/A{
1982390SN/A#if 0
1991080SN/A    static bool no_warn = true;
2001080SN/A    int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
2011080SN/A    // Only support block sizes of 64 atm.
2021080SN/A    assert(blk_size == 64);
2031080SN/A    int offset = src & (blk_size - 1);
2041080SN/A
2051080SN/A    // Make sure block doesn't span page
2061121SN/A    if (no_warn &&
2072107SN/A        (src & PageMask) != ((src + blk_size) & PageMask) &&
2081089SN/A        (src >> 40) != 0xfffffc) {
2091089SN/A        warn("Copied block source spans pages %x.", src);
2101080SN/A        no_warn = false;
2111080SN/A    }
2121080SN/A
2131080SN/A    memReq->reset(src & ~(blk_size - 1), blk_size);
214595SN/A
2152623SN/A    // translate to physical address
2162623SN/A    Fault fault = cpuXC->translateDataReadReq(req);
217595SN/A
2182090SN/A    if (fault == NoFault) {
2192190SN/A        cpuXC->copySrcAddr = src;
2202190SN/A        cpuXC->copySrcPhysAddr = memReq->paddr + offset;
221595SN/A    } else {
2222205SN/A        assert(!fault->isAlignmentFault());
2232205SN/A
2242190SN/A        cpuXC->copySrcAddr = 0;
2252190SN/A        cpuXC->copySrcPhysAddr = 0;
226595SN/A    }
227595SN/A    return fault;
2282390SN/A#else
2292423SN/A    return NoFault;
2302390SN/A#endif
231595SN/A}
232595SN/A
233595SN/AFault
2342623SN/ABaseSimpleCPU::copy(Addr dest)
235595SN/A{
2362390SN/A#if 0
2371080SN/A    static bool no_warn = true;
238595SN/A    int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
2391080SN/A    // Only support block sizes of 64 atm.
2401080SN/A    assert(blk_size == 64);
241595SN/A    uint8_t data[blk_size];
2422190SN/A    //assert(cpuXC->copySrcAddr);
2431080SN/A    int offset = dest & (blk_size - 1);
2441080SN/A
2451080SN/A    // Make sure block doesn't span page
2461121SN/A    if (no_warn &&
2472107SN/A        (dest & PageMask) != ((dest + blk_size) & PageMask) &&
2481089SN/A        (dest >> 40) != 0xfffffc) {
2491080SN/A        no_warn = false;
2501089SN/A        warn("Copied block destination spans pages %x. ", dest);
2511080SN/A    }
2521080SN/A
2531080SN/A    memReq->reset(dest & ~(blk_size -1), blk_size);
254595SN/A    // translate to physical address
2552422SN/A    Fault fault = cpuXC->translateDataWriteReq(req);
2561080SN/A
2572090SN/A    if (fault == NoFault) {
2581080SN/A        Addr dest_addr = memReq->paddr + offset;
259595SN/A        // Need to read straight from memory since we have more than 8 bytes.
2602190SN/A        memReq->paddr = cpuXC->copySrcPhysAddr;
2612190SN/A        cpuXC->mem->read(memReq, data);
262595SN/A        memReq->paddr = dest_addr;
2632190SN/A        cpuXC->mem->write(memReq, data);
2641098SN/A        if (dcacheInterface) {
2651098SN/A            memReq->cmd = Copy;
2661098SN/A            memReq->completionEvent = NULL;
2672190SN/A            memReq->paddr = cpuXC->copySrcPhysAddr;
2681098SN/A            memReq->dest = dest_addr;
2691098SN/A            memReq->size = 64;
2701098SN/A            memReq->time = curTick;
2712012SN/A            memReq->flags &= ~INST_READ;
2721098SN/A            dcacheInterface->access(memReq);
2731098SN/A        }
274595SN/A    }
2752205SN/A    else
2762205SN/A        assert(!fault->isAlignmentFault());
2772205SN/A
278595SN/A    return fault;
2792390SN/A#else
2802420SN/A    panic("copy not implemented");
2812423SN/A    return NoFault;
2822390SN/A#endif
283595SN/A}
284595SN/A
2851858SN/A#if FULL_SYSTEM
2862SN/AAddr
2872623SN/ABaseSimpleCPU::dbg_vtophys(Addr addr)
2882SN/A{
2892190SN/A    return vtophys(xcProxy, addr);
2902SN/A}
2912SN/A#endif // FULL_SYSTEM
2922SN/A
2931858SN/A#if FULL_SYSTEM
2942SN/Avoid
2952623SN/ABaseSimpleCPU::post_interrupt(int int_num, int index)
2962SN/A{
2972SN/A    BaseCPU::post_interrupt(int_num, index);
2982SN/A
2992190SN/A    if (cpuXC->status() == ExecContext::Suspended) {
3002SN/A                DPRINTF(IPI,"Suspended Processor awoke\n");
3012190SN/A        cpuXC->activate();
3022SN/A    }
3032SN/A}
3042SN/A#endif // FULL_SYSTEM
3052SN/A
3062SN/Avoid
3072623SN/ABaseSimpleCPU::checkForInterrupts()
3082SN/A{
3091858SN/A#if FULL_SYSTEM
3102626SN/A    if (checkInterrupts && check_interrupts() && !cpuXC->inPalMode()) {
3112SN/A        int ipl = 0;
3122SN/A        int summary = 0;
3131133SN/A        checkInterrupts = false;
3142SN/A
3152190SN/A        if (cpuXC->readMiscReg(IPR_SIRR)) {
3162107SN/A            for (int i = INTLEVEL_SOFTWARE_MIN;
3172107SN/A                 i < INTLEVEL_SOFTWARE_MAX; i++) {
3182190SN/A                if (cpuXC->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
3192SN/A                    // See table 4-19 of 21164 hardware reference
3202107SN/A                    ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
3212SN/A                    summary |= (ULL(1) << i);
3222SN/A                }
3232SN/A            }
3242SN/A        }
3252SN/A
3262190SN/A        uint64_t interrupts = cpuXC->cpu->intr_status();
3272107SN/A        for (int i = INTLEVEL_EXTERNAL_MIN;
3282107SN/A            i < INTLEVEL_EXTERNAL_MAX; i++) {
3292SN/A            if (interrupts & (ULL(1) << i)) {
3302SN/A                // See table 4-19 of 21164 hardware reference
3312SN/A                ipl = i;
3322SN/A                summary |= (ULL(1) << i);
3332SN/A            }
3342SN/A        }
3352SN/A
3362190SN/A        if (cpuXC->readMiscReg(IPR_ASTRR))
3372SN/A            panic("asynchronous traps not implemented\n");
3382SN/A
3392190SN/A        if (ipl && ipl > cpuXC->readMiscReg(IPR_IPLR)) {
3402190SN/A            cpuXC->setMiscReg(IPR_ISR, summary);
3412190SN/A            cpuXC->setMiscReg(IPR_INTID, ipl);
3422234SN/A
3432234SN/A            Fault(new InterruptFault)->invoke(xcProxy);
3442SN/A
3452SN/A            DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
3462190SN/A                    cpuXC->readMiscReg(IPR_IPLR), ipl, summary);
3472SN/A        }
3482SN/A    }
3492SN/A#endif
3502623SN/A}
3512SN/A
3522623SN/A
3532623SN/AFault
3542662Sstever@eecs.umich.eduBaseSimpleCPU::setupFetchRequest(Request *req)
3552623SN/A{
3562623SN/A    // set up memory request for instruction fetch
3572623SN/A    DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",cpuXC->readPC(),
3582623SN/A            cpuXC->readNextPC(),cpuXC->readNextNPC());
3592623SN/A
3602663Sstever@eecs.umich.edu    req->setVirt(0, cpuXC->readPC() & ~3, sizeof(MachInst),
3612663Sstever@eecs.umich.edu                 (FULL_SYSTEM && (cpuXC->readPC() & 1)) ? PHYSICAL : 0,
3622663Sstever@eecs.umich.edu                 cpuXC->readPC());
3632623SN/A
3642662Sstever@eecs.umich.edu    Fault fault = cpuXC->translateInstReq(req);
3652623SN/A
3662623SN/A    return fault;
3672623SN/A}
3682623SN/A
3692623SN/A
3702623SN/Avoid
3712623SN/ABaseSimpleCPU::preExecute()
3722623SN/A{
3732SN/A    // maintain $r0 semantics
3742190SN/A    cpuXC->setIntReg(ZeroReg, 0);
3752427SN/A#if THE_ISA == ALPHA_ISA
3762455SN/A    cpuXC->setFloatReg(ZeroReg, 0.0);
3772427SN/A#endif // ALPHA_ISA
3782SN/A
3792623SN/A    // keep an instruction count
3802623SN/A    numInst++;
3812623SN/A    numInsts++;
3822SN/A
3832623SN/A    cpuXC->func_exe_inst++;
3842SN/A
3852623SN/A    // check for instruction-count-based events
3862623SN/A    comInstEventQueue[0]->serviceEvents(numInst);
3872SN/A
3882623SN/A    // decode the instruction
3892623SN/A    inst = gtoh(inst);
3902623SN/A    curStaticInst = StaticInst::decode(makeExtMI(inst, cpuXC->readPC()));
3912470SN/A
3922623SN/A    traceData = Trace::getInstRecord(curTick, xcProxy, this, curStaticInst,
3932623SN/A                                     cpuXC->readPC());
3942623SN/A
3952623SN/A    DPRINTF(Decode,"Decode: Decoded %s instruction (opcode: 0x%x): 0x%x\n",
3962623SN/A            curStaticInst->getName(), curStaticInst->getOpcode(),
3972623SN/A            curStaticInst->machInst);
3982623SN/A
3992623SN/A#if FULL_SYSTEM
4002623SN/A    cpuXC->setInst(inst);
4012623SN/A#endif // FULL_SYSTEM
4022623SN/A}
4032623SN/A
4042623SN/Avoid
4052623SN/ABaseSimpleCPU::postExecute()
4062623SN/A{
4072623SN/A#if FULL_SYSTEM
4082623SN/A    if (system->kernelBinning->fnbin) {
4092623SN/A        assert(kernelStats);
4102623SN/A        system->kernelBinning->execute(xcProxy, inst);
4112623SN/A    }
4122623SN/A
4132623SN/A    if (cpuXC->profile) {
4142623SN/A        bool usermode =
4152623SN/A            (cpuXC->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
4162623SN/A        cpuXC->profilePC = usermode ? 1 : cpuXC->readPC();
4172623SN/A        ProfileNode *node = cpuXC->profile->consume(xcProxy, inst);
4182623SN/A        if (node)
4192623SN/A            cpuXC->profileNode = node;
4202623SN/A    }
4212420SN/A#endif
4222SN/A
4232623SN/A    if (curStaticInst->isMemRef()) {
4242623SN/A        numMemRefs++;
4252SN/A    }
4262SN/A
4272623SN/A    if (curStaticInst->isLoad()) {
4282623SN/A        ++numLoad;
4292623SN/A        comLoadEventQueue[0]->serviceEvents(numLoad);
4302623SN/A    }
4312SN/A
4322623SN/A    traceFunctions(cpuXC->readPC());
4332644Sstever@eecs.umich.edu
4342644Sstever@eecs.umich.edu    if (traceData) {
4352644Sstever@eecs.umich.edu        traceData->finalize();
4362644Sstever@eecs.umich.edu    }
4372623SN/A}
4382SN/A
4392SN/A
4402623SN/Avoid
4412623SN/ABaseSimpleCPU::advancePC(Fault fault)
4422623SN/A{
4432090SN/A    if (fault != NoFault) {
4441858SN/A#if FULL_SYSTEM
4452234SN/A        fault->invoke(xcProxy);
4462SN/A#else // !FULL_SYSTEM
4472470SN/A        fatal("fault (%s) detected @ PC %08p", fault->name(), cpuXC->readPC());
4482SN/A#endif // FULL_SYSTEM
4492SN/A    }
4502SN/A    else {
4512SN/A        // go to the next instruction
4522190SN/A        cpuXC->setPC(cpuXC->readNextPC());
4532623SN/A#if THE_ISA == ALPHA_ISA
4542190SN/A        cpuXC->setNextPC(cpuXC->readNextPC() + sizeof(MachInst));
4552251SN/A#else
4562262SN/A        cpuXC->setNextPC(cpuXC->readNextNPC());
4572262SN/A        cpuXC->setNextNPC(cpuXC->readNextNPC() + sizeof(MachInst));
4582251SN/A#endif
4592251SN/A
4602SN/A    }
4612SN/A
4621858SN/A#if FULL_SYSTEM
4632SN/A    Addr oldpc;
4642SN/A    do {
4652190SN/A        oldpc = cpuXC->readPC();
4662190SN/A        system->pcEventQueue.service(xcProxy);
4672190SN/A    } while (oldpc != cpuXC->readPC());
4682SN/A#endif
4692SN/A}
4702SN/A
471